Dynamic Memory Dependence Predication
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1 Dynamic Memory Dependence Predication Zhaoxiang Jin and Soner Önder ISCA-2018, Los Angeles
2 Background 1. Store instructions do not update the cache until they are retired (too late). 2. Store queue is implemented to keep the speculative store instructions before they are retired. 3. Load instructions need to associatively search the store queue to have an early execution.
3 Store Queue Design SW1 SW2 SW3 LW The addresses match. The store has to be older than the load. If there are multiple matching stores, the youngest store is selected. SW4 Store Queue
4 Store Queue Design SW1 SW2 LW SW3 The addresses are matching. The store has to be older than the load. If there are multiple matching stores, the youngest store is selected. Due to the hardware complexity, store queue does not scale well. SW4 Store Queue
5 Store-Queue-Free Architecture SW1 SW2 : SW $9(P10), 0 ($7) SW3 LW : LW $6, 0 ($8) Memory Dependence Prediction The DEF-store-load-USE dependence is collapsed to the DEF-USE. SW4 P10 (Memory Cloaking)
6 Store-Queue-Free Architecture SW1 SW2 : SW $9(P10), 0 ($7) If the memory dependence prediction is wrong, a misspeculation recovery is launched. SW3 LW : LW $6, 0 ($8) SW4 P10 (Memory Cloaking)
7 Store-Queue-Free Architecture SW1 SW2 : SW $9(P10), 0 ($7) If the memory dependence prediction is wrong, a misspeculation recovery is launched. If a load is frequently mispredicted, it is marked as a low confidence load. SW3 LW : LW $6, 0 ($8) SW4 P10 (Memory Cloaking)
8 Store-Queue-Free Architecture SW1 SW2 : SW $9(P10), 0 ($7) SW3 LW : LW $6, 0 ($8) If the memory dependence prediction is wrong, a misspeculation recovery is launched. If a load is frequently mispredicted, it is marked as a low confidence load. A low confidence load only gets its data from the cache. Therefore, it has to wait for the predicted store (SW2) retires and updates the cache (too late). SW4 P10 (Memory Cloaking)
9 Store-Queue-Free Architecture SW1 SW2 : SW $9(P10), 0 ($7) SW3 LW : LW $6, 0 ($8) SW4 P10 (Memory Cloaking) If the memory dependence prediction is wrong, a misspeculation recovery is launched. If a load is frequently mispredicted, it is marked as a low confidence load. A low confidence load only gets its data from the cache. Therefore, it has to wait for the predicted store (SW2) retires and updates the cache (too late). Low confidence loads are kept in a special buffer where they are selected to execute once their predicted stores retire.
10 Load instruction distribution 6.98% 14.27% 78.75% Direct access Read data from the cache. Bypassing Rename the destination register with the store register (memory cloaking). Delayed access Do not read the cache until the store is retired (low confidence).
11 Delayed access VS. Bypassing If the number is greater than zero, that means the delayed access load instructions take more cycles to execute. Average execution time comparison
12 Dynamic Memory Dependence Predication SW1 SW2 : SW $9, 0 ($7) DMDP SW3 ==? Data Cache LW : LW $6, 0 ($8) SW4
13 Dynamic Memory Dependence Predication SW1 SW2 : SW $9, 0 ($7) DMDP SW3 ==? Data Cache LW : LW $6, 0 ($8) SW4 CMP $32, $7, $8
14 Dynamic Memory Dependence Predication SW1 SW2 : SW $9, 0 ($7) $33 DMDP SW3 ==? Data Cache LW : LW $6, 0 ($8) SW4 CMP $32, $7, $8 LW $33, 0($8)
15 Dynamic Memory Dependence Predication SW1 SW2 : SW $9, 0 ($7) $33 DMDP SW3 ==? Data Cache LW : LW $6, 0 ($8) SW4 CMP $32, $7, $8 LW $33, 0($8) CMOV $6, $32, $9 CMOV $6,!$32, $33
16 Real dependence DMDP can also mispredict dependence SW1 SW2 : SW $9, 0 ($7) DMDP SW3 ==? Data Cache LW : LW $6, 0 ($8) SW4
17 DMDP can also mispredict dependence When a predicate is inserted for a load instruction: 1. The load depends on the predicted store 2. The load does not depend on any in-flight store 3. The load depends on a different store
18 Memory dependence prediction results over low confidence loads 7.7% 3.7% 88.6% IndepStore The load is independent of any in-flight store. DiffStore The load is dependent on a different store. Correct The prediction is right.
19 Memory dependence prediction results over low confidence loads 7.7% 3.7% 88.6% IndepStore The load is independent of any in-flight store. DiffStore The load is dependent on a different store. Correct The prediction is right. DMDP can cover IndepStore (88.6%) and Correct (7.7%), only DiffStore (3.7% low confidence loads) is not covered.
20 Simulation configuration ROB / RS / PRF 256 / 64 / 320 Fetch / Decode / Issue 8 / 8 / 8 Store Queue (baseline) Store Buffer Cache Memory Recovery penalty Int ALU / Int MUL Int DIV, FP ALU Branch predictor Tech node Clock frequency Unlimited entries, 4 cycles latency 16 entries, store coalesce 32kB 8-way set associative, 4 cycles hit latency, 2 read ports, 1 write port, il1, dl1; 512kB 8-way set associative, 10 cycles hit latency L2 16GB DDR3L-1600, 2 channels, 2 ranks, 8 banks, open page, up to 64 pending request Minimum 15 cycles 1 cycles / 3 cycles 7 cycles 8kB TAGE 22nm 3.2GHz 1. Baseline : a superscalar processor with unlimited store queue entries, using store-set to resolve memory dependence prediction. 2. NoSQ : the store-queue-free architecture. 3. DMDP : dynamic memory dependence predication. 4. Perfect : NoSQ + perfect memory dependence predictor.
21 Evaluation results IPC normalized to the baseline
22 Evaluation results Average execution time for low confidence loads is significantly reduced (DMDP VS. NoSQ). hmmer cycles -> 8.91 cycles wrf cycles -> cycles IPC normalized to the baseline
23 Evaluation results DMDP still encounters some memory dependence mispredictions in some benchmarks bzip MPKI hmmer MPKI (Mispredictions Per 1k retired instructions) IPC normalized to the baseline
24 Energy Delay Product Reducing the execution time. 2. Fewer memory dependence mispredictions means fewer misprediction recoveries. EDP normalized to NoSQ
25 Conclusion 1. DMDP is the first mechanism to use predication for memory dependence handling. 2. The storage for maintaining the low confidence loads is completely removed. 3. The memory dependence is translated to register dependence and will be checked in the reservation station.
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