Multigig Lossless Data Compression Device

Transcription

1 R. Mehboob et al.: Multigig Lossless Data Compression Device 1927 Multigig Lossless Data Compression Device Rizwana Mehboob, Shoab A. Khan, Zaheer Ahmed, Habibullah Jamal, and Muhammad Shahbaz Abstract This paper presents a novel lossless data compression device that extends enterprise network to branch offices by integrating multiple communication technologies. The presented device incorporates Gigabit Ethernet, STM1/STM4/STM16 interfaces for WAN connectivity, fiber channel interfaces for storage area network and 10G Ethernet interface for enterprise network connectivity. The device implements a novel architecture that implements the LZ77 lossless data compression algorithm in hardware. The high throughput data compression architecture enables the interfacing of the diverse high-speed communication technologies besides preserving the channel bandwidth for accommodating multiple applications. The device finds consumer applications to optimize WAN bandwidth, healthcare, media & broadcasting and storage area networks (SAN). 1 Index Terms Lossless Data Compression, WAN Optimization, LZ77 lossless data compression, Storage Area Network (SAN) I. INTRODUCTION With the advent of the Internet technology, there has been a significant increase in the information sharing and exchange over wide area network (WAN). The small to medium scale businesses are also making best use of the technological advancement thus necessitating the mushrooming of the corporate Information Technology (IT). The public as well as the private companies are establishing readily deployable branch offices for providing 24/7 customer services to the clients. The corporate head offices as well as the branch offices have to share voice, data and video information over a geographically dispersed locations making use of the WAN technologies. Similarly, for local data, audio and video sharing within the branch offices, multiple wired and wireless local area networks (WLAN) technologies are incorporated. The magnitude of Internet usage has accelerated significantly over the past few decades, with networking becoming the preferred tool for business and communications. Enormous amount of data is stored or retrieved from laptops, desktops or 1 The research was carried out in CASE Pakistan Rizwana Mehboob is with the Computer Engineering Department, Center for Advanced Studies in Engineering (CASE) Pakistan ( rizwanamehboob@hotmail.com). Shoab Khan is with the Computer Engineering Department, Center for Advanced Studies in Engineering Pakistan ( shoab@case.edu.pk). Zaheer Ahmed is with the University of Engineering and Technology Taxila, Pakistan ( zah67@yahoo.com). Habibullah Jamal is with the University of Engineering and Technology Taxila, Pakistan ( drhjamal@uettaxila.edu.pk). Muhammad Shahbaz is with Center for Advanced Research in Engineering Pakistan ( m.shahbaz.ahmed@hotmail.com) Contributed Paper Manuscript received 07/15/10 Current version published 09/23/10 Electronic version published 09/30/ /10/$ IEEE network area storage (NAS). Similarly, huge data transaction has to be transmitted over a wired or a wireless channel. Efficient bandwidth utilization of a communication channel has always been a subject of research. The voluminous data has the capacity to saturate the WAN links and thus results in the degradation of the transmission channel and causes IP traffic congestion. In order to offset the network congestion, companies purchase the expensive additional bandwidth from carriers. Data compression is a technique for minimizing the bandwidth requirements by injecting smaller amount of data on the communication channel. Thus incorporation of data compression optimizes the channel bandwidth. Data compression is a method of encoding data with fewer bits by removing data redundancies before storage or transmission and then reinserting them by decompression process for retrieval or reception of data. Therefore, it is a method of digital data transfer such that the requirements of data storage and transmission are minimized. Data compression is also applied before encryption for providing significantly effective security, and in multi-gigabit networks data compression offsets the low-bandwidth problems [1]. The lossless data compression ensures that the data at the source and destination is exactly identical. The financial transactions, accounts, executable codes and flight reservation are examples of systems requiring lossless data compression. It is further broadly classified as statistical and dictionary based methods. The statistical methods like Arithmetic coding [2], Huffman coding [3], Run-length coding [4] captures redundancies based on symbol probabilities and apriori information of the source is required. The statistical techniques are well suited for sources where data is predictable or consistent, but these methods being typically non-adaptive, do not perform well in data communications because the network traffic is neither predictable nor consistent. Similarly, these methods are also not appropriate for hardware implementations in achieving high throughputs for real-time communication and high density data storage applications [5, 6]. On the other hand the adaptive dictionary based methods like LZ77 or LZ1 [7], LZ2 or its variant LZW [8] or their modified versions provide a better compression ratio when neither the prior knowledge nor the source statistics are known. These are classified as variable to block coders in which a dictionary of certain length of input symbols is maintained and the repeated strings of characters in the input data stream are replaced by the shorter code words. The dictionary based techniques are high speed encoders since they code several symbols at a time and are best suited to hardware implementations. This paper presents a high-speed architecture based on LZ77 algorithm for hardware implementation on an FPGA providing multi-gigabit throughput of data. In literature,

2 1928 IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, August 2010 different approaches exist for hardware implementation of LZ77 or its variants. The Content Addressable Memories (CAMS) speed up the string matching time by providing parallel lookups for repeating strings of input data in the dictionaries and fast comparisons lead to high speed compression [9][10]. The CAMs require high power consumption for higher speed and are very expensive. In the systolic arrays approach, a regular pattern of processing elements are interconnected in a simple way; and each processing element is connected to its adjacent element for carrying out simple tasks [11][12]. The complexity of the systolic array is a limitation for its widespread use and suffers from long latency in compression and decompression. Another method is the use of RISC processor [13], but the processing speed of this approach makes it unsuitable for hardware realizations. Therefore for very high throughput realization, standalone accelerator is one way of realizing the hardware compression based on LZ77 algorithm [1][6][14]. In this paper we extend the concept of our previous research [15][16][4] and propose multiple lossless data compression architectures that are embedded in the device for diverse data compression application on multiple interfaces. This paper is divided in six sections. The top level architecture of compression device is discussed in section 2. Section 3 describes the enterprise network architecture to incorporate compression device. Design methodology for hardware implementation is discussed in section 4. Results are discussed in Section 5 and Section 6 concludes the paper. II. TOP LEVEL ARCHITECTURE The top level architecture of the multi-gig compression device is shown in Figure 1. The device is equipped with multiple communication interfaces for LAN, WAN and SAN connectivity. The 10G Ethernet interface is provided to connect the device on the enterprise LAN. Two 100/1000 Ethernet interfaces are provided to extend the enterprise network to branch offices. Two SFP interfaces are embedded in the device to connect STM1/STM4/STM16 lines either to connect the remote offices or to interface the SAN on fiber channel protocol. The interconnect routing layer exchanges data between interfaces. Specially designed packet Queues are incorporated to minimize the delays. The configuration and management interface is employed to configure communication interfaces, packet queue sizes and compression parameters. Different architectures of compressor are presented to handle multiple channels and varying data rates. The device can be configured to act as a multi-gig compression device to compress/ de-compress the 10Gbps data for backup and recovery in the SAN. III. ENTERPRISE NETWORK ARCHITECTURE Data compression technique maximizes bandwidth and increases WAN link throughput by reducing frame size and thereby allowing more data to be transmitted over a link. This feature enables network managers to increase application performance and service availability for end users without costly infrastructure upgrades. Data compression enables network service providers to maximize available bandwidth and deliver more services to customers over their existing infrastructure. With the widespread use of the branch offices that serve as the actual development centers, the need for compression devices to accelerate data across the WAN becomes more critical. The architecture for enterprise network extension to branch offices is shown in Figure 2. Figure 1: Top Level Architecture of Compression Device Figure 2: Optimized Enterprise network Extension for Mobile Branch Offices

3 R. Mehboob et al.: Multigig Lossless Data Compression Device 1929 The two portable branch offices are connected with the corporate head quarter through WAN communication link. Each branch office LAN is connected with the WAN through the compression device. Similarly the corporate headquarter also incorporates compression device to extend the enterprise network to branch offices. An enterprise with several branch offices requires multi-gig compression device to handle requests from all the static and the mobile branch offices at the main data center. In our research we propose different architectures with varying data rates for branch offices and enterprise network concentration points. The compression ratio or factor by which the compression architecture reduces the size of the data depends on the type of the data transmitted. For example, the ASCII text, which is inefficient in its use of bits, is highly compressible, whereas Secure Sockets Layer (SSL) encrypted traffic, which is intentionally obfuscated to have less repeatable data patterns, is less compressible. IV. HARDWARE IMPLEMENTATION The architectures for hardware implementation of a variant of LZ77 lossless data compression algorithm is presented in this section that provides the throughputs of the order of few giga-bits/secs. The architectures are scalable and configurable according to the requirements of application. The approaches for hardware implementation have been discussed in section I. The LZ77 de-compressor is also embedded in the proposed device but its implementation is very simple. We will therefore concentrate on the compressor design only. In this section, we present the fully parallel hardware architectures capable of providing user selectable throughputs depending upon the requirement. A. Applying the Compression Algorithm In this subsection, we will discuss or the LZ77 based compression algorithm (a variant of LZ77) as discussed in [17]. The algorithm is based on the principle of sliding window of length N that comprises of two buffers; the history buffer of length L is initially filled with zeros and holds the currently encoded symbols. The look-ahead or search buffer of length M symbols holds the input search string that is yet to be encoded. The look-ahead buffer s M symbols are searched in the history buffer of length L=N- M. The longest match length (len) beginning at first symbol of look-ahead buffer with the symbols in the history buffer is sought by means of a sequential searching. The starting position of longest match (pntr) forms the pointer to the longest match. The last symbol (lsymb) in look-ahead buffer after the longest match is also used to form a codeword. The codeword is formed by concatenating the pntr, len and lsym. Consider a data string S= of alphabet set of 3 symbols (0,1,2); in the example, M= 9, N = 18; longest match of the string starting at the first position of the look-ahead buffer is found in the search buffer. In Figure 3, longest match is a string of 3 symbols 000 of length 3. The position 8 in base 10 (22 in base 3 i.e 8 10 =22 3 ) is chosen as a pointer where the match started, length of the match is 3 (3 10 =10 3 ) and last symbol after the match is 1. So the first code word (pntr len lsym) is ( ). The other codes derived likewise are shown in Figure 3. After forming the code, history buffer is shifted by length+1 positions on left and look-ahead buffer is filled with symbols from right with input data. As data is being encoded, the window slides along, removing the oldest encoded data from the window and adding newly encoded data to it Figure 3: LZ77 based Compression Process C 1 = C 2 = C 3 = C 4 = For best compression performance, the experimental studies show that L may vary from 8 to 32 and the history buffer can be of 32K maximum size and beyond this, the performance degrades [18]. B. Comparator Optimization in Parallel Comparisons In our approach, for high throughput; we make use of the parallel comparisons. Consider N=8, L=4 and M=4. The history buffer of L symbols is designated as x and search buffer symbols are termed as y. All the possible comparisons of the search buffer symbols (y0 y1 y2 y3) with that of the history buffer (x 0 x 1 x 2 x 3 ) are shown in first column of the Table 1. Table 1: Parallel Comparisons Col1 Col2 Col3 Col4 Col5 Col6 x 0 x 1 x 2 x 3 x 1 x 2 x 3 y 0 x 2 x 3 y 0 y 1 x 1 x 2 x 3 y 0 x 2 x 3 y 0 y 1 x 2 x 3 y 0 y 1 y 4 y 5 y 6 y 7 The entire search buffer is compared to the already encoded buffer in a single clock cycle. It therefore provides a maximum of N+1 bytes of encoding in a single clock

4 1930 IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, August 2010 cycle by implementing only one column of the Table 1. The columns 2 to column 6 show that the algorithm is unfolded six times. As seen in the table, only first column requires four comparators (shown in black) for each row, all other columns require only one comparator (shown in black) in each row. The results of first three symbols comparisons shown in blue colour from col 2 to col 6, are already available from the preceding column. Therefore by unfolding the algorithm, we can encode future strings based on the unfolding level. The redundant comparisons are also best understood by the comparison matrix as shown in Figure 4. The advantage gained in this architecture is that results are available in one clock cycle. If there is stringent constraint of area, the degree of parallelism can be reduced with the trade off of lesser speed and throughput. The Figure 4 exhibits 36 essential comparisons shown by black dots out of a total of 96 comparisons, if six iterations of the algorithm are considered. With the degree of unfolding shown, we can at best encode 2M+2 symbols in a single cycle or produce 2 code words. Additional hardware provides a higher degree of parallelism, therefore ensuring better data rates. Figure 5: Best Match and Pointer Calculation Logic The BMPC forms the basic compression block of our design and in the block form it is shown in Figure 6. A block of 4x4 comparisons is shown while the architecture can employ any length of block sizes e.g. 16x4, 1024x32 and 16Kx32 etc. The first number in the block represents the history buffer length while the second number of the block stands for the search or the look ahead buffer length. Figure 4: Comparison Matrix C. Best Match and Pointer Calculation The designed architecture provides automatic selection of the maximum match of symbols of look-ahead buffer with the symbols of history buffer and their match length. The beginning of the maximum match i.e. the location in history buffer from where the maximum match commenced is termed as pntr. Similarly, the length of this match is referred to as len. The logic for computing len and pntr in a column is referred to as best Match and Pointer Calculator (BMPC) logic as shown in Figure 5. The BMPC is done for a single column of Table 1; other columns calculate their respective BMPC s. Simultaneous comparisons of M by L symbols are done and this forms a basic compression block of our architecture. Figure 6: Best Match & Pointer Calculation Block D. High Throughput Architectures The building blocks for finalizing the high throughput architectures have been discussed in the preceding subsections. The first architecture is shown in Figure 7. This is an extension of high speed single stream pipelined architecture.

5 R. Mehboob et al.: Multigig Lossless Data Compression Device 1931 Figure 7: High Speed Multiple Stream Pipelined Architecture. In this architecture, pipelining is done by introducing the registers for storing the intermediate results of best matched lengths and pointers. This particular architecture introduces initial latency but produces sufficient throughputs for the required applications. Only a single column of Table 1 is incorporated for parallel comparisons. For a single column MxL comparisons (L=length of history buffer, M=length of search buffer) are required. For example if L=8 and M=4, 32 comparisons are required; the initial comparisons can be done either in fully parallel 32 comparisons with a longer critical path or it can be done as two independent operations of 16 comparisons each and their results are saved in registers. The final result of best match and length is obtained from column select logic in the next clock cycle introducing a latency of one clock cycle. Alternatively, the same comparisons can be carried out as four independent operations of 8 comparisons each that again introduce latency in the final result. This architecture is well suited for applications where high compression ratios are required as longer history buffer lengths can be accommodated in this architecture at the cost of initial latency. The IP protocol demultiplexer separates different IP data streams and schedules these streams on different layers of the architecture in the device depending on the workload of a particular layer. The architecture shown in Figure 8 is best suited to very high throughput applications. The history buffer length is not very long in this architecture and it caters for the future iterations of the algorithm in the same clock cycle. Therefore, more than one codeword can be produced in the single clock cycle. Different layers of the architecture handle different streams of data and this further helps in enhancing the throughput of the design. Figure 8: High Speed Multiple Stream Unfolded Architecture V. RESULTS AND DISCUSSION The results of our super unfolded and pipelined architectures are compared with the published Titan R optimized architecture in Error! Reference source not found.. The Titan-R is the fastest compressor published so far [19]. For comparison purpose we used the replication factor (RF) of 2 for super unfolding architecture clocked at 100 MHz, providing a throughput of 9.17 Gbps and taking only input Lookup Tables (LUTs). By further increasing the replication factor, higher throughputs can be achieved. The presented pipelined architecture for larger history buffers provides a throughput of 8.7 Gbps at 165 MHz and consumes only LUTs. The pipelined architecture can be synthesized at much higher clock rates reaching up to 500 MHz thus capable of handling 10G+ data rates. Architecture Table 2: Comparison Summary Super Unfolded RF=2 Piped- Lined Titan-R optimized LUTs (6-input) Clock Speed (MHz) Throughput (Gbps) VI. CONCLUSIONS The paper presented different architectures of compression device. The presented architectures are layered based and are fully scalable. Depending on the data rates, multiple layers of

6 1932 IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, August 2010 compression engines can be instantiated in order to meet the required throughput. The device is equipped with multiple interfaces to handle data rates starting from STM1 to 10Gbps. The presented architecture finds applications to compress big pipes of data to conserve the bandwidth. The device can also be utilized in storage area network to compress and decompress the data in real time. The presented architecture can also be employed to implement LZW and its other variants for lossless data compression. The presented device employs data compression architecture based on LZ77 algorithm and yields highest throughputs reported so far. REFERENCES [1] Ioannis Papaefstathiou, Titan II:An IPcomp Processor for 10-Gbps Networks, IEEE Design & Test of Computers, [2] P. G. Howard and J. S. Vitter, Arithmetic coding for data compression, Proc. IEEE, vol. 82, pp , [3] D.Huffman, A method for the construction of minimum redundancy codes, Proc. IRE, 1958, Vol 40,pp , Sep [4] S. Colomb., Run Length Encoding, IEEE Trans. Inform. Theory, Vol. IT-12, pp ,July [5] Dzung Tian Huang, Fast and Efficient Algorithms for Text and Video Compression, A PhD. dissertation, Brown University, Rhode Island, 1997 [6] Rizwana Mehboob, Shoab A. Khan, Zaheer Ahmed, High Speed Lossless Data Compression Architecture, 10 th IEEE Multi-Topic Conference INMIC 2006, Islambad. [7] J. Ziv and A. Lempel, A Universal Algorithm for Sequential Data Compression, IEEE trans. On Information Theory, vol. IT-23 No. 2, May [8] T.Welsh, A Technique for High-Performance Data Compression, IEEE Computers, vol. 17, pp 8-10, [9] S. Jones, 100 Mbit/s Adaptive Data Compressor Design using selectively Shiftable Content addressable Memory in Proc. Pt. G, vol.139, no. 8, August [10] C.Y. Lee and R.Y. Yang, High Throughput Data Compressor Design using Content Addressable Memory, Proc. Pt. G., vol.142, Feb [11] M. E. Gonzalez Smith and J. A. Storer, Parallel Algorithms for Data Compression [12] James A. Storer, John H. Reif A Parallel Architecture for high Speed Data Communications, IEEE 1990 [13] J.Chang,H.J.Jih, & J.W. Liu, A Lossless Data Compression Processor, in Proc 4th VLSI Design/CAD Workshop, NanTou, Aug. 1994, [14] S. Rigler, W.Bishop and A.Kennings, FPGA based Lossless Data Compression using Huffman and LZ77 Algorithms, CCECE [15] Zaheer Ahmed, Habibullah Jamal, Rizwana Mehboob, and Shoab A. Khan, A Navigation Device with MAC Supporting Multiple Physical Networks for Extended Coverage and Operations, IEEE Transactions on Consumer Electronics, Vol. 54, No. 3, August [16] Zaheer Ahmed, Habibullah Jamal, Shoab A. Khan, Rizwana Mehboob and Asrar Ashraf Cognitive Communication Device for Vehicular Networking, IEEE Transactions on Consumer Electronics, Vol. 55, No. 2, May [17] N.Ranganathan and S. Henriques, High Speed VLSI Designs for Lempel- Ziv Based Data Compression, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 40, February [18] Shih-Arn Hwang and Cheng-Wen Wu, Unified VLSI Systolic Array for LZ Data Compression, IEEE Transactions on Very Large Scale Integration, Vol. 9, No. 4, August [19] Konstantinos Papadopoulos and Ioannis Papaefstathiou, Titan-R: A Reconfigurable hardware implementation of a high-speed Compressor, 16th International Symposium on Field-Programmable Custom Computing Machines, BIOGRAPHIES Rizwana Mehboob completed her PhD. from Center for Advanced Research in Engineering (CASE) in 2010 and M.S. in Computer Engineering from National University of Sciences and Technology, Rawalpindi, Pakistan. She completed her B.Sc. in Electrical Engineering from University of Engineering and Technology, Lahore, Pakistan. She has a 16+ years of industrial experience in design/development of complex embedded systems, Hardware & Software Architecture design, Communication, Data Compression & Network protocol design. Dr. S. A. Khan did his PhD in Electrical and Computer Engineering from Georgia Institute of Technology; Atlanta, GA. Dr. Khan s areas of specialization are Digital Signal Processing, Digital Design and Communication System. He has 12+ years industrial experience in companies like Scientific Atlanta, Picture Tel, and Cisco Systems. Mostly he worked on multi-dsp-based systems. As head of R&D group at Communications Enabling Technologies, he headed the team that executed a pioneering work of System on Chip (SoC) design. He is one of the five recipients of National Education Award 2001 in the category of Outstanding Services to Science and Technology Zaheer Ahmed completed his PhD. in Electrical Engineering from University of Engineering and Technology Taxila, Pakistan. He did his M.S. in Computer Engineering from National University of Sciences and Technology, Rawalpindi, Post Graduation in Nuclear Power Plant Technology from KINPOE and B.E. in Electronics Engineering, NED University, Karachi. He has 18+ years of industrial experience in the area of hardware and software design and development. His areas of expertise are embedded systems, industrial control applications, ASIC design, cryptography and software design and development. Professor Habibullah Jamal did his B.Sc. (EE) from University of Engineering and Technology, Lahore, Pakistan in He earned his MSc. and Ph.D degrees both in Elect. Engg. from University of Toronto, Canada, in 1979 and 1982 respectively. Dr Jamal has served academia throughout his professional career. Presently he is Professor, Electrical Engineering Department, University of Engineering and Technology Taxila, Pakistan and also the Vice Chancellor of the university. He is a Fellow/Member of many professional bodies including IEEE. He is recipient of 9th Pakistan Education Forum, National Education Award 2003 and National Book Council of Pakistan Award Muhammad Shahbaz did his B.E. in Computer Engineering from National University of Sciences and Technology (NUST) Pakistan. His areas of expertise are embedded systems, kernel mode applications, FPGA design, software design and development. He has an experience of 2+ years in industry.