Standards for NoC: What can we gain?

Size: px
Start display at page:

Download "Standards for NoC: What can we gain?"

Transcription

1 Standards for NoC: What can we gain? Axel Jantsch Royal Institute of Technology, Stockholm March 2006

2 March 2006 Standards for NoC 1 What Kind of Standards Informal Standards are a set of assumptions shared and agreed upon in a community Industrial standards are set by companies that guess right Formal standards (IEEE, ISO,...) are usually preceded by an informal consensus

3 March 2006 Standards for NoC 2 Standards vs. Creativity

4 March 2006 Standards for NoC 2 Standards vs. Creativity

5 March 2006 Standards for NoC 2 Standards vs. Creativity +

6 March 2006 Standards for NoC 2 Standards vs. Creativity + =

7 March 2006 Standards for NoC 3 Standardizing Interfaces and Protocols Pins Data link Transactions End-to-end communication services Functionality + performance contracts

8 March 2006 Standards for NoC 3 Standardizing Interfaces and Protocols We gain: Pins Data link Transactions End-to-end communication services Functionality + performance contracts Reuse of IPs Reuse or verification Outsourcing and specialization Separation of Physical design issues Communication design Component design Verification System design

9 March 2006 Standards for NoC 4 Standardization of Design Methodologies Reuse of concepts Methodologies Methods Design languages Tools Reuse, separation of concerns and specialization are driving forces

10 March 2006 Standards for NoC 5 We can build on top of standards Assuming we have standard communication services, we build on top of them:

11 March 2006 Standards for NoC 5 We can build on top of standards Assuming we have standard communication services, we build on top of them: Design tools: System performance analysis Formal communication verification Allocation, mapping, and scheduling etc.

12 March 2006 Standards for NoC 5 We can build on top of standards Assuming we have standard communication services, we build on top of them: Design tools: System performance analysis Formal communication verification Allocation, mapping, and scheduling etc. New services: Dynamic resource allocation and management Dynamic power management On-line testing and diagnostics Off-chip communication services etc.

13 March 2006 Standards for NoC 6 Standardization of Performance Metrics

14 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks

15 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks Packet level and Transaction level

16 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks Packet level and Transaction level Unloaded and Loaded case

17 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks Packet level and Transaction level Unloaded and Loaded case Various temporal and Spatial distributions of traffic

18 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks Packet level and Transaction level Unloaded and Loaded case Various temporal and Spatial distributions of traffic Best effort and Guaranty services

19 March 2006 Standards for NoC 6 Standardization of Performance Metrics Benchmark applications and Stochastic micro-benchmarks Packet level and Transaction level Unloaded and Loaded case Various temporal and Spatial distributions of traffic Best effort and Guaranty services Sizes between 16 and 200 nodes

20 March 2006 Standards for NoC 7 Unloaded Case Packet Transaction Read 16/32/64b Write 16/32/64b Open Stream Close Stream Message 1/4/16/32B Delay Bandwidth Energy Area

21 March 2006 Standards for NoC 8 Loaded Case Packet Transaction Read 16/32/64b Write 16/32/64b Open Stream Close Stream Message 1/4/16/32B D 1 D 2 D 3 D n Sustained bandwidth Energy /byte 1 10 i of all packets p: delay(p) mindelay(p) D i D 1 : 90%, D 2 : 99%, D 3 : 99.9%, D n : 100%

22 March 2006 Standards for NoC 9 Temporal Distributions Uniform Bursty traffic according to the B-Model: B 0.2, B 0.3, B traffic Packet number/total packet number cycle cycle

23 March 2006 Standards for NoC 10 Spatial Patterns Uniform Uniform with locality Bit Rotate Bit Complement Hot Spot Fork-Join Pipeline Uniform

24 March 2006 Standards for NoC 11 Spatial Patterns Uniform Uniform with locality Bit Rotate Bit Complement Hot Spot Fork-Join Pipeline Bit Rotate

25 March 2006 Standards for NoC 12 Spatial Patterns Uniform Uniform with locality Bit Rotate Bit Complement Hot Spot Fork-Join Pipeline Bit Complement

26 March 2006 Standards for NoC 13 Spatial Patterns Uniform Uniform with locality Bit Rotate Bit Complement Hot Spot Fork-Join Pipeline Hot Spot

27 March 2006 Standards for NoC 14 Spatial Patterns Uniform Uniform with locality Bit Rotate Bit Complement Hot Spot Fork-Join Pipeline Fork Join Pipeline

28 March 2006 Standards for NoC 15 Size Number of nodes: 8, 16, 25, 40, 60, 80, 100, 150, 200

29 March 2006 Standards for NoC 16 Data Points for Stochastic Micro Benchmarks Temporal distribution: 4 Spatial patterns: 12 Unloaded case: ((14 4)+ Loaded case: ((14 6)) Size: 9 = 60480

30 March 2006 Standards for NoC 17 D 1 versus network size in Nostrum D1,uniform 5% D1,uniform 10% D1,uniform 15% D1,uniform 20% normalized delay number of nodes

31 March 2006 Standards for NoC 18 D 2 versus network size in Nostrum D2,uniform 5% D2,uniform 10% D2,uniform 15% D2,uniform 20% 2.1 normalized delay number of nodes

32 March 2006 Standards for NoC 19 D 3 versus network size in Nostrum D3,uniform 5% D3,uniform 10% D3,uniform 15% D3,uniform 20% 2.8 normalized delay number of nodes

33 March 2006 Standards for NoC 20 D n versus network size in Nostrum Dn,uniform 5% Dn,uniform 10% Dn,uniform 15% Dn,uniform 20% 4 normalized delay number of nodes

34 March 2006 Standards for NoC 21 Summary Standards are crucial and complementary to innovative research Let s standardize performance metrics

Network-on-Chip Micro-Benchmarks

Network-on-Chip Micro-Benchmarks Network-on-Chip Micro-Benchmarks Zhonghai Lu *, Axel Jantsch *, Erno Salminen and Cristian Grecu * Royal Institute of Technology, Sweden Tampere University of Technology, Finland Abstract University of

More information

The Nostrum Network on Chip

The Nostrum Network on Chip The Nostrum Network on Chip 10 processors 10 processors Mikael Millberg, Erland Nilsson, Richard Thid, Johnny Öberg, Zhonghai Lu, Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004

More information

Networks on Chip. Axel Jantsch. November 24, Royal Institute of Technology, Stockholm

Networks on Chip. Axel Jantsch. November 24, Royal Institute of Technology, Stockholm Networks on Chip Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004 Network on Chip Seminar, Linköping, November 25, 2004 Networks on Chip 1 Overview NoC as Future SoC Platforms What

More information

Communication Performance in Network-on-Chips

Communication Performance in Network-on-Chips Communication Performance in Network-on-Chips Axel Jantsch Royal Institute of Technology, Stockholm November 24, 2004 Network on Chip Seminar, Linköping, November 25, 2004 Communication Performance In

More information

Cross Clock-Domain TDM Virtual Circuits for Networks on Chips

Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Cross Clock-Domain TDM Virtual Circuits for Networks on Chips Zhonghai Lu Dept. of Electronic Systems School for Information and Communication Technology KTH - Royal Institute of Technology, Stockholm

More information

Ultra-Fast NoC Emulation on a Single FPGA

Ultra-Fast NoC Emulation on a Single FPGA The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo

More information

Do we need a crystal ball for task migration?

Do we need a crystal ball for task migration? Do we need a crystal ball for task migration? Brandon {Myers,Holt} University of Washington bdmyers@cs.washington.edu 1 Large data sets Data 2 Spread data Data.1 Data.2 Data.3 Data.4 Data.0 Data.1 Data.2

More information

Interconnection Networks: Topology. Prof. Natalie Enright Jerger

Interconnection Networks: Topology. Prof. Natalie Enright Jerger Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design

More information

Dynamic Flow Regulation for IP Integration on Network-on-Chip

Dynamic Flow Regulation for IP Integration on Network-on-Chip Dynamic Flow Regulation for IP Integration on Network-on-Chip Zhonghai Lu and Yi Wang Dept. of Electronic Systems KTH Royal Institute of Technology Stockholm, Sweden Agenda The IP integration problem Why

More information

Supporting Distributed Shared Memory. Axel Jantsch Xiaowen Chen, Zhonghai Lu Royal Institute of Technology, Sweden September 16, 2009

Supporting Distributed Shared Memory. Axel Jantsch Xiaowen Chen, Zhonghai Lu Royal Institute of Technology, Sweden September 16, 2009 Supporting Distributed Shared Memory Axel Jantsch Xiaowen Chen, Zhonghai Lu Royal Institute of Technology, Sweden September 16, 2009 Memory content in today s SoCs 3 Elements in SoC Processing: Well understood;

More information

The Google File System

The Google File System The Google File System Sanjay Ghemawat, Howard Gobioff, and Shun-Tak Leung Google* 정학수, 최주영 1 Outline Introduction Design Overview System Interactions Master Operation Fault Tolerance and Diagnosis Conclusions

More information

High-Level Simulations of On-Chip Networks

High-Level Simulations of On-Chip Networks High-Level Simulations of On-Chip Networks Claas Cornelius, Frank Sill, Dirk Timmermann 9th EUROMICRO Conference on Digital System Design (DSD) - Architectures, Methods and Tools - University of Rostock

More information

Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema

Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema Real Time NoC Based Pipelined Architectonics With Efficient TDM Schema [1] Laila A, [2] Ajeesh R V [1] PG Student [VLSI & ES] [2] Assistant professor, Department of ECE, TKM Institute of Technology, Kollam

More information

Write only as much as necessary. Be brief!

Write only as much as necessary. Be brief! 1 CIS371 Computer Organization and Design Midterm Exam Prof. Martin Thursday, March 15th, 2012 This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached

More information

EE/CSCI 451: Parallel and Distributed Computation

EE/CSCI 451: Parallel and Distributed Computation EE/CSCI 451: Parallel and Distributed Computation Lecture #11 2/21/2017 Xuehai Qian Xuehai.qian@usc.edu http://alchem.usc.edu/portal/xuehaiq.html University of Southern California 1 Outline Midterm 1:

More information

Network on Chip. December Royal Institute of Technology, Stockholm S NI

Network on Chip. December Royal Institute of Technology, Stockholm S NI Network on Chip NI NI NI S S S NI NI NI S S S NI NI NI S S S NI NI NI S S S NI NI NI S S S Axel Jantsch, Zhonghai Lu, Shashi Kumar, Ahmed Hemani, Mikael Millberg, Rikard Thid, Johnny Öberg, Erland Nilsson,

More information

Processors. Young W. Lim. May 12, 2016

Processors. Young W. Lim. May 12, 2016 Processors Young W. Lim May 12, 2016 Copyright (c) 2016 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version

More information

Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees

Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees Srinivasan Murali 1, Prof. Luca Benini 2, Prof. Giovanni De Micheli 1 1 Computer Systems Lab, Stanford

More information

Chapter 2. Parallel Hardware and Parallel Software. An Introduction to Parallel Programming. The Von Neuman Architecture

Chapter 2. Parallel Hardware and Parallel Software. An Introduction to Parallel Programming. The Von Neuman Architecture An Introduction to Parallel Programming Peter Pacheco Chapter 2 Parallel Hardware and Parallel Software 1 The Von Neuman Architecture Control unit: responsible for deciding which instruction in a program

More information

STLAC: A Spatial and Temporal Locality-Aware Cache and Networkon-Chip

STLAC: A Spatial and Temporal Locality-Aware Cache and Networkon-Chip STLAC: A Spatial and Temporal Locality-Aware Cache and Networkon-Chip Codesign for Tiled Manycore Systems Mingyu Wang and Zhaolin Li Institute of Microelectronics, Tsinghua University, Beijing 100084,

More information

A Worst Case Performance Model for TDM Virtual Circuit in NoCs

A Worst Case Performance Model for TDM Virtual Circuit in NoCs A Worst Case Performance Model for TDM Virtual Circuit in NoCs Zhipeng Chen and Axel Jantsch Royal Institute of Technology(KTH), Sweden {zhipeng,axel}@kth.se Abstract. In Network-on-Chip (NoC), Time-Division-Mutiplexing

More information

BeiHang Short Course, Part 5: Pandora Smart IP Generators

BeiHang Short Course, Part 5: Pandora Smart IP Generators BeiHang Short Course, Part 5: Pandora Smart IP Generators James C. Hoe Department of ECE Carnegie Mellon University Collaborator: Michael Papamichael J. C. Hoe, CMU/ECE/CALCM, 0, BHSC L5 s CONNECT NoC

More information

Layer 3: Network Layer. 9. Mar INF-3190: Switching and Routing

Layer 3: Network Layer. 9. Mar INF-3190: Switching and Routing Layer 3: Network Layer 9. Mar. 2005 1 INF-3190: Switching and Routing Network Layer Goal Enable data transfer from end system to end system End systems Several hops, (heterogeneous) subnetworks Compensate

More information

Towards Open Network-on-Chip Benchmarks

Towards Open Network-on-Chip Benchmarks Towards Open Network-on-Chip Benchmarks Cristian Grecu 1, Andrè Ivanov 1, Partha Pande 2, Axel Jantsch 3, Erno Salminen 4, Umit Ogras 5, Radu Marculescu 5 1 University of British Columbia, 2 Washington

More information

HIRP OPEN 2018 Compiler & Programming Language. An Efficient Framework for Optimizing Tensors

HIRP OPEN 2018 Compiler & Programming Language. An Efficient Framework for Optimizing Tensors An Efficient Framework for Optimizing Tensors 1 Theme: 2 Subject: Compiler Technology List of Abbreviations NA 3 Background Tensor computation arises frequently in machine learning, graph analytics and

More information

A Scalable Content- Addressable Network

A Scalable Content- Addressable Network A Scalable Content- Addressable Network In Proceedings of ACM SIGCOMM 2001 S. Ratnasamy, P. Francis, M. Handley, R. Karp, S. Shenker Presented by L.G. Alex Sung 9th March 2005 for CS856 1 Outline CAN basics

More information

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design

A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design A Thermal-aware Application specific Routing Algorithm for Network-on-chip Design Zhi-Liang Qian and Chi-Ying Tsui VLSI Research Laboratory Department of Electronic and Computer Engineering The Hong Kong

More information

Replicate It! Scalable Content Delivery: Why? Scalable Content Delivery: How? Scalable Content Delivery: How? Scalable Content Delivery: What?

Replicate It! Scalable Content Delivery: Why? Scalable Content Delivery: How? Scalable Content Delivery: How? Scalable Content Delivery: What? Accelerating Internet Streaming Media Delivery using Azer Bestavros and Shudong Jin Boston University http://www.cs.bu.edu/groups/wing Scalable Content Delivery: Why? Need to manage resource usage as demand

More information

Selective Fill Data Cache

Selective Fill Data Cache Selective Fill Data Cache Rice University ELEC525 Final Report Anuj Dharia, Paul Rodriguez, Ryan Verret Abstract Here we present an architecture for improving data cache miss rate. Our enhancement seeks

More information

Comparison of Shaping and Buffering for Video Transmission

Comparison of Shaping and Buffering for Video Transmission Comparison of Shaping and Buffering for Video Transmission György Dán and Viktória Fodor Royal Institute of Technology, Department of Microelectronics and Information Technology P.O.Box Electrum 229, SE-16440

More information

Introduction to the Qsys System Integration Tool

Introduction to the Qsys System Integration Tool Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will

More information

Efficient Latency Guarantees for Mixed-criticality Networks-on-Chip

Efficient Latency Guarantees for Mixed-criticality Networks-on-Chip Platzhalter für Bild, Bild auf Titelfolie hinter das Logo einsetzen Efficient Latency Guarantees for Mixed-criticality Networks-on-Chip Sebastian Tobuschat, Rolf Ernst IDA, TU Braunschweig, Germany 18.

More information

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip

Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip ASP-DAC 2010 20 Jan 2010 Session 6C Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip Jonas Diemer, Rolf Ernst TU Braunschweig, Germany diemer@ida.ing.tu-bs.de Michael Kauschke Intel,

More information

Module 5: Performance Issues in Shared Memory and Introduction to Coherence Lecture 9: Performance Issues in Shared Memory. The Lecture Contains:

Module 5: Performance Issues in Shared Memory and Introduction to Coherence Lecture 9: Performance Issues in Shared Memory. The Lecture Contains: The Lecture Contains: Data Access and Communication Data Access Artifactual Comm. Capacity Problem Temporal Locality Spatial Locality 2D to 4D Conversion Transfer Granularity Worse: False Sharing Contention

More information

Table of Contents 1 Introduction A Declarative Approach to Entity Resolution... 17

Table of Contents 1 Introduction A Declarative Approach to Entity Resolution... 17 Table of Contents 1 Introduction...1 1.1 Common Problem...1 1.2 Data Integration and Data Management...3 1.2.1 Information Quality Overview...3 1.2.2 Customer Data Integration...4 1.2.3 Data Management...8

More information

TDM Virtual-Circuit Configuration for Network-on-Chip Zhonghai Lu, Member, IEEE, and Axel Jantsch, Member, IEEE

TDM Virtual-Circuit Configuration for Network-on-Chip Zhonghai Lu, Member, IEEE, and Axel Jantsch, Member, IEEE IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 8, AUGUST 2008 1021 TDM Virtual-Circuit Configuration for Network-on-Chip Zhonghai Lu, Member, IEEE, and Axel Jantsch, Member,

More information

Class A Bridge Latency Calculations

Class A Bridge Latency Calculations Class A Bridge Latency Calculations Christian Boiger IEEE 802 Plenary Meeting November 2010 Dallas, TX 1 Example - 15 port FE Bridge - 13 FE talkers, each is sending one stream - 1 FE listener L, is receiving

More information

Lab Test Report DR100401D. Cisco Nexus 5010 and Arista 7124S

Lab Test Report DR100401D. Cisco Nexus 5010 and Arista 7124S Lab Test Report DR100401D Cisco Nexus 5010 and Arista 7124S 1 April 2010 Miercom www.miercom.com Contents Executive Summary... 3 Overview...4 Key Findings... 5 How We Did It... 7 Figure 1: Traffic Generator...

More information

Deterministic Ethernet & Unified Networking

Deterministic Ethernet & Unified Networking Deterministic Ethernet & Unified Networking Never bet against Ethernet Mirko Jakovljevic mirko.jakovljevic@tttech.com www.tttech.com Copyright TTTech Computertechnik AG. All rights reserved. About TTTech

More information

Data Parallel Architectures

Data Parallel Architectures EE392C: Advanced Topics in Computer Architecture Lecture #2 Chip Multiprocessors and Polymorphic Processors Thursday, April 3 rd, 2003 Data Parallel Architectures Lecture #2: Thursday, April 3 rd, 2003

More information

I/O Handling. ECE 650 Systems Programming & Engineering Duke University, Spring Based on Operating Systems Concepts, Silberschatz Chapter 13

I/O Handling. ECE 650 Systems Programming & Engineering Duke University, Spring Based on Operating Systems Concepts, Silberschatz Chapter 13 I/O Handling ECE 650 Systems Programming & Engineering Duke University, Spring 2018 Based on Operating Systems Concepts, Silberschatz Chapter 13 Input/Output (I/O) Typical application flow consists of

More information

Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni

Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Department of Computer Science Columbia University in the City of New York NSF Workshop on Emerging Technologies

More information

Design and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University

Design and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University Design and Test Solutions for Networks-on-Chip Jin-Ho Ahn Hoseo University Topics Introduction NoC Basics NoC-elated esearch Topics NoC Design Procedure Case Studies of eal Applications NoC-Based SoC Testing

More information

Connection-oriented Multicasting in Wormhole-switched Networks on Chip

Connection-oriented Multicasting in Wormhole-switched Networks on Chip Connection-oriented Multicasting in Wormhole-switched Networks on Chip Zhonghai Lu, Bei Yin and Axel Jantsch Laboratory of Electronics and Computer Systems Royal Institute of Technology, Sweden fzhonghai,axelg@imit.kth.se,

More information

Constructing Virtual Architectures on Tiled Processors. David Wentzlaff Anant Agarwal MIT

Constructing Virtual Architectures on Tiled Processors. David Wentzlaff Anant Agarwal MIT Constructing Virtual Architectures on Tiled Processors David Wentzlaff Anant Agarwal MIT 1 Emulators and JITs for Multi-Core David Wentzlaff Anant Agarwal MIT 2 Why Multi-Core? 3 Why Multi-Core? Future

More information

Bandwidth Aware Routing Algorithms for Networks-on-Chip

Bandwidth Aware Routing Algorithms for Networks-on-Chip 1 Bandwidth Aware Routing Algorithms for Networks-on-Chip G. Longo a, S. Signorino a, M. Palesi a,, R. Holsmark b, S. Kumar b, and V. Catania a a Department of Computer Science and Telecommunications Engineering

More information

QoS and System Capacity Optimization in WiMAX Multi-hop Relay Using Flexible Tiered Control Technique

QoS and System Capacity Optimization in WiMAX Multi-hop Relay Using Flexible Tiered Control Technique 2009 International Conference on Computer Engineering and Applications IPCSIT vol.2 (2011) (2011) IACSIT Press, Singapore QoS and System Capacity Optimization in WiMAX Multi-hop Relay Using Flexible Tiered

More information

Basics (cont.) Characteristics of data communication technologies OSI-Model

Basics (cont.) Characteristics of data communication technologies OSI-Model 48 Basics (cont.) Characteristics of data communication technologies OSI-Model Topologies Packet switching / Circuit switching Medium Access Control (MAC) mechanisms Coding Quality of Service (QoS) 49

More information

OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel

OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab (http://synergy.ece.gatech.edu) hyoukjun@gatech.edu April

More information

Multimedia Networking. Network Support for Multimedia Applications

Multimedia Networking. Network Support for Multimedia Applications Multimedia Networking Network Support for Multimedia Applications Protocols for Real Time Interactive Applications Differentiated Services (DiffServ) Per Connection Quality of Services Guarantees (IntServ)

More information

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013 NetSpeed ORION: A New Approach to Design On-chip Interconnects August 26 th, 2013 INTERCONNECTS BECOMING INCREASINGLY IMPORTANT Growing number of IP cores Average SoCs today have 100+ IPs Mixing and matching

More information

CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE VERIFICATION PANKAJ SINGH, MALATHI CHIKKANNA

CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE VERIFICATION PANKAJ SINGH, MALATHI CHIKKANNA CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE VERIFICATION PANKAJ SINGH, MALATHI CHIKKANNA INTRODUCTION Rapid progress in Semiconductor Technology Numerous circuits soldered ona printed circuit board

More information

Dual Cell-high Speed Downlink Packet Access System Benefits and User Experience Gains

Dual Cell-high Speed Downlink Packet Access System Benefits and User Experience Gains International Journal of Information and Computation Technology. ISSN 0974-2239 Volume 3, Number 4 (2013), pp. 279-292 International Research Publications House http://www. irphouse.com /ijict.htm Dual

More information

VLIW DSP Processor Design for Mobile Communication Applications. Contents crafted by Dr. Christian Panis Catena Radio Design

VLIW DSP Processor Design for Mobile Communication Applications. Contents crafted by Dr. Christian Panis Catena Radio Design VLIW DSP Processor Design for Mobile Communication Applications Contents crafted by Dr. Christian Panis Catena Radio Design Agenda Trends in mobile communication Architectural core features with significant

More information

NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures

NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, and Yiannakis Sazeides University of Cyprus

More information

Negotiating the Maze Getting the most out of memory systems today and tomorrow. Robert Kaye

Negotiating the Maze Getting the most out of memory systems today and tomorrow. Robert Kaye Negotiating the Maze Getting the most out of memory systems today and tomorrow Robert Kaye 1 System on Chip Memory Systems Systems use external memory Large address space Low cost-per-bit Large interface

More information

The Google File System

The Google File System The Google File System Sanjay Ghemawat, Howard Gobioff, and Shun-Tak Leung December 2003 ACM symposium on Operating systems principles Publisher: ACM Nov. 26, 2008 OUTLINE INTRODUCTION DESIGN OVERVIEW

More information

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik

SoC Design. Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik SoC Design Prof. Dr. Christophe Bobda Institut für Informatik Lehrstuhl für Technische Informatik Chapter 5 On-Chip Communication Outline 1. Introduction 2. Shared media 3. Switched media 4. Network on

More information

TCP Spatial-Temporal Measurement and Analysis

TCP Spatial-Temporal Measurement and Analysis TCP Spatial-Temporal Measurement and Analysis Infocom 05 E. Brosh Distributed Network Analysis (DNA) Group Columbia University G. Lubetzky-Sharon, Y. Shavitt Tel-Aviv University 1 Overview Inferring network

More information

Model-based Measurements Of Network Loss

Model-based Measurements Of Network Loss Model-based Measurements Of Network Loss June 28, 2013 Mirja Kühlewind mirja.kuehlewind@ikr.uni-stuttgart.de Universität Stuttgart Institute of Communication Networks and Computer Engineering (IKR) Prof.

More information

Network Management & Monitoring Network Delay

Network Management & Monitoring Network Delay Network Management & Monitoring Network Delay These materials are licensed under the Creative Commons Attribution-Noncommercial 3.0 Unported license (http://creativecommons.org/licenses/by-nc/3.0/) End-to-end

More information

CS Computer Architecture

CS Computer Architecture CS 35101 Computer Architecture Section 600 Dr. Angela Guercio Fall 2010 An Example Implementation In principle, we could describe the control store in binary, 36 bits per word. We will use a simple symbolic

More information

Re-configurable VLIW processor for streaming data

Re-configurable VLIW processor for streaming data International Workshop NGNT 97 Re-configurable VLIW processor for streaming data V. Iossifov Studiengang Technische Informatik, FB Ingenieurwissenschaften 1, FHTW Berlin. G. Megson School of Computer Science,

More information

Chapter 2: Memory Hierarchy Design Part 2

Chapter 2: Memory Hierarchy Design Part 2 Chapter 2: Memory Hierarchy Design Part 2 Introduction (Section 2.1, Appendix B) Caches Review of basics (Section 2.1, Appendix B) Advanced methods (Section 2.3) Main Memory Virtual Memory Fundamental

More information

Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency

Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency Profiling-Based L1 Data Cache Bypassing to Improve GPU Performance and Energy Efficiency Yijie Huangfu and Wei Zhang Department of Electrical and Computer Engineering Virginia Commonwealth University {huangfuy2,wzhang4}@vcu.edu

More information

I/O CHARACTERIZATION AND ATTRIBUTE CACHE DATA FOR ELEVEN MEASURED WORKLOADS

I/O CHARACTERIZATION AND ATTRIBUTE CACHE DATA FOR ELEVEN MEASURED WORKLOADS I/O CHARACTERIZATION AND ATTRIBUTE CACHE DATA FOR ELEVEN MEASURED WORKLOADS Kathy J. Richardson Technical Report No. CSL-TR-94-66 Dec 1994 Supported by NASA under NAG2-248 and Digital Western Research

More information

Routing of guaranteed throughput traffic in a network-on-chip

Routing of guaranteed throughput traffic in a network-on-chip Routing of guaranteed throughput traffic in a network-on-chip Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen Department of EEMCS, University of Twente, the Netherlands {n.k.kavaldjiev,

More information

CS7810 Prefetching. Seth Pugsley

CS7810 Prefetching. Seth Pugsley CS7810 Prefetching Seth Pugsley Predicting the Future Where have we seen prediction before? Does it always work? Prefetching is prediction Predict which cache line will be used next, and place it in the

More information

MIT Kerberos for Mobile Devices

MIT Kerberos for Mobile Devices MIT Kerberos for Mobile Devices Zhanna Tsitkova MIT Kerberos Consortium March 30, 2009 Mobile Technology Concerns Battery Limited CPU Caching to reduce DNS traffic Limited Memory Lite Client on Mac OS

More information

An overview on Internet Measurement Methodologies, Techniques and Tools

An overview on Internet Measurement Methodologies, Techniques and Tools An overview on Internet Measurement Methodologies, Techniques and Tools AA 2011/2012 emiliano.casalicchio@uniroma2.it (Agenda) Lezione 2/05/2012 Part 1 Intro basic concepts ISP Traffic exchange (peering)

More information

Network Service Assurance

Network Service Assurance Service Assurance Embedded 'Always-On' Ethernet Devices for Circuit 'Turn-Up' Testing & In-Service Assurance for Layer- 2 and Layer-3 infrastructures Ethernet (L-2) - Typical Scenario HQ & Operations Centre

More information

Methodology of Searching for All Shortest Routes in NoC

Methodology of Searching for All Shortest Routes in NoC PROCEEDING OF THE TH CONFERENCE OF FRUCT ASSOCIATION Methodology of Searching for All Shortest Routes in NoC Nadezhda Matveeva, Elena Suvorova Saint-Petersburg State University of Aerospace Instrumentation

More information

Master Informatics Eng.

Master Informatics Eng. Advanced Architectures Master Informatics Eng. 207/8 A.J.Proença The Roofline Performance Model (most slides are borrowed) AJProença, Advanced Architectures, MiEI, UMinho, 207/8 AJProença, Advanced Architectures,

More information

Lecture notes for CS Chapter 2, part 1 10/23/18

Lecture notes for CS Chapter 2, part 1 10/23/18 Chapter 2: Memory Hierarchy Design Part 2 Introduction (Section 2.1, Appendix B) Caches Review of basics (Section 2.1, Appendix B) Advanced methods (Section 2.3) Main Memory Virtual Memory Fundamental

More information

Getting it Right: Testing Storage Arrays The Way They ll be Used

Getting it Right: Testing Storage Arrays The Way They ll be Used Getting it Right: Testing Storage Arrays The Way They ll be Used Peter Murray Virtual Instruments Flash Memory Summit 2017 Santa Clara, CA 1 The Journey: How Did we Get Here? Storage testing was black

More information

Lecture 3: Topology - II

Lecture 3: Topology - II ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 3: Topology - II Tushar Krishna Assistant Professor School of Electrical and

More information

Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, and Alberto Leon-Garcia

Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, and Alberto Leon-Garcia Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, and Alberto Leon-Garcia The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto, ON, Canada Motivation: IoT

More information

Query Processing: A Systems View. Announcements (March 1) Physical (execution) plan. CPS 216 Advanced Database Systems

Query Processing: A Systems View. Announcements (March 1) Physical (execution) plan. CPS 216 Advanced Database Systems Query Processing: A Systems View CPS 216 Advanced Database Systems Announcements (March 1) 2 Reading assignment due Wednesday Buffer management Homework #2 due this Thursday Course project proposal due

More information

COSC 6385 Computer Architecture - Memory Hierarchy Design (III)

COSC 6385 Computer Architecture - Memory Hierarchy Design (III) COSC 6385 Computer Architecture - Memory Hierarchy Design (III) Fall 2006 Reducing cache miss penalty Five techniques Multilevel caches Critical word first and early restart Giving priority to read misses

More information

TSHOOT: Troubleshooting and Maintaining Cisco IP Networks

TSHOOT: Troubleshooting and Maintaining Cisco IP Networks 642-832 TSHOOT: Troubleshooting and Maintaining Cisco IP Networks Course Number: 642-832 Length: 5 Days Course Overview Troubleshooting and Maintaining Cisco IP Switched Networks (TSHOOT 642-832) is a

More information

Fast-Response Multipath Routing Policy for High-Speed Interconnection Networks

Fast-Response Multipath Routing Policy for High-Speed Interconnection Networks HPI-DC 09 Fast-Response Multipath Routing Policy for High-Speed Interconnection Networks Diego Lugones, Daniel Franco, and Emilio Luque Leonardo Fialho Cluster 09 August 31 New Orleans, USA Outline Scope

More information

Overview of the Simulation Process. CS1538: Introduction to Simulations

Overview of the Simulation Process. CS1538: Introduction to Simulations Overview of the Simulation Process CS1538: Introduction to Simulations Simulation Fundamentals A computer simulation is a computer program that models the behavior of a physical system over time. Program

More information

2 Improved Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers [1]

2 Improved Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers [1] EE482: Advanced Computer Organization Lecture #7 Processor Architecture Stanford University Tuesday, June 6, 2000 Memory Systems and Memory Latency Lecture #7: Wednesday, April 19, 2000 Lecturer: Brian

More information

Akash Raut* et al ISSN: [IJESAT] [International Journal of Engineering Science & Advanced Technology] Volume-6, Issue-3,

Akash Raut* et al ISSN: [IJESAT] [International Journal of Engineering Science & Advanced Technology] Volume-6, Issue-3, A Transparent Approach on 2D Mesh Topology using Routing Algorithms for NoC Architecture --------------- Dept Electronics & Communication MAHARASHTRA, India --------------------- Prof. and Head, Dept.Mr.NIlesh

More information

A Comparison of Capacity Management Schemes for Shared CMP Caches

A Comparison of Capacity Management Schemes for Shared CMP Caches A Comparison of Capacity Management Schemes for Shared CMP Caches Carole-Jean Wu and Margaret Martonosi Princeton University 7 th Annual WDDD 6/22/28 Motivation P P1 P1 Pn L1 L1 L1 L1 Last Level On-Chip

More information

Donn Morrison Department of Computer Science. TDT4255 Memory hierarchies

Donn Morrison Department of Computer Science. TDT4255 Memory hierarchies TDT4255 Lecture 10: Memory hierarchies Donn Morrison Department of Computer Science 2 Outline Chapter 5 - Memory hierarchies (5.1-5.5) Temporal and spacial locality Hits and misses Direct-mapped, set associative,

More information

Design and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation. Jiayi Zhang September 2009

Design and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation. Jiayi Zhang September 2009 TRITA-ICT-EX-29:157 Master Thesis in Electronic System Design Design and Implementation of AXI-based Network-on-Chip Systems for Flow Regulation Jiayi Zhang September 29 Supervisor: Examiner: Dr. Zhonghai

More information

MHL What is it? Quantum Data Inc Big Timber Road Elgin, IL USA Phone: (847)

MHL What is it? Quantum Data Inc Big Timber Road Elgin, IL USA Phone: (847) MHL What is it? Mobile High-Definition Link (MHL) is a video interface derived from HDMI but targeted to provide an interface from mobile devices like smart phones to TVs or other displays. The MHL standard

More information

Abstract. Paper organization

Abstract. Paper organization Allocation Approaches for Virtual Channel Flow Control Neeraj Parik, Ozen Deniz, Paul Kim, Zheng Li Department of Electrical Engineering Stanford University, CA Abstract s are one of the major resources

More information

Adaptive Video Multicasting

Adaptive Video Multicasting Adaptive Video Multicasting Presenters: Roman Glistvain, Bahman Eksiri, and Lan Nguyen 1 Outline Approaches to Adaptive Video Multicasting Single rate multicast Simulcast Active Agents Layered multicasting

More information

MTAT : Software Testing

MTAT : Software Testing MTAT.03.159: Software Testing Lecture 04: Static Testing (Inspection) and Defect Estimation (Textbook Ch. 10 & 12) Spring 2013 Dietmar Pfahl email: dietmar.pfahl@ut.ee Lecture Reading Chapter 10: Reviews

More information

Announcements (March 1) Query Processing: A Systems View. Physical (execution) plan. Announcements (March 3) Physical plan execution

Announcements (March 1) Query Processing: A Systems View. Physical (execution) plan. Announcements (March 3) Physical plan execution Announcements (March 1) 2 Query Processing: A Systems View CPS 216 Advanced Database Systems Reading assignment due Wednesday Buffer management Homework #2 due this Thursday Course project proposal due

More information

Fast Flexible FPGA-Tuned Networks-on-Chip

Fast Flexible FPGA-Tuned Networks-on-Chip This work was funded by NSF. We thank Xilinx for their FPGA and tool donations. We thank Bluespec for their tool donations. Fast Flexible FPGA-Tuned Networks-on-Chip Michael K. Papamichael, James C. Hoe

More information

Memory Subsystem Profiling with the Sun Studio Performance Analyzer

Memory Subsystem Profiling with the Sun Studio Performance Analyzer Memory Subsystem Profiling with the Sun Studio Performance Analyzer CScADS, July 20, 2009 Marty Itzkowitz, Analyzer Project Lead Sun Microsystems Inc. marty.itzkowitz@sun.com Outline Memory performance

More information

Scalability of Network-on-Chip Communication Architecture for 3-D Meshes

Scalability of Network-on-Chip Communication Architecture for 3-D Meshes Scalability of Network-on-Chip Communication Architecture for -D Meshes Awet Yemane Weldezion, Matt Grange +, Dinesh Pamunuwa +, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera +, and Hannu Tenhunen School

More information

This chapter contains these sections:

This chapter contains these sections: This chapter contains these sections: ControlNet media-access control-hardware (ASICs) are interface chips that allow a product to access a ControlNet network. The ControlNet ASIC is called CNA10. The

More information

Page 1. Multilevel Memories (Improving performance using a little cash )

Page 1. Multilevel Memories (Improving performance using a little cash ) Page 1 Multilevel Memories (Improving performance using a little cash ) 1 Page 2 CPU-Memory Bottleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency Latency

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: August 26, 2014 at 08:54 CS429 Slideset 20: 1 Cache

More information

AMD: WebBench Virtualization Performance Study

AMD: WebBench Virtualization Performance Study March 2005 www.veritest.com info@veritest.com AMD: WebBench Virtualization Performance Study Test report prepared under contract from Advanced Micro Devices, Inc. Executive summary Advanced Micro Devices,

More information

Computer Architecture. Memory Hierarchy. Lynn Choi Korea University

Computer Architecture. Memory Hierarchy. Lynn Choi Korea University Computer Architecture Memory Hierarchy Lynn Choi Korea University Memory Hierarchy Motivated by Principles of Locality Speed vs. Size vs. Cost tradeoff Locality principle Temporal Locality: reference to

More information