OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel
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1 OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel Hyoukjun Kwon and Tushar Krishna Georgia Institute of Technology Synergy Lab ( April 25, 2017
2 Hardware Development Cost Low cost challenge source: Todd Austin, Micro-49 keynote 2
3 Many-IP Heterogeneous System CPU1 Wireless CPU2 GPU Network Sensor Sensor2 Memory Accelerator Network-on-Chip (NoC) Scalability challenge Flexibility challenge 3
4 Diverse System Requirements Throughput Critical Latency Critical source: MNIST, Engadget, TheStack 4
5 Challenges for NoCs Low-cost - Low design/verification costs of custom/generic NoCs - Design Automation of high-performance, low-energy NoCs Scalability - Many-IP heterogeneous system support - Low latency - Low energy - Low area Flexibility - Diverse connectivity - Diverse latency/throughput requirements 5
6 OpenSMART Low Cost Flexibility Scalability User-configurable Automatic NoC Generation High-level HW Lanugage SMART NoC Krishna et al, HPCA 2013 Chen et al, DATE 2013 Krishna et al, IEEE Micro Top Picks 2014 Verified on FPGA Arbitrary Topology Support Area/power-efficient RTL Building Blocks OpenSMART 6
7 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 7
8 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 8
9 SMART NoC Single-cycle Multi-hop Asynchronous Repeated Traversal SSR (SMART Setup Request) SSR (SMART Setup Request)SSR (SMART Setup Request) S SMART: HPCmax achieve the performance Krishna et al, HPCA of dedicated 2013 Chen al, DATE 2013 connections over a network Krishna al, of IEEE shared Micro links Top Picks 2014, D 1-cycle (no other traffic) 9
10 Is 1-cycle Network Possible? Is wire fast enough to support 1-cycle network? Yes ~20mm ~20mm Wire traversal length within 1ns (1Ghz): 10-16mm Wire delay over technology: constant Chip dimension: remain similar (~20mm) On-chip are fastremain enough similar to transmit across the chip Clockwires frequency: (1~3GHz) within 1-2 cyclesdecrease at 1GHz even if technology scales Tile dimension: over technology ~20mm ~20mm 10
11 Features of SMART Low latency network - Dynamic bypass of intermediate routers between any two routers - Limit: HPCmax (hops per cycle max), maximum number of hops that the underlying wire allows the flit to traverse within a clock cycle Separate control path - HPCmax bits from every router along each direction - Arbitration of multiple bypass requests on the same link - No ACK required 11
12 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 12
13 OpenSMART Design Flow Topology - Bandwidth - VC - Routing Configuration User Specification OpenSMART Front-end Input Unit SMART Unit Output Unit Building Block Library (RTL) HPCmax Analyzer Switch Unit OpenSMART BSV/Chisel Compiler ASIC/FPGA Synthesis Tool External Tool Chains Verilog Files 13
14 OpenSMART NoC NoC generated by OpenSMART NIC NIC NIC NIC Router Router Router Router Router Router Router Router NIC NIC NIC NIC Interface AMBA Wishbone Custom 14
15 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 15
16 OpenSMART Building Blocks Buffer Arbiter Input Unit VC Selector Arbiter Output Unit input Buffer + input VC arbitration output VC selection + output port arbitration + credit management >> switching (via crossbar) + routing calculation Crossbar Switch Unit Routing Calculator SSR SSR Controller SSR communication & arbitration + bypass flag Bypass Flag SMART Unit 16
17 OpenSMART Router Incoming Flits Input Unit Arbiter OpenSMART Router Arbiter (Baseline) Outgoing Flits Flit Input Units Flit Header Flit Size Flit Data Output Units Input Buffers Number of VCs/VC Depth >> Flit Header Switch Unit Flit Data 17
18 OpenSMART Router Incoming Flits Output Port Request Output Unit Arbiter OpenSMART Router (Baseline) Outgoing Flits Output Port Grant Input Units Output Arbiter Units VC Selector >> nextvc Switch Unit VC nextvc VC queue hascredit Credit Manager Credit 18
19 OpenSMART Router Incoming Flits From Input Units OpenSMART Router (Baseline) Input Units Switching Unit Output Units >> >> >> >> >> Routing Switch Algorithm Unit Outgoing Flits Outgoing Flits Crossbar Routing Unit 19
20 OpenSMART Router (SMART) Incoming SSRs Incoming Flits Incoming SSRs Input Units SMART Unit OpenSMART Router (SMART) SSR From Local Router SSR Controller SMART Arbiter Output Units Priority >> Switch Unit Outgoing SSRs >> Priority SMART Unit HPCmax Bypass Flag Prioritization by distance -> SSR from a nearer SSR Prioritization router gets the higher priority (Local (distance = 0) has the highest prirority) Bypass MUX Selection Outgoing SSRs Outgoing Flits 20
21 OpenSMART Router (1cycle) Incoming Flits OpenSMART Router (Baseline) Outgoing Flits Cycle 0 Input Units Output Units >> Cycle 1 Switch Unit 21
22 OpenSMART Router (2cycle/SMART) Cycle 1 Incoming SSRs OpenSMART Router (SMART) >> Priority Outgoing SSRs Incoming Flits Cycle 0 Input Units Output Units SMART Unit >> Switch Unit Outgoing Flits Cycle 3 22
23 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 23
24 Walk-through Example 1 Router r4 sends a flit to router r7 HPCmax = 3 bypass, bypass, stop Cycle Cycle 1: Multi-hop 0: SSR Send Bypass 110 SSR (SMART 110Setup Request) 110 r5 r6 r7 24
25 Walk-through Example 2 Router Incoming r4 sends a flit to router r7 Router SSRs r5 sends a flit to router r7 Dist = 0 SSR From Local Router SMART Arbiter HPCmax = 3 Dist = 3 Bypass Cycle Cycle 1: Multi-hop 0: SSR Bypass Flag Dist = 2 Priority Send Dist = SSR (SMART 110Setup Request) 110 From: r4 From: r Winner r5 r6 r7 SMART Unit in r5 25
26 OpenSMART: Features Language - BSV and Chisel Flow control - VC and SMART Buffer Management - Credit-based buffer management Router Microarchitecture - 1- and 2-cycle state-of-the-art packet switching router - SMART router 26
27 OpenSMART: Features Routing Calculation - XY, YX, and source-routing - One-hot encoding hop count + shift-based routing calculation - For SMART, routing calculation is done during bypasses VC Selection - FIFO-based dynamic VC selection - Next VC is stored in a separate register - For SMART, VC selection is done during bypasses 27
28 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 28
29 Latency 4X 5X (a) Uniform Random (b) Bit-complement 29
30 Energy Consumption Repeaters require less energy than clocked latches 30
31 HPCmax (a) HPCmax on ASIC (b) HPCmax on FPGA 31
32 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 32
33 Router Area Number of Ports (a) ASIC area (b) FPGA LUTs (c) FPGA FFs 33
34 Router Power Number of Ports (a) ASIC (b) FPGA 34
35 Maximum Clock Frequency 35
36 Outline Motivation: Scalable, Flexible, and Low-cost NoCs Background: SMART NoCs OpenSMART - Design Flow - Building Blocks - Walk-through Examples Case Studies - Mesh vs. SMART - High-radix vs. Low-radix Conclusions 36
37 Conclusion NoCs are crucial components to support many- IP heterogeneous systems Providing connectivity while satisfying their diverse requrements. OpenSMART provides automatic generation of NoCs for many-ip heterogeneous systems Supports recent low latency SMART NoC as well as highly-optimized 1-cycle routers Written in high-level HDLs 37
38 Announcement OpenSMART contributes the open-source hardware ecosystem! Source code will be available in May 2017 Please sign up via our webpage to request the source code Thank you! 38
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