High-Level Simulations of On-Chip Networks
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1 High-Level Simulations of On-Chip Networks Claas Cornelius, Frank Sill, Dirk Timmermann 9th EUROMICRO Conference on Digital System Design (DSD) - Architectures, Methods and Tools - University of Rostock Institute of Applied Microelectronics and Computer Engineering Cavtat, 1st of September 2006 Conference on Digital System Design (DSD)
2 Outline Current situation Development of technology Bus-based system design Network-On-Chip (NOC) Simulator Related work Chosen approach Integration into a design flow Preliminary results Communication System control/monitoring Outlook 1
3 Current situation Development of technology Power dissipation, leakage, power density Performance (frequency, MIPS) Interconnects Parameter variability Reliability Costs Requirements: More MIPS/mm² More MIPS/Watt [Tenhunen, 2005] 2
4 Current situation Bus-based system design Shared communication medium Connected problems: Synchronous design Processor Cache Memory Controller On-Chip Bus I/O Audio RF 3D Graphic Video Bluetooth Chip-Area = 22 mm x 22 mm 3
5 Current situation Bus-based system design Shared communication medium Connected problems: Synchronous design Design-Productivity-Gap Memory-Bottleneck Processor Cache On-Chip Bus Memory Controller Worsening the situation: Chip-Size Interconnects Integration density Parameter variability... and many more I/O 3D Graphic Audio Video RF Bluetooth Chip-Area = 22 mm x 22 mm 4
6 Network-On-Chip (NOC) Route packets, not wires (W. Dally) The network is the computer (J. Gage) Promising properties: Modularity Encapsulation Portability Reuse Scalability Parallelism... Change of Paradigms: Computation Computing-in-time Communication Computing-in-time-and-space 5
![Simulator Related work Prototyping, Test-Chips Star topology for multimedia applications [Lee, 2003] 4x4 mesh network with traffic generators [Mullins, 2006] Parametrizable VHDL-model ported to](/docs-images/74/70662053/images/7-0.jpg "FPGA [Zeferino, 2004] Emulation framework on an FPGA [Genko, 2005] High-level VHDL [Sigüenza, 2002] SystemC approach and design flow [Jalabert, 2004] Event-based C++ Simulator [Wiklund, 2004] 6")
7 Simulator Related work Prototyping, Test-Chips Star topology for multimedia applications [Lee, 2003] 4x4 mesh network with traffic generators [Mullins, 2006] Parametrizable VHDL-model ported to FPGA [Zeferino, 2004] Emulation framework on an FPGA [Genko, 2005] High-level VHDL [Sigüenza, 2002] SystemC approach and design flow [Jalabert, 2004] Event-based C++ Simulator [Wiklund, 2004] 6
8 Simulator Chosen approach Level of abstraction for System-Developers: Modules Logic-Gates Transistors 7
9 Simulator Integration into a design flow 8
10 Preliminary results Communication Network size Routing schemes Packet injection rate Packet congestion 1 0,6 0,2 Links in Y direction Routers in Y direction Link implementation Link width Pipelining links Router in X direction Links in X direction 9
11 Preliminary results System control/monitoring Dynamic power management Power, supply voltage drop, and temperature 4 Distribution of hot spots Tasks, communication, and temperature Static, dynamic display Application example for the temperature distribution of a 5x5 network
12 Outlook Intended investigations / Open issues Operating system (centralized) System control (distributed) Power, temperature Communication-computation trade-offs Hardware reconfiguration Self-healing, Reliability Load balancing, task-mapping Composability of functions/tasks/services Exploitation of parallel structure Programming models Distributed memory Benchmarking Design-space exploration Test and verification 11
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