CS Part III 1 Dr. Rajesh Subramanyan, 2005

Transcription

1 CS Part III 1 Dr. Rajesh Subramanyan, 2005 Memories Chapter 12 Caches And Caching

2 CS Part III 2 Dr. Rajesh Subramanyan, 2005 Topics Introduction Definition Key idea Characteristics of a cache Importance of caching Examples of caching Terminology Locality of reference Best and worst case cache performance

3 CS Part III 3 Dr. Rajesh Subramanyan, 2005 Topics Hit and miss ratio Cache replacement policy LRU Hierarchy ofcaches Improving Cache Performance Caching in Virtual and Physical Memory Improving performance through parallelism Write Through and Write Back

4 CS Part III 4 Dr. Rajesh Subramanyan, 2005 Topics Cache coherence L1, L2, and L3 caches Cache Flush Summary

5 CS Part III 5 Dr. Rajesh Subramanyan, 2005 Introduction Several slides missing

6 CS Part III 6 Dr. Rajesh Subramanyan, 2005 TLB and Demand Paging TLB TLB is a cache, it holds selected page entries Whenever MMU looks up a page entry, itstores it in the TLB TLB uses LRU Demand Paging isaform for caching, view physical memory as cache and external storage as large data storage physical memory only holds fraction of total pages

7 Cache analysis shows that using demand paging on a computer system with a small physical memory can perform almost as well as the if the computer had a physical memory large enough for the entire virtual address space To achieve high performance, amemory cache is designed to simultaneously search the local cache and access the underlying memory. Parallelism complicates the hardware. CS Part III 7 Dr. Rajesh Subramanyan, 2005 Demand Paging Improving performance through parallelism

8 Caching improves read performance, not write performance CS Part III 8 Dr. Rajesh Subramanyan, 2005 Write Through and Write Back Performance and Coherence Issues Write through when cache is written to, update underlying memory immediately of the change Write-back cache keeps data item locally, and updates memory when it needs to be replaced. uses dirty bit to keep track

9 What if data item in cache updated several times before being replaced? write-back avoids multiple updates to memory Will old value of data in memory be accessed? Not with single processor. Data values are accessed from the closest storage, here cache values will be retrieved CS Part III 9 Dr. Rajesh Subramanyan, 2005 Write-back improves performance

10 Two processors sharing an underlying memory. Because each processor has a seperate cache, conflicts can occur if both processors reference the same memory address. CS Part III 10 Dr. Rajesh Subramanyan, 2005 Cache coherence processor 1 processor 2 cache 1 cache 2 physical memory Solution: need cache coherence protocol

11 Computer systems use a multilevel cache hierarchy inwhich an L1 cache is embedded on the processor chip, and an L2 is external to the processor. Inthe best case, the two-level cache makes the cost of accessing memory approximately the same as the cost of accessing a register CS Part III 11 Dr. Rajesh Subramanyan, 2005 L1, L2, and L3 caches Processor L1 Cache L2 Cache L3 Cache Itanium 2 32KB 256KB 3MB, 4MB, or 6MB Itanium 32KB 96KB 2MB or 4MB Xeon MP 8KB 256KB or 512KB 512KB, 1MB or 2MB P4 8KB 512KB - Example cache sizes.

12 How can a cache resolve the ambiguity that occurs because multiple applications the same range of addresses? Cache Flush cache flush operation disambiguating identifier Cache flushing removing all values from the cache cache must be flushed whenever OSchanges to new virtual address space Disambiguation use extra bits that identify the address space CS Part III 12 Dr. Rajesh Subramanyan, 2005

13 CS Part III 13 Dr. Rajesh Subramanyan, 2005

14 CS Part III 13 Dr. Rajesh Subramanyan, 2005 Slide Missing Implementation of Memory Caching

15 Cache intercepts requests, automatically stores values, and answers requests whenever possible CS Part III 14 Dr. Rajesh Subramanyan, 2005 Summary Caching is a fundamental optimization technique TLB and demand paging are also forms of caching Caches can be organized in a multilevel hierarchy

16 CS Part III 15 Dr. Rajesh Subramanyan, 2005