CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.

Transcription

1 CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng.

2 Part 4: Memory Organization Our goal: understand the basic types of memory in computer understand memory hierarchy and the general process to access memory know how memory is organized to store data understand basics of cache memory including the cache memory address mapping algorithm from main memory Understand virtual memory

3 Part 4: Memory Organization Overview: Introduction to memory Memory hierarchy and how computer access memory How memory is organized to store data and program Two memory technologies - Cache memory - Virtual memory

4 Cache Memory Cache Mapping Schemes

5 Cache Mapping Scheme

6 Cache Mapping Scheme Block (K words) Direct mapping Fully associative mapping Set associative mapping

7 Why not direct mapped cache Suppose a program generates a series of memory references such as: 50, D0, 50, D0, 50, D0,... The cache will continually evict and replace blocks. The theoretical advantage offered by the cache is lost in this extreme case because the cache miss rate is 100% This is the main disadvantage of direct mapped cache. Other cache mapping schemes are designed to prevent this kind of thrashing, including fully associative cache and set associative cache

8 Fully associative mapped cache Instead of placing memory blocks in specific cache locations based on memory address, we could allow a block to go anywhere in cache. In this way, cache would have to fill up one by one before any blocks are evicted. This is how fully associative cache works. In fully associative cache, a memory address is partitioned into only two fields: the tag and the word.

9 Fully associative mapped cache Suppose, we have 8-bit memory addresses and a cache with 16 blocks, each block include 8 (i.e.2 3 ) bytes. The field format of a memory reference is: 5 bit = 8bit -3bit Tag 5 bit Word 3 bit When the cache is searched, all tags are searched in parallel to retrieve the data quickly. However, this requires very special, costly hardware to be implemented

10 Set associative mapped cache Set associative cache combines the ideas of direct mapped cache and fully associative cache. An N-way set associative cache mapping is: like direct mapped cache in which a memory reference maps to a particular location in cache. Unlike direct mapped cache, a memory reference maps to a set of several (N) cache blocks, similar to the way in which fully associative cache works. Instead of mapping anywhere in the entire cache, a memory reference can map only to the subset of cache blocks.

11 Set associative mapped cache The number of cache blocks per set in set associative cache varies according to overall system design. For example, a 2-way set associative cache can be conceptualized as shown in the schematic below. Each set contains two different memory blocks.

12 Set associative mapped cache In set associative cache mapping, a memory reference is divided into three fields: tag, set, and word, as shown below. The set field determines the set to which the memory block maps. Suppose we have a main memory of 2 8 bytes. This memory is mapped to a 2-way set associative cache having 16 blocks where each block contains 8 (i.e.2 3 ) bytes. Since this is a 2-way cache, each set consists of 2 blocks, and there are 8 (i.e.2 3 ) sets. Thus, we need 3 bits for the set, 3 bits for the word, giving 2 leftover bits for the tag: 2 bit = 8bit -3bit -3bit Tag 2 bit Set 3 bit Word 3 bit

13 Replacement policy in cache memory In direct mapped cache Each main memory block only maps to one specified cache block So we have no choice and have to replace that block In fully or set associative mapped cache Least Recently Used (LRU) algorithm keeps track of the last time that a block was assessed and evicts the block that has been unused for the longest period of time e.g. in 2-way set associative, which of the 2 block is LRU? First in first out (FIFO) algorithm replaces the block that has been in the cache the longest, regardless of when it was last used Random algorithm picks a block at random and replaces it with a new block.

14 Summary on Cache Memory Cache memory gives faster access to main memory Cache maps blocks of main memory to blocks of cache memory. There are three general types of cache: Direct mapped, fully associative and set associative. Most of today s small systems employ multilevel cache hierarchies. Level1 cache (8KB to 64KB) is situated on the processor itself. Access time is typically very fast about 4ns. Level 2 cache (64KB to 2MB) may be on the motherboard, or on an expansion card. Access time is usually around 15-20ns. Accordingly, the Level 3 cache (2MB to 256MB) refers to cache that is situated between the processor and main memory

15 Thank you for your attendance Any questions?