Heavy Photon Search Data Acquisition

Transcription

1 Heavy Photon Search Data Acquisition Presented by Ryan Herbst PPA Engineering 5/25/2011 1

2 Overview Data Output & Control 1GigE Read Out Board Ethernet Switch Processor Blade Trigger Board ATCA Crate RTM RTM Differential Analog Clock & Control Clock & Trigger Chamber With Hybrids 2.5V 1.25V Bias Power Supplies DAQ contained in ATCA chassis Common digital read out board 4 daughter boards each controlling 3 hybrids Amplifier and ADC contained on RTM board Off-the-shelf ATCA processor blade supporting Linux OS Off-the-shelf ATCA switch card Trigger board for future integration Same hardware as read out board with different RTM PPA Engineering 5/25/2011 2

3 Hybrid CLKP/M Buff/Dist OUT0P/M TRGP/M Buff/Dist OUT1P/M OUT2P/M SCLK SDA RST_L OUT4P/M OUT5P/M 2.5V Bias 1.25V Incoming clock & trigger buffered, 2 loads per output (2.5V supply) Each has a unique I2C address Each hybrid has its own I2C bus analog outputs buffered with gain = 1 differential amplifier Gain is adjustable if required Power inputs distributed to all parts 2.5V = 690mA nominal / 1455mA worst case 1.25V = 325mA nominal / 825mA worst case Bias routed directly to wire bond pads with local bypassing Internal current reference used PPA Engineering 5/25/2011 3

4 Hybrid Power R=0 R=0 C LVDS s 2.5V 1.25V VDD GND C C CHV GND VSS Bias In CHV R CHV R CHV CHV BIAS Pads Bias GND R CHV capacitors are 2KV (Capacitor High Voltage) LVDS buffers isolated from planes/traces Conductive supports tied through impedance to GND Output differential signals centered around 1.25V ATCA chassis ground should be at same (or reasonably close) to GND on hybrid Need to generate overall grounding diagram. PPA Engineering 5/25/ R Conductive Support

5 RTM / COB Overview Analog Data From 3 Hybrids (15 Channels) 5 x s 5 x ADC 5 x s 5 x ADC 5 x s 5 x ADC ADC Data to (COB) ADC Control From (COB) Each Hybrid Gets Its Own Clock, Trigger & I2C Signals Clock s Trigger s I2C Fan Out Clock From (COB) Trigger From (COB) I2C & Select From (COB) 1 RTM per main board (COB Carrier On Board) COB supports 4 cards Each COB connects To ¼ of an RTM ¼ of an RTM supports 3 Hybrids (15 s) Total of 12 Hybrids (60 s) per RTM/COB combination Independent clock & I2C per ¼ RTM 2 8-Channel ADC devices per ¼ RTM, 8 ADCs in total I2C section uses transistor drivers & select lines, avoiding standard I2C buffers PPA Engineering 5/25/2011 5

6 RTM Analog Data Differential Differential Amplifier / Gain = Differential 14-bit ADC (1 of 8 Channels) LVDS DDR Digital Data LVDS 280Mhz Data Clock LVDS Data Alignment LVDS 40Mhz Sample Clock Input differential amplifier with Gain = (replicated from ARC) Input signal +/- 400mV * = +/- 574mV ADC range Is +/- 1V, room for increased gain Add gain In Hybrid buffer? Input analog signal differentially terminated to 1.25V Hybrid driver should have similar ground reference Option to terminate with floating parallel resistor Signal still needs to be close to 1.25V ADC continuously 40Mhz chooses which samples are valid based upon trigger signal 14-bit differential ADC Separate clock from Hybrid distribution Allows for sample phase adjustment PPA Engineering 5/25/2011 6

7 COB Overview RTM Board 0 (DPM) Board 1 (DPM) Board 2 (DPM) Board 3 (DPM) Fulcrum Ethernet Switch Switch Control & Timing Dist. Board (DTM) Ethernet IPMB Power & Reset Clock & Trigger ATCA Back Plane Clock & Trigger COB (Carrier On Board) Developed at SLAC as standard DAQ platform Supports 4 mezzanine cards (DPM) Interconnected by Fulcrum Ethernet switch Each has connection to ¼ RTM Switch/Timing control board (DTM) Simple clock fanout and EEPROM config of switch for our experiment Supports more intelligent switch control & external IO for some applications Fans out backplane timing & trigger signals to boards PPA Engineering 5/25/2011 7

8 Data Processing (DPM) RTM ADC Control 15 Channels Data Reduction s UDP Core 10G MAC/XAUI COB Switch Timing Control Register Read/Write Clock / Trig Incoming data stream Trigger rate = 50Khz Raw data rate = 15 s * 128 Channels * 16-bits * 6 samples * 50Khz = 9.2Gbps Assuming data rate of < 1Gbps after applying thresholds Simple approach is to check if any of 6 samples are above threshold Each talks directly to ATCA Linux blade over UDP Register read/write protocol Bulk data transfer Trigger & clock distributed from back plane Optional buffering using DDR3 SDRAM module Not needed but could be used to locally store some raw data to tune trigger PPA Engineering 5/25/2011 8

9 Trigger Interface Board System Clock Trigger Data Sync Trigger RTM s Timing Timing Message To Linux Blade Clock, Trigger & Sync To ATCA Backplane Standard ATCA clock & trigger distribution Uses multi-drop LVDS backplane for clock & trigger Re-use of data processing board & Trigger board has only one daughter board (DPM) loaded Trigger specific RTM May be able to use front panel of DTM for timing signals on one of the readout boards CTM is designed to support front panel IO Eliminates extra ATCA blade Any readout board can become timing master PPA Engineering 5/25/2011 9

10 ATCA Processor Blade COB Board 0 COB Board 1 ATCA Ethernet Switch UDP Stack Event Builder To System Event Builder / Storage COB Board N Control & Monitoring Software To / From Run Control Trigger Board Control & monitoring software Manages & configures Hybrids & s Collects and reports system/run status Event builder Combines data from all s into a single event frame Additional data reduction if necessary PPA Engineering 5/25/

11 Development Board Analog Data From Hybrid 5 x s 5 x ADC Clock s Trigger s I2C Fan Out Control Fiber Optic Link PGP or Ethernet Single board to support 1 Hybrid 5 channels of input differential amplifier/buffer 5 ADC channels (1 8-channel ADC chip) Small for data collection Fiber interface using SLAC standard DAQ protocol (PGP) Existing generic software and control GUI for easy development UDP can also be used PPA Engineering 5/25/