CBC performance with switched capacitor DC-DC converter. Mark Raymond, Tracker Upgrade Power Working Group, February 2012.

Transcription

1 CBC performance with switched capacitor DC-DC converter Mark Raymond, Tracker Upgrade Power Working Group, February

2 CBC power features 2 powering features included on CBC prototype pads for test features 2.5 -> 1.25 DC-DC converter LDO regulator (1.2 -> 1.1) feeds analog FE provides stable voltage rail and supply noise rejection 2.5 -> 1.2 DC-DC converter allows to power CBC using single 2.5 V rail thanks to Michal Bochenek and Federico Faccio for the design and help with incorporating the layout into the CBC 7 mm amplifiers & comparators TEST DEVICES 256 deep pipeline + 32 deep buffers power SLVS data clock trigger I 2 C, reset power LDO bandgap pads for test features 4 mm bias generator 2

3 CBC power features - DC performance 1.25 DC-DC switched capacitor converter DC-DC & LDO outputs converts 2.5 -> ~ 1.2 clearly functioning, high efficiency ~ 9% study of DC-DC switching effects on noise follows in next slides Volts LDO input LDO output LDO linear regulator provides clean,regulated rail to analog FE ~ 1.2 Vin, 1.1 Vout dropout ~ 4 mv for 6 ma load provides > 3dB supply rejection up to 1 MHz for further details see: CBC_Tracker_Electronics_May_11.pdf 1.5 LDO dropout LDO output [V] us / division 4 mv 1.1 3mA load 6mA load 1.15 LDO input voltage [V] 1.2 3

4 +2.5V GND 1n 1uF DC-DC DC-DC diff. clock (CMOS) DC-DC 1.2 GND(D) VDDD all GNDs connected together 1n DC-DC powering option can power CBC from single +2.5V supply 1 MHz diff. clock to DC-DC circuit DC-DC 1.2V feeds VDDD (dig. supply) and VLDOI (LDO I/P) 4 external capacitors minimum (actually 5 in this picture) CBC on test board GND +2.5 GND DC-DC 1.2 LDO GND(A) VDDA 1n bandgap VLDOO VLDOI 1n GND GND BGI linked (or not) to BGO maybe don t need this cap 4

5 +2.5V GND 1n to study effects on analog performance 1uF DC-DC DC-DC diff. clock (CMOS) DC-DC 1.2 GND(D) VDDD all GNDs connected together 1n external DC supply at least 2 possibilities for adverse effects 1) noise on DC-DC O/P rail could affect analogue performance via VDDA rail (though LDO should reject) 2) DC-DC circuit noise could couple to front end via another path (substrate, GND,..) study here concentrates on 2 nd path by providing analogue rail from external clean supply will provide digital rail either from external supply or from DC-DC output (when DC-DC operating) GND(A) LDO VDDA 1n bandgap VLDOO VLDOI 1n external DC supply BGI linked to BGO 5

6 adding external capacitance want to measure noise (from s-curves) dependence on external capacitance plug-on boards containing arrays of capacitors connect to bonded out channels acquire s-curve for one of the bonded out channels GND individual channel capacitors GND GND 6

7 no. of events a) Cadded = 1.78 pf s-curves:reference measurement fixed trig., 1.2V b) Cadded = 3.78 pf measure s-curves for single channel for different external capacitances conditions for measurements on this slide no. of events fixed trig., 1.2V digital circuitry supplied with external 1.2 V supply DC-DC not running CBC triggered at fixed time following a fast reset c) Cadded = 5.79 pf => always triggering same pipeline location gives cleanest possible measurement as reference no. of events fixed trig., 1.2V (no reason to expect any effect from random triggering, but just to check) comparator threshold VCTH [mv]

8 no. of events fixed trig., 1.2V random trig., 1.2V 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf 44 s-curves: DC supply (random trigger) now repeat for random triggering digital circuitry still supplied with external 1.2V supply DC-DC still not running 8 but fast reset removed no. of events 6 2 fixed trig., 1.2V random trig., 1.2V pseudo-random trigger, so now triggering locations throughout pipeline no effect on s-curves visible (i.e. no effect on noise) c) Cadded = 5.79 pf (as expected) 8 no. of events 6 2 fixed trig., 1.2V random trig., 1.2V comparator threshold VCTH [mv]

9 no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf 44 s-curves: DC-DC running (fixed trigger time) now feed digital circuitry with DC-DC 1.2 V DC-DC now running return to triggering at fixed time following a fast reset no. of events 6 2 fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC DC-DC clocked at 1 MHz with fixed phase relationship to fast reset once again - no significant effect on s-curves c) Cadded = 5.79 pf 44 => DC-DC circuit doesn t affect intrinsic noise 8 no. of events 6 2 fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC comparator threshold VCTH [mv]

10 no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf 44 s-curves: DC-DC running (random trigger) now try pseudo-random triggering again DC-DC still running s-curves now distorted for larger capacitance 8 no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC c) Cadded = 5.79 pf 44 => something to do with random triggering when DC-DC circuit operating an effect associated with specific pipeline locations? try to understand what s going on with a more systematic study => look at s-curve dependence on triggered pipeline location 8 no. of events 6 2 fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC comparator threshold VCTH [mv]

11 s-curve dependence on triggered pipeline loc n 1 8 Cadded = 1.78 pf acquire s-curves with increasing separation between fast reset time and trigger position (25 nsec steps) no. of events 6 4 DC-DC circuit operating results here for smallest capacitance: 2 not all s-curves in same position S-curve mid-points [mv] VCTH [mv] 4 steps noise [mv rms] plotting s-curve mid-point vs vs. trigger position shows repetitive structure separation between positive (or negative) shifts = 4 steps = 1 µsec = DC-DC period pedestal shift only, no change in shape => intrinsic noise unaffected trig. pos'n [ 25 ns steps]

12 increasing external capacitance 1 8 Cadded = 3.78 pf effect becomes much more noticeable no. of events VCTH [mv] S-curve mid-points [mv] noise [mv rms] trig. pos'n [ 25 ns steps]

13 for largest external capacitance 1 no. of events Cadded = 5.79 pf s-curves in top plot colour coded to show which ones correspond to which point in bottom plot some distortion visible for most negatively shifted curves (out of amplifier linear range) VCTH [mv] so DC-DC circuit operation somehow affects channel pedestal magnitude of effect proportional to external capacitance to ground S-curve mid-points [mv] noise [mv rms] trig. pos'n [ 25 ns steps]

14 repeat for external DC supplies 1 just to check no. of events Cadded = 5.8 pf effect goes away completely if DC-DC circuit not operational VCTH [mv] S-curve mid-points [mv] noise [mv rms] trig. pos'n [ 25 ns steps]

15 what s going on? C f behaviour most likely due to DC-DC circuit operation causing difference between internal and external grounds would result in spurious charge injection proportional to C EXT C EXT GND INT GND EXT can anything be done to improve situation? v noise better connection between GND INT and GND EXT? ultimately limited by bond wires is present test setup optimal? have tried to improve following discussions with CERN engineers start by taking a critical look at CBC test board 15

16 CBC test board copper layout top bottom double-sided pcb ~ solid ground on bottom surface connected (PTH) to ground on top surface CBC glued on the centre ground area ground brought out from under chip to bond pads 16

17 possible deficiencies top too cautious about keeping bonding area clear - capacitors could have been positioned closer to chip could have put more plated through holes in have tried to make improvements to existing board to see whether performance is affected 17

18 improvements have tried to improve grounding and decoupling by turning this into this this is the final version of the test board after all modifications chip glob-topped to protect bonds will go through modifications step-by-step for clarity - describing changes and showing resulting effects on s-curves 18

19 first take reference measurement reference ch ch ch measure s-curves as before for 3.8 pf added external cap. look at 3 channels at top, middle and bottom of chip 19

20 improved ground coupling between CBC and external capacitor board three lengths of tinned copper braid soldered to ground plane on back of CBC board connected to ground area on external capacitor board 2

21 effect of improved grounding reference ch124 ch6 ch improved grounding to external caps ch124 ch4 5 ch6 5 5 some differences - most noticeable for channel 6 21

22 improved 2.5 V rail decoupling solder 2.5 V 2.5V decoupled closer to the chip extra copper piece added adjacent to 2.5 V input, soldered to ground additional 1 nf capacitor soldered as close as possible to bond pad 22

23 improved 2.5 V rail decoupling - reality extra copper piece extra capacitor 23

24 effect of improved 2.5 V decoupling reference improved grounding to external caps added cap on 2.5V rail ch ch ch ch124 ch4 5 ch ch ch6 5 ch4 5 ch124 gets appears to get worse, ch 4 gets better 24

25 extra ground contacts 25

26 effect of extra ground contacts added cap on 2.5V rail ch ch ch extra ground contacts ch124 5 ch6 5 ch4 5 not much difference 26

27 additional shielding copper tape cover over top of capacitors - soldered round edge 27

28 efect of additional shielding added cap on 2.5V rail ch ch ch extra ground contacts ch124 5 ch6 5 ch added shielding ch124 5 ch6 5 ch4 5 channel 6 now looks a bit strange 28

29 some more capacitor repositioning DC-DC output decoupling & floating capacitor as close as possible to chip 29

30 some more capacitor repositioning 3

31 effect of capacitor repositioning added shielding ch124 5 ch6 5 ch4 5 output & floating caps as close as possible ch124 ch6 ch some effects on all three channels not obvious what conclusions to draw 31

32 conclusions? reference after everything ch ch ch ch ch ch no dramatic improvement in behaviour clearly some effects but no strong indication of a magic solution might be able to do better with new improved board layout? but seems unlikely that all undesirable effects can be made to go away 32

33 summary C f fundamental performance of DC-DC circuit itself is good high efficiency for 2:1 step down conversion no significant effect on intrinsic noise C EXT but switching transients appear to couple to internal chip ground causing pedestal shifts - magnitudes dependent on external capacitance GND EXT v noise GND INT worth noting: this would likely not be a problem for hybrid pixel chips low sensor capacitance low inductance bump-bond coupling between sensor and chip grounds what next? more measurements? - I m open to suggestions CBC2 will include same DC-DC circuit bump-bond layout ought to help significantly with performance (better coupling between on and off-chip grounds) 33