Interfacing the EL with the SED133X Controllers

Transcription

1 Interfacing the EL with the SED133X Controllers Application Note This Application Note focuses on interfacing to the SED133X series controllers from SMOS. While this document was written with the EL display in mind, the concepts and general equations can be applied to many other displays with the same success. Copyright 1998 by Planar Systems, Inc. Planar and The Definition of Quality are registered trademarks of Planar Systems, Inc. Planar provides this information as reference only and does not imply any recommendation or endorsement of other vendors products. This document is subject to change without notice. AN December 1998 The Definition of Quality

2 Table of Contents INTRODUCTION...3 The S-MOS Controllers...3 IMPLEMENTATION OVERVIEW...4 Hardware Implementation...4 Frequency Selection...4 Setting The Oscillator Frequency Based On The Desired Refresh Rate...5 Determining The Maximum Refresh Rate...6 RAM/ROM...6 Interface Mode...6 Software Implementation...6 MEMORY ARBITRATION CONFLICT IN THE SED133X SERIES CONTROLLERS...8 SUMMARY...9 APPENDIX A: S-MOS CONTACT INFORMATION...10 APPENDIX B: SCHEMATIC 133X INTERFACE Planar Application Note

3 Introduction Systems designers are faced with a wide variety of flat panel display technologies which in turn require the selection of an appropriate interface solution from a wide range of options. Planar electroluminescent (EL) Small Graphics Displays (SGD) incorporate a simple, yet effective, interface that is similar to many LCD interfaces. This interface is supported by a wide variety of off-the-shelf chipsets which will provide display control functionality, thus freeing the system processor for other duties. Designers can select the appropriate chipset that best suits their architecture and pricepoint. Choosing the best interface becomes a decision based on tradeoffs in cost, size, complexity and time to market. This application note describes the basic principals of interfacing the EL to the SED133X controller ICs made by S-MOS Systems. The S-MOS Controllers The S-MOS display controllers have been designed to be simple, cost effective methods of interfacing to standard EL, LCD and VF type displays. The controllers usually reside between the main system controller or processor and the display inputs and take care of the mundane and repetitive task of constantly refreshing the display data. Though these chips have slightly different interfaces, in general, they behave like an SRAM component to the host processor. Thus any data that is written to the correct address in the virtual SRAM will be mapped to the display. The entire interface solution consists of the SMOS display controller chip, a small memory device (SRAM or DRAM) usually an oscillator and some glue logic. There are two families of S-MOS controllers. The SED133X family includes the SED1330, SED1335 and SED1336 controllers. The key feature of these controllers is that they have character generation onboard and interface to the host over an 8-bit port instead of a full address and data bus. In general, the SEDl33X controllers are made for low cost, simple systems. They do not support dual scan displays. The SED135X family includes the SED1351 and SED1352 controllers. These controllers interface to the host processor over a full address and data port, but do not have character generation onboard. These controllers have faster access time, support dual scan displays and are considered to be a higher performance option to the SED133X series. The SED135X family will be discussed in a separate application note. This application note focuses on interfacing to the SED133X series controllers. While this application note was written with the EL in mind, the concepts and general equations can be applied to many other displays with the same success. Application Note

4 Implementation Overview From a designer s standpoint, implementing a new interface for a display consists of developing the hardware and software. Though the 133X series chipsets are very simple to integrate in the system, a number of choices must be made at the hardware level to insure the required performance level is achieved. Once the hardware is set up properly, the remaining challenge is implementing the software for the specific display and requirements in your application. Hardware Implementation The schematic below outlines an example of integrating the SED133X series controllers into an application. The entire solution consists of basic glue logic to decode the memory address range of the controller, an external crystal connected to the onboard oscillator and some memory devices. A complete schematic is included in figure 3 at the back of this document. Figure 1 This block diagram outlines a simple, yet complete, 1335 interface example. It consists of RAM, an oscillator circuit, and connectors to the microprocessor and display. Frequency Selection The exact crystal frequency chosen depends entirely upon the application and requirements. There are a number of things to consider when choosing the controllers crystal frequency for use with the EL The output clock frequency from the SED133X controllers is approximately 1/4 of the crystal frequency. Therefore, if the maximum allowable input clock frequency for the SED133X of 10MHz is chosen, the output clock frequency that the display will see is only 2.5MHz. This is well below the maximum allowable input clock frequency for the EL which is 7.143MHz. The output clock frequency controls how fast data is loaded into the display and may impact how fast the display can be refreshed. In the SED133X controllers, a register value is typically one less than the absolute value of the register. Therefore if the C/R register (the C/R register controls the number of horizontal bytes in the display) is set to 39 then the actual number of horizontal characters is = 40. For the equations that follow, 4 Planar Application Note

5 square brackets around a parameter name indicate the number represented by the parameter, rather than the value written to the parameter register. For example, [C/R] = C/R + 1. For the EL , the following base settings apply: [C/R] 40 This sets the total number of visible horizontal bytes on the display. The total pixels is given by the following equation: total pixels = [C/R] X 8 = 40 X 8 = 320. If [C/R] is set too low the controller will not shift enough column data out. The display will then compress the data vertically and probably flicker. This happens because the display will wait until it has a full line of data in its buffer before continuing onto the next line. If [C/R] is set too high the image will appear normal because the display will simply ignore the extra data. [TC/R] 44 This sets the total horizontal time including blanking. It can be used to create a virtual display area or extend the period of a line for timing reasons. According to the SMOS specification, this register must always be at least 4 greater than [C/R]. [L/F] 240 This register sets the total number of lines on the display. The maximum value is 256 and minimum is 1. If [L/F] is set to be greater than the actual number of lines in a display, the image will be normal because the display will ignore the extra lines of data. If [L/F] is set to be less than the actual number of lines in the display the image may flicker because the display always waits until it fills all 240 lines with data before accepting another VS. The following equations are helpful when setting up your hardware and software system. Setting The Oscillator Frequency Based On The Desired Refresh Rate To determine the main oscillator frequency (fosc) required for a given refresh rate, use the following equation where frr is the targeted refresh rate for the application: fosc ([TC/R] x 9 + 1) x [L / F] x frr Assuming a 60Hz refresh rate: fosc (44 x 9 + 1) x [240] x 60 = MHz In practice, the oscillator should be set to allow the maximum refresh rate required. The registers are then changed to lower the overall refresh rate. This can be accomplished by changing the TC/R register which will add extra clocks per line. The display will ignore the extra clocks per line, and the overall scan frequency will be decreased proportionately. Application Note

6 Determining The Maximum Refresh Rate If the oscillator frequency is known, the maximum refresh rate (frr) can be determined by the following equation: frr = fosc ([TC/R] x 9 + 1) x [L / F] Assuming a 10MHz oscillator frequency: frr = 10 Mhz = 105 Hz (44 x 9 + 1) x 240 RAM/ROM The SED133X provides a number of options for integrating RAM and ROM for the display data and character information. The controller can handle up to 64Kbytes of external static RAM which would translate to a little over six complete graphic screen images for a monochrome display that can be in memory at one time (64Kbytes total memory / 9600 bytes per display page [9600=(320 pixels horizontal X 240 pixels vertical) / 8 bits per byte]). The exact memory configuration for any particular application depends on the following: character generation requirements, RAM availability, and the desired number of memory pages. Consult the SED133X technical manual for more details on choosing RAM/ROM. Interface Mode The SED133X comes with two interfaces modes which are selected by an input pin on the controller. The user may select between either Motorola or Intel style signals. Consult the SED133X technical manual for details on how to choose the interface mode. Software Implementation Controlling the SED133X from a microprocessor can be accomplished over the 8- bit port by selecting the proper commands and writing the proper data to the registers in the controller. The controller has thirteen commands that will put the chip in various operating modes. For instance, the first command is a system set command which specifies that the next eight bytes written to the data port will configure things like display size, refresh rate, display type, etc. Due to the number of possible configurations, it is impractical to go through all of the options here; this application note is limited to the basics. Please refer to the SED133X technical manual for details of the various commands and modes available in the SED133X controllers. 6 Planar Application Note

7 After power up, the following sequence of commands will set up the EL display in text mode and write sample text to the display. Of course, all systems architectures will vary, so you should use this code as a starting point only. The example output for this program is shown at right. Fig. 2 Program Output Example DD=DATA BYTE (HEX) A=ADDRESS LINE (A0) Register list for setup and writes some text to the display DD A Comment DD A Comment DD A Comment 40 0 System Set 48 1 H 45 1 E I 44 1 D S I I 4E 1 N 2F S 20 1 F T T 48 1 H H 45 1 E 44 0 SCROLL 45 1 E F 1 O F0 1 4E 1 N C 0 CRSRDIR 4C 1 L A 0 PXL SHFT 59 1 Y 46 0 MEMWRITE E MEMWRIT 46 1 F F 1 O 42 0 DATAWRIT E 1 N B 0 OVERLAY 54 1 T set up the overlay options 46 0 MEMWRITE DISP ON 0B 1 load new address for next line turn the display on ADD WRT 42 0 DATAWRIT load a starting location on screen DATAWRIT C F 1 O E 1 N T I 52 1 R E 1 N 4F 1 O C 4C 1 L C 1 L 4C 1 L U 45 1 E 54 1 T 44 1 D 52 1 R Application Note

8 Memory Arbitration Conflict in the SED133X Series Controllers The SED133X controllers have a memory arbitration conflict problem with virtually all versions of the product. This conflict occurs when the display controller is actively writing data to the display and a data write occurs on the host port. The data from the host port overwrites the data that is being written to the display, which manifests itself by creating flicker, or noise, on the display. The noise is only apparent during the data write. As soon as the data write is complete, the screen image returns to normal with no artifacts, or noise, of any kind. The data in the frame buffer is not corrupted, only the data which is streaming out to the display. There are three ways to deal with this problem. The first option is to simply ignore the problem. If you are not updating a substantial portion of the screen, or your images are generally constant, you won't notice much flicker or noise. The second option is to poll the status flag, bit 6 of the 8-bit port. When this flag is set LOW (0), the user may write to the memory without causing any flicker or noise on the display. Though a simple solution in theory, many designers are frustrated by the requirement to have their controller poll this bit to find out when the display can be written to. It can create a significant amount of overhead in the host processor code. Lastly, it is possible to monitor the LP output from the SED133X products. This signal is HIGH (1) when it is possible to write to the memory without causing any flicker or noise on the display. This signal is LOW (0) when writing to the memory will cause flicker. This signal can be fed into an interrupt on a processor which will allow the processor to simply be interrupted instead of having to poll the status bit to determine when the controller may be written to. The extent of the memory arbitration problem will vary from application to application. It is possible to determine the percentage of time that the display may be updated in a given application if the main oscillator frequency, TC/R and C/R are known by using the following equations: First, determine the total line time (t LINE ) by, tline = ([TC/R] x 9 + 1) fosc For our example with a 10MHz clock, tline = 44 x MHz = 39.7 us 8 Planar Application Note

9 Next, determine the total time (t DATA )that the controller will be sending data to the display, tdata = ([C/R] x 9 + 1) fosc tdata = ([C/R] x 9 + 1) fosc = 36.1 us For every 39.7uS, there will be 3.6uS (39.7uS uS=3.6uS) of time available where you can update the display memory without causing artifacts. This example assumes the maximum clock rate, and minimum line time which corresponds to the maximum refresh rate. As the refresh rate is reduced, the amount of time increases proportionately. The following equation may be used to determine the percentage of time the display may be updated without causing artifacts as a function of refresh rate: AccessRatio(%) = 100 x 1- [ [[L/F] x frr] x [[C/R] x 9 + 1] ] fosc For a 60Hz display, [240 x 60] x [40 x 9 + 1] AccessRatio(%) = 100 x 1- = 48% 10 MHz [ ] The display may be written to roughly 48% of the time without causing artifacts. Summary The SED133X controllers provide a simple, low cost method of integrating the EL display into many applications. Though this application note was designed with the EL in mind, the concepts and general equations can be applied to any size display with the same success. Application Note

10 Appendix A: S-MOS Contact Information S-MOS Systems, Inc North First Street San Jose, California USA +1 (408) The table below outlines various features of each controller. For complete details of the SED products, refer to the individual model design guides from S-MOS Systems. Part Number SED1330 SED1335 SED1336 SED1351 SED1352 Internal CGROM 160 chars (5x7) 160 chars (5x7) 160 chars (5x7) N/A N/A CPU Interface (Bits) 68xxx , 16 8, 16 80xx , 16 8, 16 MPU 8, 16 ISA 8, 16 Digital RGB Display Size Up to 640x256 dots at a duty of 1/256 Up to 640x256 dots at a duty of 1/256 LCD: 640x200, TV: 256x200 max. duty of 1/1024 up to 1024x1024 1/1024 single mode, 1/ 2048 dual mode, 640x480, 320x200 Frame Buffer Support 64KB SRAM 64KB SRAM 64KB SRAM 64KB SRAM 128KB SRAM Frame Buffer Data Bus Width (bits) /16 fclk, max (MHz) fosc (MHz) Supply Voltage Gray Shade Levels 5V x x x FOA x 3V x x FLB x 2 x x x 4 x x 16 x Display Data Bus (bits) 4 x x x x x 8 x x Control Register Panel Type 3 layers, smooth scrolling, inverse video, text and graphic display 3 layers, smooth scrolling, inverse video, text and graphic display LCD/TV support, 3 layers, smooth scroll, inverse video, text & graphic display 2 layers, data OR function, smooth scroll, overlay, inverse video Passive x x x x x TV ntsc/pal 10 Planar Application Note

11 Appendix B: Schematic 133X Interface Figure 3. Detailed schematic 1335 interface example. It consists of RAM, an oscillator circuit, and connectors to the microprocessor and display. Application Note

12 North & South America OEM Sales Planar Systems, Inc NW Compton Drive Beaverton, Oregon Tel. +1 (503) Fax +1(503) AN Europe & Asia-Pacific OEM Sales Planar Systems, Inc. P.O. Box 46, Olarinluoma 9 FIN Espoo, Finland Tel Fax intlsales@planar.com Visit the Planar web site at