Chapter 9 - PIO Verses DMA Transfers Page 9-6

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1 Chapter 9 - PIO Verses DMA Transfers Page 9-6 The listing example on the previous page is for ATA transfers, which expect 512-byte sector transfers. ATAPI transfers are slightly different since you may make a transfer that is not the size of a sector. See the example source code in the utils\hdc_type directory of the available CD-ROM for more. DMA Transfers For DMA transfers, by following the sequence explained before, you have successfully done almost everything you need to do up to this point of actually making the transfer. However, you must first set up the DMA for the transfer. In the sequence explained before, sometime before you send the command to the ATA_COMMAND register, you must first set up the DMA registers and a memory buffer used to make the transfer. If the ATA Controller is a PCI device, that PCI device may have a Bus Master function that communicates with the memory bus directly. Bit 7 in the PCI s Programming Interface register will indicate whether it has a Bus Master DMA controller or not. This Bus Master is part of the PCI function and is used for all DMA transfers associated with the two channels of the controller. If the ATA Controller is on the ISA bus, the ISA DMA controller is used for DMA transfers. This form of DMA uses the 8237 DMA controller to transfer 16-bits at a time. However, with later 32-bit machines, it is faster to read a count of bit dwords via PIO transfers than it is to set up the ISA DMA and use it. Also, most computers now have at least a PCI bus and use PCI ATA controllers. Therefore, all DMA references from this point on will be for the PCI and use the PCI s Bus Master function. For more on ISA DMA, see Chapter 4 on how the FDC uses DMA. Bus Master DMA The PCI bus uses the DMA associated with the Bus Master address received while the PCI detection was executed. For the PCI ATA interface, the Bus Master I/O address is received from BAR 4, or offset 0x20 in the PCI Configuration Space. Please note that if the Programming Interface field in the PCI Class Code set does not have bit 7 set, this device does not support Bus Master DMA and you must use the ISA DMA or PIO transfers. This I/O address uses the same addressing as the other addresses, with bit 0 indicating Port I/O or Memory Mapped I/O, etc.

2 Page 9-7 FYSOS: Media Storage Devices This 16-byte address space contains the DMA registers for both the Primary and the Secondary channels of this PCI device. Table 9-1: The DMA Bus Master Registers The DMA Bus Master Registers Name Off Size Type Description Channel 0 BM0_COMMAND 00h 1 R/W Command Register (Primary Bus) BM0_RESV0 01h 1 n/a Device Specific (Reserved) BM0_STATUS 02h 2 R/WC Status Register (Primary Bus) BM0_RESV1 03h 1 n/a Device Specific (Reserved) BM0_ADDRESS 04h 4 R/W Address Register (Primary Bus) Channel 1 BM1_COMMAND 08h 1 R/W Command Register (Secondary Bus) BM1_RESV0 09h 1 n/a Device Specific (Reserved) BM1_STATUS 0Ah 2 R/WC Status Register (Secondary Bus) BM1_RESV1 0Bh 1 n/a Device Specific (Reserved) BM1_ADDRESS 0Ch 4 R/W Address Register (Secondary Bus) The first set, the Primary Bus, is used for the first two drives on the first controller, also called the first channel, while the second set is for the second channel. You only need one set per channel, since you can only read or write from one drive on a channel at a time. Remember that you must select the drive to use it, hence you can only read or write from the selected drive. DMA Command Register The Command register has two usable bits. Table 9-2: DMA Bus Master Command Register DMA Bus Master Command Register (BMx_COMMAND) Bit R/W Description 7:4 R Reserved 3 R/W Read/Write Control 0 = Read (Read from memory/write to the disk) 1 = Write (Read from the disk/write to Memory) 2:1 R Reserved 0 R/W Start/Stop 0 = Disable the Bus 1 = Enable the Bus Bit 3 is used to tell the controller which direction to transfer data. A clear bit means reading from the memory and writing to the disk. A set bit means to read from the disk, writing to the memory.

3 Chapter 9 - PIO Verses DMA Transfers Page 9-8 Bit 0 is used to start or stop the bus. When you have set up the registers and have sent the DMA transfer command to the ATA controller, you then set this bit to start the transfer. Once you have received the interrupt on completion, you must clear this bit. DMA Status Register The Status register gives the status of the bus and the transfer. Table 9-3: DMA Bus Master Status Register DMA Bus Master Status Register (BMx_STATUS) Bit R/WC Description 7 R Simplex 0 = Both the Primary and the Secondary Channels can be used at the same time. 1 = You may only use one Channel at a time. 6 R/W Drive 1 DMA Capable 0 = Drive 1 is not yet capable or is not at all capable of DMA transfers 1 = Host Software has set this bit indicating Drive 1 is ready for DMA transfers 5 R/W Drive 0 DMA Capable 0 = Drive 0 is not yet capable or is not at all capable of DMA transfers 1 = Host Software has set this bit indicating Drive 0 is ready for DMA transfers 4:3 R Reserved 2 R/WC Interrupt 0 = No interrupt is pending on ATA controller 1 = Interrupt has fired on ATA controller 1 R/WC Error 0 = No error occurred 1 = An error has occurred 0 R Bus Master IDE Active 0 = No data is being transferred 1 = Data is currently being transferred Bit 7 indicates that the Bus Master is capable of processing memory on both channels at the same time. Bits 6 and 5 are set by host software once the ATA driver has set the disk for DMA transfers. If the ATA disk is not capable of DMA transfers, these bits must remain zero. Bits 6 and 5 are not used by most systems and are completely ignored by the DMA controller. No need to worry about them here.

4 Page 9-9 FYSOS: Media Storage Devices Bit 2 is set by the controller when the ATA controller has fired an interrupt. This is so that interrupts may be shared throughout the host. If your ATA driver receives an interrupt, you check that this bit has been set. If not, the interrupt fired for a different reason, possibly for another device. If this bit is set, the interrupt was for this device. The PCI will fire an interrupt when either channel has finished the transfer. You must check bit 2 to see which channel it is in reference to. Bit 1 is set by the controller when an error has occurred. Bit 0 is set by the controller when bit 0 of the Command register is set. This bit is cleared by the controller when that bit is cleared or the controller has reached the EOT flag. See a later section for the EOT flag. DMA Address Register The Address register points to a Physical Region Descriptor Table of tasks for the DMA controller to perform. Table 9-4: DMA Bus Master Address Register DMA Bus Master Address Register (BMx_ADDRESS) Bit R/W Description 31:2 R/W Bits 31:2 of a four byte aligned physical address of Descriptor Table 1:0 R Reserved The is the 4-byte aligned physical address of the Bus Master Descriptor Table, also known as the Physical Region Descriptor Table which is explained next. Physical Region Descriptor Table This is a table of tasks for the DMA Bus Master controller to perform. Once bit 0 is set in the Command register, the controller starts with the first 8-byte entry and continues until the bit is cleared, an error occurs, or the current entry contains the EOT flag. This table is a count of two 4-byte dword entries, one right after another, with the following format. Figure 9-1: Physical Region Descriptor Table Entry Bits 31:1 of Physical Base Address of Memory Region 0 EOT Reserved Size in bytes When the Command Register has bit 0 set, the controller will transfer size bytes, the direction determined by bit 3 in the Command Register, to/from the address in the first

5 Chapter 9 - PIO Verses DMA Transfers Page 9-10 dword of the entry. If bit 31 (EOT) is cleared in the second dword, the controller will move to the next entry and make that transfer. The controller will continue to do this until there is an error, the EOT flag is set, or bit 0 in the Command Register is cleared. The count of bytes to transfer must be an even number and less than 65,536 with a value of zero indicating 65,536 bytes. Also note that the physical memory region of the transfer, must not cross a 64k boundary. Note that once the Start bit is set, all transfers in the Descriptor Table must be in the same direction indicated by bit 3 in the Command register. If you write to bit 3, you have also written to bit 0, either stopping the controller, or starting it again, and the controller will start over from the first entry. To change direction, you must stop the controller, re-initialize the Descriptor Table, and then start the controller. One way to get around this is to create two separate Descriptor Tables, one for each direction, then when it is time to change direction, move to the other table. However, you must note that the controller will start at the first of the table each time. You cannot resume from any entry within the table. Example Descriptor Table For example sake, I am going to say that I can only transfer 8 sectors per Descriptor Table entry and I want to transfer 16 sectors to physical address 0x Therefore I need two entries as with the following layout. Listing 9-4: Physical Region Descriptor Table Example #1 // first entry 0x // physical starting address 0x // 4096 bytes 0x x // next physical address // 4096 bytes with the EOT bit set Then in my ATA driver, I would use the ATA_READ_DMA command, indicating I want to read 16 sectors from some LBA address. Once that command is sent, I would set bit 0 of the DMA Command Register. The 16 sectors would be transferred and an Interrupt will fire. Now, you are probably asking why I didn t just use a single entry and transfer 8,192 bytes instead. This is where paging would come into play. If I have system memory paging enabled and my linear address buffer used two separate physical address pages, this makes it real easy to read 8,192 bytes (16 sectors) to those two physical pages, even though those pages may not be physically consecutive in memory.

6 Page 9-11 FYSOS: Media Storage Devices For example, let s say I have a linear address buffer at 0x of 0x2000 bytes in size, 16 sectors worth. As far as my user-space program is concerned, those 0x2000 bytes are consecutive in memory. However, since the host system is using paging, the first 0x1000 byte page of physical memory is actually at 0x and the second 0x1000 byte page is at physical memory address 0x Therefore, by using this DMA Descriptor Table technique, I can read the 16 sectors, 8 sectors each, to those two physical addresses, which will in turn, mean that I read them to the user-space app s linear address of 0x using the following DMA Descriptor Table. Listing 9-5: Physical Region Descriptor Table Example #2 // first entry 0x // physical starting address 0x // 4096 bytes 0x x // next physical address // 4096 bytes with the EOT bit set Read DMA Programming Sequence To read the 16 sectors to the app s linear address of 0x , the ATA driver would follow something like the following steps. 1) Create a Physical Region Descriptor (PRD) Table with the two entries listed in Listing 9-5 above. 2) Write the physical address of this PRD Table to the appropriate channel s BMx_ADDRESS register, making sure the address is on a 4-byte boundary. 3) Clear the Interrupt and Error bits in BMx_STATUS register by writing a 1 to each bit. 4) Send the ATA_READ_DMA command from the ATA driver. 5) Set or clear the Direction bit and set the Start bit in the BMx_COMMAND register. 6) The Controller transfers the data. 7) Once it is done, the ATA device triggers the interrupt. 8) Was the Interrupt bit set in the BMx_STATUS register? If so, the ATA Device triggered the interrupt. If not, a different device triggered the interrupt, (shared interrupts) and the state of the transfer is unknown. Re-issue transfer and go to 7. 9) Acknowledge the interrupt by clearing the Start bit in the BMx_COMMAND register. 10) Read the BMx_STATUS register determining if there was an error. a) If the Interrupt bit is clear and the Active bit is set, the controller is still processing the transfer b) If the Interrupt bit is set and the Active bit is clear, as far as the DMA is concerned, the transfer was a success. c) If the Interrupt bit is set and the Active bit is set, again, as far as the DMA is concerned, the transfer was a success. However, the DMA controller did not reach the last Descriptor Table entry. The ATA controller exhausted its transfer size.

7 Chapter 9 - PIO Verses DMA Transfers Page 9-12 d) If the Interrupt bit is clear and the Active bit is clear, there was an error. 11) Read the ATA_STATUS register, which clears the pending interrupt, and determine if there was an error. 12) Did the transfer succeed? Using the sequence described at the beginning of this chapter and used for PIO transfers, simply place the following code just before you send the ATA command to initialize the DMA. See later what this call actually does. dma_init_dma(ata, phy_address, buflen); Then just after you have sent the command and the device indicates it is ready for the transfer by setting the DRQ bit, start the controller. if (ata_wait(ata, ATA_STATUS_DRQ, wait)) dma_start_dma(ata, dir); else return WAS_AN_ERROR; Once you have received the interrupt and have checked the Bus Master s status bit to verify this interrupt belongs to this command, stop the DMA controller. dma_stop_dma(ata); Initializing the DMA Bus Master To initialize the DMA Bus Master, make sure it is not active, clear the status bits, and write a physical 4-byte aligned address of your Physical Region Descriptor Table to the BMx_ADDRESS register. Listing 9-6: Initializing the DMA Bus Master // create descriptor table bit32u *table = (bit32u *) SOME_DWORD_ALIGNED_ADDRESS; table[0] = address ; // address to store sector table[1] = 0x size; // EOT plus size of sector if (channel == ATA_CHANNEL_PRIMARY) { outportb(bus_master + BM0_COMMAND, 0); outportb(bus_master + BM0_STATUS, (1 << 2) (1 << 1)); outportl(bus_master + BM0_ADDRESS, table); } else { outportb(bus_master + BM1_COMMAND, 0); outportb(bus_master + BM1_STATUS, (1 << 2) (1 << 1)); outportl(bus_master + BM1_ADDRESS, table); }

8 Page 9-13 FYSOS: Media Storage Devices Unfortunately, initializing the DMA is a little bit more than just setting up a Physical Region Descriptor Table and pointing the BMx_ADDRESS register to it. Depending on the type of DMA used, either Mulitword or Ultra DMA, you have to set the timing registers in the PCI s Configuration Space for the specific device and transfer. Please see Appendix F in this book for more on this subject. Starting the DMA To start the DMA, simply set bit zero. Don t forget to set the direction at the same time using bit 3. Set it to read from the disk and write to the memory. Listing 9-7: Starting the DMA Controller if (channel == ATA_CHANNEL_PRIMARY) outportb(bus_master + BM0_COMMAND, (dir << 3) (1 << 0)); else outportb(bus_master + BM1_COMMAND, (dir << 3) (1 << 0)); Stopping the DMA Stopping the controller is a simple task of clearing bit 0 of the BMx_COMMAND register. However, we also read the BMx_STATUS register, saving its contents, then writing it back to clear any Write/Clear bits, then returning the original saved value. Listing 9-8: Stopping the DMA Controller if (channel == ATA_CHANNEL_PRIMARY) { inportb(bus_master + BM0_STATUS); status = inportb(bus_master + BM0_STATUS); outportb(bus_master + BM0_COMMAND, (0 << 0)); outportb(bus_master + BM0_STATUS, status); return status; } else { inportb(bus_master + BM1_STATUS); status = inportb(bus_master + BM1_STATUS); outportb(bus_master + BM1_COMMAND, (0 << 0)); outportb(bus_master + BM1_STATUS, status); return status; } The reason for the extra read of the status register is for a slight pause just after the interrupt is fired and just before we read the status to make sure the controller had time to set the corresponding bits.

9 Chapter 9 - PIO Verses DMA Transfers Page 9-14 Wrap up When using an ATA only controller, the ATA_READ_DMA command is used to read from the disk using DMA. No other indication is needed to tell the controller to use DMA as long as you have successfully set up the DMA. However, that command is not available for a Packet Interface (ATAPI) device. Therefore, you send the appropriate SCSI command, maybe READ(12), using the packet interface. To indicate to the controller that you will be using DMA, you must set bit 0 of the ATA_FEATURES register when sending the ATA_PACKET_COMMAND to the drive. Setting bit 0 tells the controller that the command you are sending in the following packet will use the DMA to make the transfer. If you have this bit clear, you will use PIO to make the transfer. You must also note that not all commands allow DMA transfers. For example, the two Identify Device commands only allow PIO transfers. See the respected ATAPI specification to see if a particular command allows DMA transfers. With this information, you should now be able to retrieve the Identify Block, send a Packet Interface command, and read or write sectors. The HDC_TYPE utility on the CD- ROM gives full source code to all described functions within this chapter.