Bus System. Bus Lines. Bus Systems. Chapter 8. Common connection between the CPU, the memory, and the peripheral devices.

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1 Bus System Chapter 8 CSc 314 T W Bennet Mississippi College 1 CSc 314 T W Bennet Mississippi College 3 Bus Systems Common connection between the CPU, the memory, and the peripheral devices. One device issues a request for information over the bus, and another device sends the information in response. Bus Lines Control Data/Address Control Data Address CSc 314 T W Bennet Mississippi College 2 CSc 314 T W Bennet Mississippi College 4

2 Bus Lines Output Through a Bus Control signals Several lines. Processor uses them to control communication. Other devices may make requests to the processor. Data/Address May be 8, 16 or some other width. May use shared data and address lines (cheaper) or separate (faster). CSc 314 T W Bennet Mississippi College 5 CSc 314 T W Bennet Mississippi College 7 Input Through a Bus Types of Busses Processor-Memory (Local Bus): Short, transfer at memory speed. Connect CPU, memory, and maybe a few fast devices. I/O Busses: Long, slow. SCSI, IDE Backplane Busses: Keep everyone happy. PCI Distinctions are not always clear. CSc 314 T W Bennet Mississippi College 6 CSc 314 T W Bennet Mississippi College 8

3 Bus Arrangements Synchronous Busses All connections to the bus share the same clock and clock periods. Each device knows what it may do during each period. Bus length is limited. Clock signals don t travel well over long wires. Faster than asynchronous. CSc 314 T W Bennet Mississippi College 9 CSc 314 T W Bennet Mississippi College 11 Synchronous/Asynchronous Busses Synchronous: Bus has a clock and devices are synchronized. Asynchronous: Bus had no clock and devices must handshake. Asynchronous Busses Each communicating device has own clock. s use special signals to keep track of each other and know what to do next. Works over longer distances. s may be added easily. Slower than synchronous. CSc 314 T W Bennet Mississippi College 10 CSc 314 T W Bennet Mississippi College 12

4 Handshaking Protocol Performance Parameters Data bus width. More wires mean more bits at a time. Separate data/address lines. Block transfers. CSc 314 T W Bennet Mississippi College 13 CSc 314 T W Bennet Mississippi College 15 State Machines for Handshaking The Bus Master The device which initiates transfers on the bus. Simplest: Only the CPU Faster: Multiple bus masters. If the CPU is the only bus master, it must be involved in every transfer. It is better to relieve the CPU of this work. CSc 314 T W Bennet Mississippi College 14 CSc 314 T W Bennet Mississippi College 16

5 Bus Arbitration Centralized Can t all talk at once. Who gets to be bus master? Daisy Chain. Requests go through each device in increasing priority. 1 2 n Centralized. All requests go through a centralized arbiter. Distributed by self-selection. Each device knows all pending requests and yields to the highest priority. Bus arbiter Grant Request Distributed by collision-detection. Try it; if it collided, try it again. Release CSc 314 T W Bennet Mississippi College 17 CSc 314 T W Bennet Mississippi College 19 Daisy Chain Commanding s The CPU writes data interpreted as command codes. The CPU reads status information. Memory-mapped: s are given addresses in real address space. Dedicated I/O instructions. CSc 314 T W Bennet Mississippi College 18 CSc 314 T W Bennet Mississippi College 20

6 User Programs Need Not Apply Only the O/S is allowed to communicate with devices. Memory-mapped device addresses are not part of user space. I/O instructions are not permitted in privileged mode. Polling v. Interrupts Polling: CPU repeatedly reads the status. Interrupts: The device informs the CPU when something happens. Polling is simpler, interrupts are more efficient. CSc 314 T W Bennet Mississippi College 21 CSc 314 T W Bennet Mississippi College 23 O/S Enforces Security Reading keyboards. File permissions. File system integrity. Data Transfer Processor can direct each transfer. A separate device can direct block transfers. Direct Memory Access (DMA). Network packets for other processes. User programs could bypass the O/S security systems and data structures if they could make direct access to devices. CSc 314 T W Bennet Mississippi College 22 CSc 314 T W Bennet Mississippi College 24

7 Direct Memory Access Mac I/O Bus or Backplane Bus CPU Memory DMA Controller Other Memory Bus CSc 314 T W Bennet Mississippi College 25 CSc 314 T W Bennet Mississippi College 27 Direct Memory Access CPU sends instructions to DMA. DMA controller moves a block of data from the other device to the memory. CPU does something else in the mean time. DMA controller interrupts CPU when done. CSc 314 T W Bennet Mississippi College 26

Buses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub.

Buses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub. es > 100 MB/sec Pentium 4 Processor L1 and L2 caches Some slides adapted from lecture by David Culler 3.2 GB/sec Display Memory Controller Hub RDRAM RDRAM Dual Ultra ATA/100 24 Mbit/sec Disks LAN I/O Controller