ECE 485/585 Microprocessor System Design

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1 Microprocessor System Design Lecture 3: Polling and Interrupts Programmed I/O and DMA Interrupts Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.

2 I/O Subsystems Things to Think About What instructions does the processor use to communicate with I/O devices? Direct (Isolated) I/O Memory Mapped I/O How do we know if an I/O device is ready or an I/O operation is complete Polling Interrupts How do we transfer data between the I/O device and memory? Programmed I/O (PIO) Direct memory access (DMA) Bus Mastering

3 I/O Completion or Ready Notification Two methods: Polled I/O Interrupt driven I/O Polled I/O: Peripheral make status (ex: busy/ready for new I/O request) available through an I/O port or memory mapped register CPU executes a busy-wait loop reading the status from the peripheral and looping until peripheral is ready to accept a new I/O request (and/or has completed the current I/O request) Interrupt driven I/O: Peripheral signals the CPU when it is ready for a new I/O request (and/or has completed the current I/O request) Program running on the CPU is interrupted and starts executing the code that handles the peripheral

4 Polling READB: IN AL, BUSY ; get BUSY flag TEST AL, BUSY_BIT ; test BUSY bit JNE READB ; still busy -- loop IN AL, DATAP ; read data Simplified Polling Code Fragment Microprocessor Address, Data, Control Memory I/O Device

5 Interrupt Driven I/O Permits the processor to execute useful instructions instead of polling an I/O device The I/O device interrupts the processor when it needs attention (e.g. has data) or an I/O operation has completed Keyboard character typed, mouse button clicked, etc. Requested disk block has actually been read (this takes eons in CPU cycle time) Timer tick expired Analog/Digital conversion complete new measurement available System wake-up (power saving architectures)

6 The Interrupt Mechanism Hardware Interrupts (Asynchronous) Non-Maskable Interrupt(s) (NMI) Priority Maskable Interrupt(s) (INTR) Software Interrupts (Synchronous) Nomenclature varies Intel calls these exceptions to distinguish them from H/W interrupts Often called traps or faults RISC architectures (ARM, MIPS, ) tend to name both hardware and software interrupts exceptions and handle them the same way

7 Interrupt Hardware: Vectors NMI INTR INTA# AD0-AD15 Non-maskable Interrupt Interrupt Interrupt Acknowledge Type vector Intel 8086

8 Interrupt Mechanism: Hardware Interrupts Occur under external control (asynchronous) Can occur any time during instruction/program execution but may only be recognized at instruction boundaries Non-Maskable Interrupts Ex: Power Failure Enough time to save state and shutdown gracefully Priority Maskable Interrupts I/O Devices Assigned Different Priorities Relative importance of servicing request (e.g. keyboard or disk) Ability of device to buffer data

9 Interrupt Mechanism: Software Interrupts Occur under CPU control (synchronous) Can occur when the CPU wants it to occur May be the result of instruction execution Divide-by-Zero Page fault or segmentation violation May be the result of instruction(s) inserted into the program that s running Debugging (breakpoints and single step) Operating System Calls User program makes O.S. request INT # instruction

10 x86 Interrupt Processing Sequence Interrupt occurs Push current processor state onto stack Flags (zero, carry, negative, ) CS:IP Clear IF and TF (Interrupt and Trap Flags) Prevents further interrupts Retrieve Instruction Pointer (CS:IP) Uses Interrupt Vector as index into Interrupt Descriptor Table (IDT) Begin executing with new CS:IP of ISR Service the interrupt (Interrupt Service Routine) ISR ends by executing IRET instruction (explicit) Pops CS:IP and Flags from Stack

11 x86 Interrupt Processing Sequence START: MOV AX, CX ; comment MOV CX, ICOUNT ; comment. Executing Code ISR: PUSH AX ; comment PUSH BX IN IRET Entry number, not address Interrupt Service Routine Interrupt Descriptor Table CS:IP (PC) of ISRs Interrupt occurs Push Flags and CS:IP (PC) Clear IF and TF (interrupt/trap flag) Stack CS:IP Flags IRET pops stack and execution resumes where interrupted IDT[Vector x 4] to get new CS:IP

12 Why multiply interrupt by 4?

13 I/O Subsystems Things to Think About What instructions does the processor use to communicate with I/O devices? Direct (Isolated) I/O Memory Mapped I/O How do we know if an I/O device is ready or an I/O operation is complete Polling Interrupts How do we transfer data between the I/O device and memory? Programmed I/O (PIO) Direct memory access (DMA) Bus Mastering

14 Data Transfer Two methods: Programmed I/O DMA (Direct Memory Access) Programmed I/O: All I/O operations go through the CPU Program running on CPU accesses device registers and moves data to/from peripheral and memory (and/or internal registers) DMA: CPU sets up DMA hardware, tells the DMA hardware to start and then goes merrily on its way DMA hardware accesses peripherals and moves the data to/from memory w/o CPU interaction DMA hardware generates an interrupt when the I/O transaction is complete

15 Programmed I/O Microprocessor Address, Data, Control Memory I/O Device CPU fetches/execute instructions to be executed to do the I/O CPU moves data from I/O device to processor and then to memory

16 Ex: Buffer transfer using Programmed I/O START: MOV BX, OFFSET BUFFER MOV DX, FFF8H ; set up I/O port MOV CX, COUNT ; set up byte count READB: IN AL, DX ; read byte MOV [BX], AL ; copy to buffer INC BX ; increment pointer LOOP READB ; decrement/test CX Simplified I/O Read Code Fragment Microprocessor Address, Data, Control Memory I/O Device

17 Direct Memory Access (DMA) Microprocessor Address, Data, Control Memory I/O Device DMA Controller

18 DMA (Detail) mp floats its bus interface pins AEN

19 Tying It All Together: Disk Read Example Operation: Read a block of 512 bytes from a floppy disk Communicate w/ the Floppy Disk Controller (FDC) Write Read Data command to FDC Tell the FDC to start Determine when operation is complete and/or has data ready Polling: Read the Status Register to find out when data is available and/or operation is complete Interrupt: Handle interrupt(s) from the FDC Transfer data from FDC to memory Programmed I/O: CPU reads each byte of data and writes the byte to memory DMA: DMA controller moves data from FDC to memory w/o involving the CPU

20 Next Time Lecture Topics: Memory Hierarchy Memory Taxonomy Register Files and SRAM Memory Organization Readings: Nothing new

An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal)

An Interrupt is either a Hardware generated CALL (externally derived from a hardware signal) OR A Software-generated CALL (internally derived from the execution of an instruction or by some other internal