FT28C512/ Volt Byte Alterable EEPROM

Transcription

1 5 Volt Byte Alterable EEPROM FEATURES Access time: 90ns Simple byte and page write Single 5V supply No external high voltages or V PP control circuits Self-timed No erase before write No complex programming algorithms No overerase problem Low power CMOS Active: 50mA Standby: 500µA Software data protection Protects data against system level inadvertent writes High speed page write capability Highly reliable Endurance: 100,000 write cycles Data retention: 100 years Early end of write detection DATA polling Toggle bit polling Two PLCC and LCC pinouts FT28C512 FT28C010 EPROM pin compatible FT28C513 Compatible with lower density EEPROMs DESCRIPTION The FT28C512/513 is a 64K x 8 EEPROM, fabricated with Force s proprietary, high performance, floating gate CMOS technology. The FT28C512/513 is a 5V only device. The FT28C512/513 features the JEDEC approved pin out for byte wide memories, compatible with industry standard EPROMS. The FT28C512/513 supports a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The FT28C512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the FT28C512/513 supports the software data protection option. BLOCK DIAGRAM A 7 A 15 X Buffers Latches and Decoder 512Kbit EEPROM Array A 0 A 6 Y Buffers Latches and Decoder I/O Buffers and Latches Control Logic and Timing I/O 0 I/O 7 Data Inputs/Outputs V CC V SS Rev A 1/

2 PIN CONFIGURATIONS TSOP A 15 A 12 A 7 A Plastic DIP RDIP FLAt Pack SOIC (R) V CC A 14 A 13 A 8 A11 A 9 A8 A13 A14 VCC A15 A12 A7 A 6 A5 A FT28C A10 I/O7 I/O6 I/O5 I/O4 I/O 3 VSS I/O2 I/O1 I/O0 A0 A 1 A2 A3 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 I/O 0 PLCC/LCC A 15 V CC I/O 1 A 12 I/O 2 V SS A A 13 A A FT28C A (Top View) A I/O I/O 3 I/O 4 I/O 5 I/O 6 A 5 A 4 A 3 A 2 A 1 A 0 I/O 0 I/O 1 I/O 2 V SS FT28C A 9 A 11 A 10 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 A 1 13 A 2 12 A 4 10 A 6 8 A 12 6 I/O 0 15 A 0 I/O 1 V SS A 3 11 A 5 9 A 7 7 A I/O PGA I/O 3 19 FT28C512 Bottom View V CC 36 1 I/O 5 21 I/O I/O 6 22 I/O 7 23 A A A A 9 28 A A A 6 A 5 A 4 A 3 A 2 A 1 A 0 I/O 0 I/O 1 A 7 I/O 2 A 12 V SS A 14 A 15 I/O 3 V CC I/O 4 I/O 5 A FT28C512 9 (Top View) A 8 A 9 A 11 A 10 I/O 7 I/O 6 PIN DESCRIPTIONS Addresses (A 0 A 15 ) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable () The Chip Enable input must be LOW to enable all read/ write operations. When is HIGH, power consumption is reduced. Output Enable () The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O 0 I/O 7 ) Data is written to or read from the FT28C512/513 through the I/O pins. Write Enable () The Write Enable input controls the writing of data to the FT28C512/513. PIN NAMES Symbol Description A 0 A 15 Address Inputs I/O 0 I/O 7 Data Input/Output Write Enable Chip Enable Output Enable V CC +5V V SS Ground No Connect Rev A 2/

3 DEVI OPERATION Read Read operations are initiated by both and LOW. The read operation is terminated by either or returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either or is HIGH. Write Write operations are initiated when both and are LOW and is HIGH. The FT28C512/513 supports both a and controlled write cycle. That is, the address is latched by the falling edge of either or, whichever occurs last. Similarly, the data is latched internally by the rising edge of either or, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the FT28C512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the FT28C512/513, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A 7 through A 15 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding. If a subsequent HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The FT28C512/513 provides the user two write operation status bits. These can be used to optimise a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment I/O DP TB DATA Polling (I/O 7 ) Reserved Toggle Bit DATA Polling The FT28C512/513 features DATA polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the FT28C512/513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O 7 will reflect true data. Toggle Bit (I/O 6 ) The FT28C512/513 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O 6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease, and the device will be accessible for additional read or write operations. Rev A 3/

4 DATA POLLING I/O 7 Figure 2a. DATA Polling Bus Sequence Last Write I/O 7 V IH HIGH Z V OH V OL FT28C512/513 Ready A 0 A 15 An A n A n A n A n A n A n Figure 2b. DATA Polling Software Flow Write Data DATA Polling can effectively halve the time for writing to the FT28C512/513. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine. Writes Complete? No Yes Save Last Data and Address Read Last Address IO 7 Compare? No Yes Ready Rev A 4/

5 THE TOGGLE BIT I/O 6 Figure 3a. Toggle Bit Bus Sequence Last Write I/O 6 * V OH HIGH Z V OL * * Beginning and ending state of I/O 6 will vary. FT28C512/513 Ready Figure 3b. Toggle Bit Software Flow Last Write Load Accum From Addr N Compare Accum with Addr N Compare Ok? Yes FT28C512 Ready The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple FT28C512/513 memories that is frequently updated. Toggle Bit Polling can also No provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for polling the Toggle Bit. HARDWARE DATA PROTECTION The FT28C512/513 provides three hardware features that protect nonvolatile data from inadvertent writes. Noise Protection A pulse typically less than 10ns will not initiate a write cycle. Default V CC Sense All write functions are inhibited when V CC is 3.6V. Write Inhibit Holding either LOW, HIGH, or HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently. SOFTWARE DATA PROTECTION The FT28C512/513 offers a software controlled data protection feature. The FT28C512/513 is shipped from Force with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once V CC was stable. Rev A 5/

6 The FT28C512/513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilising the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the FT28C512/ 513 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array. SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Software Data Protection Figure 4a. Timing Sequence Software Data Protect Enable Sequence followed by Byte or Page Write V CC 0V (V CC ) Data Addr AAA AAA A Writes ok t WC Write Protected t BLC MAX Byte or Page Note: All other timings and control pins are per page write timing requirements Rev A 6/

7 Figure 4b. Write Sequence for Software Data Protection Write Data AA to Address 5555 Write Data 55 to Address 2AAA Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the FT28C512/513 will automatically disable further writes, unless another command is issued to cancel it. If no further commands are issued the FT28C512/513 will be write protected during power-down and after any subsequent power-up. The state of A 15 while executing the algorithm is don t care. Note: Once initiated, the sequence of write operations should not be interrupted. Write Data 80 to Address 5555 Write Data XX to any Address Write Last Byte to Last Address Optional Byte/Page Load Operation After t WC Re-Enters Data Protected State Rev A 7/

8 Resetting Software Data Protection Figure 5a. Reset Software Data Protection Timing Sequence V CC Data Addr AAA AAA 80 AA AAA 5555 t WC Standard Operating Mode Note: All other timings and control pins are per page write timing requirements Figure 5b. Software Sequence to Deactivate Software Data Protection Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data A0 to Address 5555 Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data 20 to Address 5555 In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After t WC, the FT28C512/513 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. SYSTEM CONSIDERATIONS Because the FT28C512/513 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that be decoded from the address bus and be used as the primary device selection input. Both and would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is/are outputting data on the bus. Because the FT28C512/513 has two power modes, (standby and active), proper decoupling of the memory array is of prime concern. Enabling will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between V CC and V SS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. Rev A 8/

9 In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between V CC and V SS for each 8 devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Active Supply Current vs. Ambient Temperature I CC (ma) V CC = 5V I CC (RD) by Temperature Over Frequency I CC (ma) Frequency (MHz) 5.0 V CC 55 C +25 C +125 C Ambient Temperature ( C) Standby Supply Current vs. Ambient Temperature V CC = 5V 0.2 I SB (ma) Ambient Temperature ( C) Rev A 9/

10 ABSOLUTE MAXIMUM RATINGS Temperature under bias FT28C512/ C to +85 C FT28C512I/513I C to +135 C FT28C512M/513M C to +135 C Storage temperature C to +150 C Voltage on any pin with respect to V SS... 1V to +7V D.C. output current... 5mA Lead temperature (soldering, 10 seconds) C COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMEND OPERATING CONDITIONS Temperature Min. Max. Commercial 0 C +70 C Industrial 40 C +85 C Military 55 C +125 C Supply Voltage Limits FT28C512/513 5V ±10% D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Unit Test Conditions I CC V CC current (active) (TTL inputs) 50 ma = = V IL, = V IH, All I/O s = open, address inputs =.4V/2.4V f = 5MHz I SB1 V CC current (standby) (TTL inputs) 3 ma = V IH, = VIL, All I/O s = open, other inputs = V IH I SB2 V CC current (standby) (CMOS inputs) 500 µa = V CC 0.3V, = VIL, All I/O s = Open, Other Inputs = V IH I LI Input leakage current 10 µa V IN = V SS to V CC I LO Output leakage current 10 µa V OUT = V SS to V CC, = V IH V (1) ll Input LOW voltage V (1) V IH Input HIGH voltage 2 V CC + 1 V V OL Output LOW voltage 0.4 V I OL = 2.1mA V OH Output HIGH voltage 2.4 V I OH = 400µA Note: (1) V IL min. and V IH max. are for reference only and are not tested. POR-UP TIMING Symbol Parameter Max. Unit t (2) PUR Power-up to read operation 100 µs (2) t PUW Power-up to write operation 5 ms Rev A 10/

11 CAPACITAE T A = +25 C, F = 1MHZ, V CC = 5V Symbol Parameter Max. Unit Test Conditions (2) C I/O Input/output capacitance 10 pf V I/O = 0V (2) C IN Input capacitance 10 pf V IN = 0V ENDURAE AND DATA RETENTION Parameter Min. Max. Unit Endurance 10,000 Cycles per byte Endurance 100,000 Cycles per page Data retention 100 Years A.C. CONDITIONS OF TEST Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady MODE SELECTION Mode I/O Power L L H Read D OUT Active L H L Write D IN Active H X X Standby and write inhibit High Z Standby X L X Write inhibit X X H Write inhibit May change from LOW to HIGH May change from HIGH to LOW Don t Care: Changes Allowed N/A Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance EQUIVALENT A.C. LOAD CIRCUIT 5V 1.92KΩ Output 1.37KΩ 100pF Note: (2) This parameter is periodically sampled and not 100% tested. Rev A 11/

12 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits Symbol Read Cycle Parameter FT28C FT28C FT28C FT28C FT28C FT28C FT28C FT28C FT28C FT28C Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. t RC Read cycle time ns t Chip enable access time ns t AA Address access time ns t Output enable access time ns t LZ (3) LOW to active output ns t OLZ (3) LOW to active output ns t HZ (3) HIGH to high Z output ns (3) t OHZ HIGH to high Z output ns t OH Output hold from address change ns Unit t RC Address t t V IH t OLZ t OHZ t LZ t OH t HZ Data I/O HIGH Z Data Valid Data Valid t AA Note: (3) t LZ min., t HZ, t OLZ min., and t OHZ are periodically sampled and not 100% tested. t HZ max. and t OHZ max. are measured, with C L = 5pF from the point when or return HIGH (whichever occurs first) to the time when the outputs are no longer driven. Rev A 12/

13 WRITE CYCLE LIMITS Symbol Parameter Min. Max. Unit (4) t WC Write cycle time 10 ms t AS Address setup time 0 ns t AH Address hold time 50 ns t CS Write setup time 0 ns t CH Write hold time 0 ns t CW pulse width 100 ns t S HIGH setup time 10 ns t H HIGH hold time 10 ns t WP pulse width 100 ns t WPH High recovery 100 ns t DV Data valid 1 µs t DS Data setup 50 ns t DH Data hold 0 ns t DW Delay to next write 10 µs t BLC Byte load cycle µs Controlled Write Cycle Address t WC t AS t AH t CS t CH t S t H t WP t DV Data In Data Valid Data Out t DS HIGH Z t DH Note: (4) t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete the internal write operation. Rev A 13/

14 Controlled Write Cycle t WC Address t AS t AH t CW t S t WPH t H t CS t CH t DV Data In Data Valid t DS t DH Data Out HIGH Z Page Write Cycle (5) t WP t BLC t WPH Address* (6) I/O Last Byte Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2 t WC *For each successive write within the page write operation, A 7 A 15 should be the same or writes to an unknown address could occur. Notes: (5) Between successive byte writes within a page write operation, can be strobed LOW: e.g. this can be done with and HIGH to fetch data from another memory device within the system for the next write; or with HIGH and LOW effectively performing a polling operation. (6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the or controlled write cycle timing. Rev A 14/

15 DATA Polling Timing Diagram (7) Address A n A n A n t H t S t DW I/O 7 D IN = X D OUT = X D OUT = X t WC Toggle Bit Timing Diagram t H t S I/O 6 HIGH Z * * t DW t WC *Starting and ending state will vary, depending upon actual t WC. Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings. Rev A 15/

16 PACKAGING INFORMATION 32-Lead Hermetic Dual In-Line Package Type D (42.95) Max (15.49) (12.70) Pin (0.13) Min (2.54) Max. Seating Plane (5.90) Max (3.81) Min (1.52) (0.38) (5.08) (3.18) (2.79) (2.29) Typ (2.54) (1.65) (0.84) Typ (1.40) (0.58) (0.36) Typ (0.46) (15.75) (14.99) Typ (15.60) (0.38) (0.20) 0 15 NOTE: ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) Rev A 16/

17 PACKAGING INFORMATION 32-Pad Ceramic Leadless Chip Carrier Package Type E (7.62) BSC (0.38) (0.08) (3.81) BSC (0.51) x 45 Ref. Pin (2.41) (1.91) (0.56) DIA (0.15) (5.08) BSC (0.38) Min (1.39) (1.14) TYP. (4) PLCS (0.71) (0.56) (32) Plcs (1.27) BSC (1.02) x 45 Ref. Typ. (3) Plcs (11.63) (11.22) (11.63) (3.05) (1.52) (2.24) (1.27) (14.22) (13.71) (14.17) (10.16) BSC Pin 1 Index Corner NOTE: 1. ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERAE: ±1% NLT ±0.005 (0.127) Rev A 17/

18 PACKAGING INFORMATION 32-Lead Ceramic Flat Pack Type F (31.19) (25.40) Pin 1 Index (0.48) (0.38) (1.27) BSC (21.08) Max (1.14) Max (0.13) Min (0.18) (0.10) (10.93) (3.05) (2.29) (9.40) (6.86) (0.76) Min (8.82) (8.38) (1.14) (0.66) NOTE: ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) Rev A 18/

19 PACKAGING INFORMATION 32-Lead Plastic Leaded Chip Carrier Package Type J (10.67) 0.050" Typical 0.030" Typical 32 Places (1.27) Typ " Typical 0.400" 0.050" Typical (1.14) x (12.57) (12.32) Typ (12.45) (11.51) (11.35) Typ (11.43) (7.62) Ref (0.53) (0.33) Typ (0.43) FOOTPRINT 0.300" Ref " Seating Plane ±0.004 Lead CO Planarity (0.38) (2.41) (1.52) (3.56) (2.45) Typ (3.45) (1.22) (1.07) Pin (15.11) (14.86) Typ (14.99) (14.05) (13.89) Typ (13.97) (10.16) Ref. 3 Typ. NOTES: 1. ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERAE FOR REFEREE ONLY Rev A 19/

20 PACKAGING INFORMATION 32-Lead Plastic Dual In-Line Package Type P (42.29) (41.76) (14.15) (12.95) Pin 1 Index Pin (38.10) Ref (2.16) (1.02) Seating Plane (4.06) (3.17) (4.06) (3.56) (0.76) (0.38) (2.79) (2.29) (17.78) (7.62) (0.56) (0.36) (15.88) (14.99) Typ (0.25) 0 15 NOTES: 1. ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH Rev A 20/

21 PACKAGING INFORMATION 32-Lead Ceramic Small Outline Gull Wing Package Type R Nom ±0.007 See Detail A For Lead Information Typ Min R Typ Typ. Detail A R Typ Min " Typical Max ± " Typical 0.050" Typical FOOTPRINT 0.030" Typical 32 Places Max Nom. NOTES: 1. ALL DIMENSIONS IN IHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN IHES Rev A 21/

22 PACKAGING INFORMATION 36-Lead Ceramic Pin Grid Array Package Type K A (0.20) A (1.27) NOTE: Leads 5, 14, 23, & 32 Typ (.010) (4.57 ±.25) 4 Corners Typ (2.54) All Leads Pin 1 Index Typ (.010) (4.57 ±.25) 4 Corners (3.05) (2.54) (1.83) (1.57) (19.56) (19.05) SQ A (0.51) (0.41) A (4.70) (4.45) NOTE: ALL DIMENSIONS IN IHES (IN PARENTHESES IN MILLIMETERS) Rev A 22/

23 PACKAGING INFORMATION 40-Lead Thin Small Outline Package (TSOP) Type T (12.522) (12.268) (1.143) (0.038) (0.889) Pin #1 Ident O (1.016) (0.127) Dp O (0.762) X0.003 (0.076) Dp (1.219) (0.500) (10.058) (9.957) (0.178) 15 Typ. Seating Plane A (14.148) (13.894) (0.065) Seating Plane (0.254) (0.152) (1.016) Detail A (0.813) Typ (0.152) Typ. 4 Typ (0.432) (0.432) (0.508) Typ ± 0.05 (0.583 ± 0.002) Solder Pads 0.30 ± 0.05 (0.012 ± 0.002) Typical 40 Places 15 Eq. Spc.@ 0.50 ± = 9.50 ± 0.06 (0.374 ± ) Overall Tol. Non-Cumulative FOOTPRINT 0.17 (0.007) 0.03 (0.001) 1.30 ± 0.05 (0.051 ± 0.002) 0.50 ± 0.04 ( ± ) NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (IHES IN PARENTHESES). Rev A 23/

24 Ordering Information Device FT28C512 X X XX Access Time 90 = 90ns 12 = 120ns 15 = 150ns 20 = 200ns 25 = 250ns Temperature Range Blank = Commercial = 0 C to +70 C I = Industrial = 40 C to +85 C M = Military = 55 C to +125 C MB = Mil-STD-883 M5004 Device FT28C513 X X XX Access Time 90 = 90ns 12 = 120ns 15 = 150ns 20 = 200ns 25 = 250ns Package D = 32-Lead CerDip E = 32-Pad LCC F = 32-Lead Flat Pack J = 32-Lead PLCC K = 36-Lead Pin Grid Array P = 32-Lead Plastic Dip R = 32-Lead Ceramic SOIC T = 40-Lead TSOP Temperature Range Blank = Commercial = 0 C to +70 C I = Industrial = 40 C to +85 C M = Military = 55 C to +125 C MB = Mil-STD-883 M5004 Package E = 32-Pad LCC J = 32-Lead PLCC Rev A 24/

25 Ashley Crt, Henley, Marlborough, Wilts, SN8 3RH UK Tel: +44(0) Fax:+44(0) Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. Life Support Applications Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products for use in such applications do so at their own risk and agree to fully indemnify Force Tecnologies for any damages resulting from such improper use or sale. All trademarks acknowledged Copyright Force Technologies Ltd 2011 Rev A 25/