ic-nq EVAL NQ1D EVALUATION BOARD DESCRIPTION

Transcription

1 Rev B4, Page 1/6 ORDERING INFORMATION Type Order Designation Description/Options ic-nq Demo EVAL NQ1D ic-nq Evaluation Board with BiSS PC Adapter ready-to-operate, incl. adapter MB3A equipped with ic-mb3 BiSS Master and PC interface cable for PC parallel printer port ic-nq Software NQ1D Evaluation Board Software PC program to configure ic-nq and the configuration EEPROM; download at BiSS to PC-LPT Adapter BiSS to PC-USB Adapter MB3A MB3U BiSS Master Adapter with ic-mb3 for PC parallel printer port, supplied without interface cable (replaces adapter IC103) BiSS Master Adapter with ic-mb3 for PC USB port BiSS Master Board EVAL MB3D-S ic-mb3 Evaluation Board (serial SPI link to PC) ready-to-operate master for 3 sensors, incl. PC/µC cable; to be operated via NQ1D or BiSS software EVAL MB3D-P ic-mb3 Evaluation Board (parallel link to µc) BiSS Master Board ic-sy1 EVAL SY1D BiSS Master FPGA Board (MB1D) ready-to-operate master for 8 sensors, isolated sensor supply and sensor line signals, incl. PC interface cable BiSS Software BiSS Master Software universal PC program to configure master boards and sensors; download at BOARD NQ1D TERMINAL DESCRIPTION (size 100 mm x 80 mm) Name Function VDD VB GND GNDA +5 V Supply Voltage (ca. 10 to 25 ma, with MB3A ca. 130 ma) +8 V Supply Voltage (series regulator mounted) Supply Ground Reference Ground Fig. 1: Evaluation board NQ1D, component side BiSS Plug Configuration No. Name Function 1 VB Positive Supply Voltage (+8V..) 2 MA % Master Clock Signal P 3 MA! Master Clock Signal N 4 VDD Positive Supply Voltage (+5V) 5 SHIELD Cable Shield 6 GND Ground (0V) 7 SL % Slave Data Signal P 8 SL! Slave Data Signal N 9 NC Not connected Copyright 2005, ic-haus

2 Rev B4, Page 2/6 DESCRIPTION Hardware All pins on ic-nq are lead out as terminals. Supply voltages VDDA (analog) and VDD (digital) as well as GNDA and GND are linked but can be separated if needed by removing jumpers J6 and J7. A 5 V series regulator can be assembled as an option for external voltage supply via pin VB. 8-pole sockets are provided for the input wiring of SIN, COS and ZERO. Individual components or a complete second board connecting sensors can be clipped onto these. An RS422 driver (type 75179) can be used for data transmission via BiSS with an RL/CL line termination. The interface cable is connected to the sub-d 9 pin. Resistors RSCL and RSDA are not required if the EEPROM is to be accessed solely via ic-nq. Fig. 2: Circuit diagram of evaluation board NQ1D (with possible additional components). Assembly Options R1 to R6, C1 to C4: to be mounted depending on the configuration X1: 78L05 or, alternatively, X2: 7805 with C9, C10, D1. U3: RS422 driver with a pinout (substitutes bridged socket pins 3-5 and 2-8) RL, CL: line termination J5: bridge for line shield to board ground

3 Rev B4, Page 3/6 Software Control software nq_xx.exe with its parameter file default.hex runs on a PC under Windows. A driver for the parallel interface is also required and assembled. The self-extracting file port95nt.exe installs all the necessary files. BIOS Setup Bi-Directional or EPP (eg. under Win NT) must be selected in the BIOS for the bidirectional operation of the parallel interface. Setting the BIOS to Normal alone is not sufficient. Typical DMA settings are: ECP DMA select 3, on-board parallel interface address 378h with interrupt Q7. Software Description Fig. 3: Screen display. Menu Section Menu Button Description <File> Load File Chip configuration I/O, Intel hex file format (*.hex) Save File Intel format, suits most EEPROM programmers Save BiSS Master Config Stores the ic-mb3 master chip configuration as *.cfg <Mode> Mode must be set in accordance to the adapter in use. No Hardware See Note 1. BiSS-Master / Intel-Mode Eval Board MB3D-P, BiSS Master FPGA Board SY1D BiSS-Master / Motorola-Mode MB3D-P (jumper S2 altered), SY1D (jumper J3 altered) BiSS-Master / SPI-Mode BiSS PC-LPT Adapter MB3A, Eval Board MB3D-S BiSS-Master Emulation PC-LPT Adapter IC103 (BiSS protocol emulation from PC) <Extra> Enable R/O Window Selects for a separate position data output window Set OscFreq Permits entries for ic-nq s Elec. Char. item no. A01 (applied to calculate Max FIN and Min EDGEDIST) Config SSI Mode See ic-nq data sheet for parameters SELSSI, CFGSSI(1:0) Middle Section - Output - Button Description Read Output Start/stop of data transfers (Slave -> BiSS Master -> PC) Initialize BiSS device initialization (output of a single clock pulse) Config BiSS Slave ID Use 0" when only one ic-nq is connected. By a higher slave ID a r/w access to registers of further ic-nq s connected in chain is possible (BiSS network). AutoGetSens Releases the BiSS Master to cyclically repeat sensor mode data transfers (Slave -> BiSS Master) Enable internal clock Use of internal RC clock or ext. clock oscillator (BiSS Master) FrequSens Sensor mode clock frequency FrequReg Register mode clock frequency AutoGetSens Cycle Time Interval time for sensor mode cycles

4 Rev B4, Page 4/6 Lower Section - Configuration - Button <Name of ic-nq parameter> FCTR Description Please refer to the ic-nq data sheet. Parameter selecting the maximum tracking rate (default 0004h). Please refer to the ic-nq data sheet for permissible entries. A selection for MaxFIN or Min EDGEDIST automatically displays and transmits a corresponding entry for the FCTR register. MaxFIN Min EDGEDIST Identifier AMPL Selection list entries are calculated from the current SELRES, FCTR and MIN OSCFREQ settings (see menu extra). A selection for MaxFIN automatically displays and transmits a corresponding entry for the FCTR register. Selection list entries are calculated from current SELRES, FCTR and MAX OSCFREQ settings (see menu extra). A selection for Min EDGEDIST automatically displays and transmits a corresponding entry for the FCTR register. BiSS device manufacturer ID and product code. Can be edited and stored to the configuration EEPROM (Write E 2 prom). Thresholds for monitoring the sensor signal. Selections are stored under SELAMPL and AMPL. Amendments to individual parameters are transferred immediately to ic-nq s registers (RAM). Bottom Line Buttons Read Param Write Param Load File Save File Write E 2 prom Reads in ic-nq s current configuration (ic-nq RAM -> PC) Transfers the setup displayed on screen to ic-nq (PC -> RAM) Reads in a configuration file (*.hex) Stores the displayed configuration to file (*.hex) Writes the setup displayed on the screen to the EEPROM connected to ic-nq. It also transfers the CRC value calculated by the software to the EEPROM. Note 1: In No Hardware mode settings for all parameters under Configuration can be made and saved with the Save File button as an Intel.hex file. Using an external programming device it is then possible to create a configuration EEPROM.

5 Rev B4, Page 5/6 Operation with BiSS PC Adapter IC103 BiSS PC adapter IC103 is provided for communication via BiSS without a master IC. Using this adapter ic-nq's control program can emulate BiSS line signals via the parallel interface. Required assembly for NQ1D: jumper J4, connection of pins 2 with 8 and 3 with 5 at socket U3 or line driver U , no linear regulators X1/X2. The adapter is powered via jumper J4 from board NQ1D which itself should be powered by V connected to ground at VDD (the current draw is ca. 25 ma with the adapter). BiSS Master Emulation should be selected as the mode of operation here; the necessary master and slave parameters are preset. BiSS emulation is slow with long timeouts; the EEPROM is suitably preconfigured to this end (default delivery status). As the BiSS protocol is controlled via timeout parameters and data in register mode is transmitted using PWM, each interrupt can result in a faulty data transmission on a multitasking operating system. It is thus recommended that no other programs be run simultaneously. Fig. 4: Adapter IC103 Operation with BiSS PC adapter MB3A The ic-nq control program supports the use of BiSS PC adapter MB3A which is either clipped directly onto the board NQ1D or connected by leads. Board NQ1D powers the adapter and must be supplied with +5 V at VDD versus GND. Required assembly for NQ1D: jumper J4, line driver U , linear regulators X1/X2 optional. Adapter MB3A operates with BiSS master ic-mb3, activated by the control program via an SPI link. The mode of operation should thus be set to BiSS Master SPI Mode. Various timeout parameters are possible, as are sensor data transmissions at a rate of up to 10 Mbit/s. Operation with BiSS Master Board MB3D-S The ic-nq control program supports the use of BiSS master board MB3D-S which is either clipped directly onto the board NQ1D or connected by leads. Here, the master powers the sensors, with board MB3D now supplying board NQ1D with power. To this end, master board MB3D must be supplied with +8 V at VB versus GND. Fig. 5: Adapter MB3A Required assembly for NQ1D: jumper J4, line driver U , no linear regulators X1/X2. Board MB3D-S operates with BiSS master ic-mb3, activated by the control program via an SPI link. The mode of operation should thus be set to BiSS Master SPI Mode. Various timeout parameters are possible, as are sensor data transmissions at a rate of up to 10 Mbit/s. Fig. 6: BiSS master MB3D-S

6 Rev B4, Page 6/6 Operation with BiSS Master FPGA Board SY1D (MB1D) The ic-nq control program supports the use of BiSS master FPGA board SY1D which is either clipped directly onto the board NQ1D (after removing the connecting nuts on one side) or connected by leads. Here, the master powers the sensors, with board SY1D now supplying board NQ1D with power. To this end, master FPGA board SY1D must be supplied with +8 V at VB versus GND. Required assembly for NQ1D: jumper J4, line driver U , no linear regulators X1/X2. Jumper J3 on SY1D selects either BiSS Master Intel Mode or BiSS Master Motorola Mode (default delivery status); the operating mode of the software should be set accordingly. Various timeout parameters are possible, as are sensor data transmissions at a rate of up to 10 Mbit/s. Fig. 7: BiSS master SY1D Communication Failures For adapter IC103: If error message "Error TimeOut: NO SL ACK" is generated on "Initialize", the BiSS signals on line MA on NQ1D should be checked. If no reaction to "Initialize" is forthcoming here, it is then necessary to check the configuration of the PC parallel interface. This specification is for a newly developed product. ic-haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact ic-haus to ascertain the current data. Copying - even as an excerpt - is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.