SPECIAL SPECIFICATION 1859 Programmable Logic Controller

Transcription

1 1993 Specifications CSJ s , etc. & SPECIAL SPECIFICATION 1859 Programmable Logic Controller 1. Description. This Item shall govern for the furnishing and installation of a programmable logic controller (PLC) unit in field locations as shown on the plans and detailed in these Special Specifications. 2. Materials. (1) General Requirements. All materials furnished, assembled, fabricated or installed under this Item shall be new, corrosion resistant and in strict accordance with the details shown in the plans and in the specifications. The programmable logic controller receives discrete and analog inputs, and control discrete and analog outputs in a manner dictated by the user specified logic called Relay Ladder Logic. A programmable controller can also perform data handling operations and communicate with external devices. All products shall be designed, manufactured, and tested in accordance with recognized UL, FM, and IEC industrial standards. The system shall be operational during and after testing. (a) Physical Characteristics. The unit shall consist of rugged components designed specifically for industrial environments. A complete system shall consist of one or more racks containing I/O modules, function modules, and communication processors interconnected by signal cables. All components shall be housed in structurally secure enclosures. The controller CPU shall be modular mounted on a DIN rail. The modular type shall be fully enclosed within a durable plastic shroud. The I/O system shall be modular. Each module shall be fully enclosed within a durable plastic shroud. When mounted on the system base, each I/O module shall not occupy more than one slot. There shall be room for up to 8 I/O, Function Modules or Communication Processor modules (excluding the CPU, Interface Module and Power Supply). I/O modules shall be retained in their slot by a hinge on the upper rear edge and a screw on the lower rear edge of the DIN rail. I/O modules shall be installed in any available slot in the CPU or expansion rack

2 I/O modules shall connect electrically to the adjacent module via a backplane bus connector. I/O modules shall be fully enclosed in a plastic covering protecting the electronic circuitry from exposure. (b) Durability. All components shall be manufactured with a high degree of durability. All switches and other operator-controlled devices shall be of the size and durability for the intended use as is normally offered for industrial applications. All signal cables furnished by the manufacturer shall be constructed so as to withstand, without damage, all normal use and handling. (c) Parts Interchange. The controller shall have a high degree of interchange capability. The power supply, battery, power connector and EPROM memory cartridges should all operate equally well regardless of the CPU being used. The system shall incorporate a modular design using plug-in connectors for backplane connectivity. Wherever possible, all assemblies and sub-assemblies performing similar functions shall be interchangeable. The system design shall accommodate the replacement of assemblies without having to disconnect field wiring. Removable connectors shall be used to connect field wiring to the individual I/O module assemblies. All major assemblies and sub-assemblies, modules, and devices shall be identified using permanent labels or markings each of which indicates the manufacturer s catalog number, product manufacturing date code, FM, UL and IEC certifications. (2) Functional Requirements. The programmable logic controller shall include the following functional requirements: (a) Central Processing Unit (CPU). CPU - CPU shall possess the capability to solve application logic, store the application program, store numerical values related to the application processes and logic, and interface to the I/O systems. The CPU shall need no additional modules to provide at least the following advanced programming features: PID, Integer / Floating-point Math, Logic functions, Comparisons, Data Blocks, and user-defined functions. Modular CPU - The modular type CPU shall contain: A memory mounted on the board, for performing Boolean operations, and interface to an RS-485 programming network. Additionally, CPU shall contain a built-in PROFIBUS DP interface. The modular type CPU shall contain a real-time calendar and clock that can be accessed by the user program. This Time of Day clock and calendar shall be

3 battery-backed and maintain seven time functions: Year (2 digits), Month, Day of Month, Hour, Minute, Second, and Day of week. The modular CPU shall execute Boolean functions at a rate of 0.3 to 0.6 microseconds per instruction or lower. The modular CPU shall be capable of controlling up to 32 I/O slots in an expanded configuration depending upon the CPU being utilized. The modular CPU shall be able to provide additional serial ports via a modular communication processor. (b) System Diagnostics. VISUAL DIAGNOSTICS - Status of low or dead battery shall be indicated by a red Battery LED on the CPU module. The CPU will also notify the user in the event of a System Fault, and the mode of the processor (Run / Stop). The diagnostic status of the fuses, for those discrete I/O modules containing fuses, shall be indicated by a red LED mounted on the top of the module. The red LED shall illuminate when a blown fuse condition is present. ALARM FEATURES - The alarm processor shall report three types of fault action; fatal, diagnostic, or informational, and the CPU shall respond as follows: FAULT ACTION FATAL DIAGNOSTIC INFORMATIVE CPU Enters STOP Mode YES YES YES Set Diagnostic Bit YES YES NO Logged In Fault Table YES YES YES When an I/O fault occurs, the alarm processor shall report the rack and slot location of the fault, the condition, the I/O address and the program logic address that caused the fault, if appropriate. (c) System Security. OEM PROGRAM PROTECTION - The PLC will have the ability to store the userprogram in a non-volatile EPROM memory cartridge. This feature allows users to protect the resident logic program from unauthorized changes. (d) CPU Memory. MEMORY CAPACITY - The PLC shall supply a modular design CPU that contains at least the following: 48 Kbytes for application programming Either 2048 (2K) or 9, bit registers for register and data usage global reference flags or control relays bits for discrete inputs

4 bits for discrete outputs bit registers for analog inputs bit registers for analog outputs Additionally the PLC shall offer up to 4 MB of memory on FEPROM as an option MEMORY STORAGE - The register values and the application program shall be stored in battery backed, CMOS static RAM memory. The application program and system configuration shall also be stored in FLASH, EEPROM, EPROM memory if so desired. There shall be a long-life Lithium battery used to maintain the contents of the CMOS RAM memory in the CPU. There shall be an easily accessible battery compartment in the CPU. The battery shall be replaceable with power applied to the PLC and without having to remove the CPU. An LED shall provide visual indication of the battery condition. Additionally, a low battery condition shall be alarmed with a system diagnostic bit. CPUs shall allow resident user program to be maintained in the CPU without power applied. Two levels of maintainability shall be provided, short duration and long duration. For short duration, the program shall be maintained by a hi-capacity capacitor for a period of no less than 1 hour. This allows adequate time for replacing the battery in the central processing unit, should the external supply to the CPU be interrupted. For long duration, the CPU module shall maintain its contents by using the battery. This allows the CPU module to be shipped via surface mail where power supply to the module is not available. This method may be achieved by providing internally mounted battery. (e) Programming Environment. PROGRAMMING DEVICES - On-line and off-line, CPU and I/O configuration and application program development shall be achieved with a PC compatible computer and programming and documentation software. The IBM compatible computer shall be connectable to the PLC via a built-in communication port on the CPU. The serial communication port shall provide RS- 422 signals with RS-485 compatibility at a speed of 300 Baud to 12 Mbaud (configurable). In addition to the MPI (Multi-Point Interface) communications, the PC compatible computer shall be connectable to the PLC via PROFIBUS DP or Ethernet TCP/IP protocol. A separate module providing Ethernet communications connection shall plug into any system

5 The programming devices shall have access to the application program, the CPU and I/O system configurations, all registers, CPU and I/O status, system diagnostic relays, and I/O override capabilities WINDOWS 95 / 98 / NT COMPATIBLE SOFTWARE - The WINDOWS compatible software shall provide the capability of reading, writing, and verifying the configuration and program with a diskette backup. The software shall execute only in a WINDOWS operating system. The software shall provide on-screen help information throughout its execution paths. It shall have the capability of programming the user program, store the program to the PLC, monitor program and reference address status while the PLC is in Run or Stop mode. The software must be capable of generating a printout of the relay ladder program for documentation purposes. The user shall be able to select any of the program documentation below: Types of Documentation Description Print Program This printout shall print the program logic with or without the equivalent Boolean instructions for each rung, the reference list, reference descriptions and/or users rung comments. Cross reference tables This printout shall show the use of references in the program. Reference tables This printout shall show the values of each reference in each selected table and allow the user to double-click on any reference to display the code where the reference is utilized. Configuration Printout This printout shall allow the user to generate a rack hardware and its assigned reference addresses listing, and the CPU configuration listing. The software shall provide the capability for programming using user-defined variables (Symbolic Names). These Symbolic Names will consist of 24 characters with an optional 80 character descriptor. OPERATOR INTERFACE - The programming port and its protocol shall be open in architecture. The protocols of this communication port shall be published such that a user may develop his own operator interface device, software or hardware, to access Register, I/O status, I/O override and system diagnostic memory data. Through an open nature of this communications protocol, a wide variety of operator interface shall be made available. These may be manufacturer s own brand or they may be manufactured by 3 rd party vendors

6 (f) Instruction Set. PROGRAMMING LANGUAGE - The CPU shall be capable of solving an application program whose source format shall conform to the IEC guidelines. The basic languages supported are: relay ladder logic, block diagram or statement list. The language shall support relay, timers and counters, arithmetic, relational, bit operation, data move, conversion, and control functions. The CPU shall be capable of solving an application program whose main program format is in Relay Ladder Logic, Statement List (Structured Text) or Function Block Diagram with underlying code in statement list. The CPU will also be capable of supporting other IEC languages such as Structured Control Language (SCL) or Sequential Flowchart (GRAPH 7) programming. RELAY FUNCTIONS - Relay ladder operations shall consist of the following contacts and coils: RELAY FUNCTIONS Normally Open Contact Normally Closed Contact Negation Contact Output Coil Negated Output Coil Midline Output Coil Set Coil (Latch) Reset Coil (Unlatch) Retentive Set/Reset Coil Retentive Reset/Set Coil Negative Edge Detection Positive Edge Detection Positive Edge Detection and Negative Edge Detection shall function as leading and trailing edge one-shot coils respectively. Contacts may be referenced any number of times within the application program. A single rung may contain multiple coils. TIMERS AND COUNTERS - Timer and counter operations shall consist of the following types: TIMERS AND COUNTER FUNCTIONS Pulse Timer (S_PULSE) Extended Pulse Timer (S_PEXT) On-Delay Timer (S_ODT) Retentive On-Delay Timer (S_ODTS) Off-Delay Timer (S_OFFDT) Up Counter (S_CU)

7 Down Counter (S_CD) Up / Down Counter (S_CUD) The retentive on-delay timer shall behave as a stop-watch that increments time when enabled and holds the current timed value until receiving power flow to the reset input. The simple on-delay timer shall increment while it receives power flow and reset to zero when power flow stops. The simple off-delay timer shall increment while it power flow stops and reset to zero when power flow is present. There shall be at least 682 programmed timers and/or counters available for use in application programs. Each timer or counter requires the use of three 16-bit registers within %R memory for storage of the preset, the current value and a control word. These three registers shall be accessible to the user via a register reference. The timers and counters shall not require an output reference, the output of a timer or counter can be used to energize a coil, or enable another function, such as a math function, or another timer or counter. The time/count limit shall be either a programmed constant or shall be programmable via a register reference value. The time shall be counted in tenths of seconds or hundredths of seconds, and the range for the timers and counters is 0 to 32,767 time units. MATH - The CPU will support both integer and floating-point math and shall support three data types, Signed Integer (INT), Double Precision Integer (DINT) and Floating Point (REAL). Arithmetic functions shall consist of the following types: ARITHMETIC FUNCTIONS Addition Subtraction Multiplication Division Modulo Division *Square *Square Root *Natural Logrithm *Exponentiation *Sine *Cosine *Tangent *Arctangent *Arcsine

8 *Arccosine * Real Data types only Signed Integers (INT) data shall be stored in 16 contiguous bits of memory, in 2 s complement notation. The range for Signed Integer Data shall be -32,768 to +32,767. Double Precision Integer (DINT) data shall be stored in 32 contiguous bits of memory, double precision data is always signed. The range for Double Precision Integer Data shall be -2,147,483,648 to 2,147,483,647. Floating Point (REAL) data shall be stored in IEEE format and shall be stored in 32 contiguous bits of memory. The range for Real Data shall be (positive) e-38 to e+38 (negative) e-38 to e+38. The arithmetic function blocks shall consist of multiple inputs and outputs. The enable input shall begin the execution. All of the Arithmetic functions shall be such that they can be cascaded together in a single rung. RELATIONAL FUNCTIONS - Relation Functions which are used to compare two numbers, shall operate on Signed Integer, Double Precision Integer and Real data types, and shall consist of the following types: RELATIONAL FUNCTIONS Equal To Not Equal To Greater Than Greater Than or Equal to Less Than Less Than or Equal to BIT OPERATION FUNCTIONS - Bit Operation Functions shall perform comparison and movement operations on word data that is specified as a continuous string of data in 16-bit or 32-bit increments. Bit Operation Functions that are used to perform Boolean operations on corresponding bits of two bit strings of the same length shall consist of the following types: BOOLEAN FUNCTIONS Logical AND Logical OR Logical Exclusive OR Bit Operation Functions used to create an output string that is a copy of an input bit string, but with its bits inverted, shifted, or rotated. These functions shall operate on 16-bit or 32-bit data types and shall consist of the following types:

9 BIT FUNCTIONS Logical Invert (NOT) Shift Left Shift Right Rotate Left Rotate Right The shift functions shall allow for the user to specify the number of places that the array is to be shifted as an input, and provide the state of the last bit shifted out, and a copy of the shift register as outputs. DATA MOVE FUNCTIONS - Basic data movement capabilities shall be provided by the following list of functions: DATA MOVE FUNCTIONS Move Shift Register The movement of data (8 / 16 / 32 bit values), as individual bits, from one location to another shall be accomplished by the Move function. The Shift Register function shall provide the functionality to shift one or more data bits within a reference location. All of the data within the Shift Register shall be accessible throughout the program from logic addressed memory. CONVERSION FUNCTIONS - Multiple conversion functions shall be provided to convert a data item from one format to another. These functions are listed below. CONVERSION FUNCTIONS BCD to Integer Integer to BCD Integer to Double Integer BCD to Double Integer Double Integer to BCD Double Integer to Real Invert Integer Invert Double Integer Negate Integer Negate Double Integer Negate Real Round Truncate Ceiling Floor CONTROL FUNCTIONS - Control functions shall be provided to limit program execution, alter the way the CPU executes the application program, or provide special PLC services. The following Control Functions shall be provided:

10 CONTROL FUNCTIONS CALL / RET Master Control Relay Activate (MCR>) Master Control Relay Deactivate (MCR<) Master Control Relay On (MCRA) Master Control Relay Off (MCRD) A master control relay function shall allow all rungs between the MCR and its subsequent end function to be executed without power flow. PID FUNCTION - A single PID function block instruction must be provided by the CPU without any additional modules. Two versions of this closed loop control algorithm (Proportional/Integral/Derivative) shall be available: The standard ISA PID algorithm, which applies the proportional gain to each of the proportional, derivative, and integral terms; and The independent algorithm that applies the proportional gain only to the proportional gain term. USER DEFINED FUNCTIONS / FUNCTION BLOCKS - A single function block must be available to allow repetitive call of a function. A password to protect the integrity of the subroutine must also be available during compile time. These functions will be able to be stored in a library for later usage. A Subroutine may be called from within another subroutine. The nesting can be at least 8 levels deep. In addition to the user-defined functions and function blocks, there are several other organization blocks which are integrated into the CPU. A Cyclic Interrupt shall be available that is executed once a programmable interval. The interval shall be between 1 and 60,000 milliseconds. All I/O shall be available to update during the execution of the subroutine. Depending on the selected CPU, you may have anywhere from 1 to 8 of these interrupts available. A Time-of-Day Interrupt shall be available that can be selectively executed once, every minute, every hour, every day, every week, every month, end of every month, yearly. Depending on the selected CPU, you may have anywhere from 1 to 8 of these interrupts available. (g) Discete I/O. ELECTRICAL SPECIFICATIONS - I/O modules shall be designed for 1500 volt isolation between the field wiring and the system backplane. MODULARITY - Interface between the PLC and user supplied input and output field devices shall be provided by rack type I/O modules

11 CONFIGURATION - All I/O will be modular without placement restrictions. I/O will be available in discrete, analog, special function modules, and communication processors. The I/O system shall accommodate up to 4 total racks or 32 I/O slots. The maximum distance between local expansion racks will be a total distance of 32 feet. Expansion I/O racks shall be connected to the CPU rack via a pair of Interface Modules (IM) and a cable. An IM-Send module resides in the CPU rack while IM- Receive modules reside in the expansion racks. I/O ADDRESSING - I/O reference addressing for each I/O module shall be automatically assigned through the use of the PC compatible configuration and programming. The user must also have the ability to manually configure individual I/O module addresses and have the software check the assigned address to determine if the address range is already assigned. There shall be no jumpers or DIP switch settings required to address modules. The circuit status of each I/O point on a module shall be indicated by a green LED mounted at the top of the module. These LED s must be visible through a clear plastic lens. Each LED shall illuminate an LED indicating the On/Off status of the discrete I/O point. Addressing of all references including I/O must be represented as a Decimal Based number. (h) Input Specifications. The 120 Volt AC input module shall accommodate an input voltage range from 0 to 132 volts. The 24 Volt DC positive and negative logic input modules shall accommodate an input voltage range of -3 to +30 volts DC. AVAILABILITY OF INPUT MODULES - As a minimum, the following discrete input modules shall be available: Description Points/Module Input / Output Simulator (configurable) 16 In / 16 Out / 8 In + 8 Out 120 Input 16 / / 230 VAC Input 8 24 VDC Input with Diagnostic Interrupt / Diagnostics VDC, Sourcing Logic Input 4 / 8 / 16 / VDC, Sinking/Sourcing Logic Input VDC Input

12 (i) Output Specifications. Discrete AC output modules shall have separate and independent commons allowing each group to be used on different phases of AC supply. Each discrete AC output shall be provided with an RC snubber to protect against transient electrical noise on the power line. Discrete DC output modules shall be available with positive and negative logic characteristics in compliance with the IEC industry standard. Discrete DC output modules shall be provided with at least eight output points in a group with a common power input terminal per group. Discrete DC output modules shall be compatible with a wide range of user-supplied load devices, such as: motor starters, solenoids, and indicators. AVAILABILITY OF OUTPUT MODULES - As a minimum, the following discrete output modules shall be available: Description Points/Module 15 VDC / 20 ma Optically Isolated 4 24 VDC / 20 ma Optically Isolated 4 24 VDC 8 24 VDC, Optically Isolated 8 /16 / VDC VAC Optically Isolated VAC Optically Isolated / 230 VAC Optically Isolated / 230 VAC Optically Isolated 8 Relay, Normally Open Optically Isolated 8 / 16 Relay, Normally Open Optically Isolated 8 Relay, Normally Open Optically Isolated 8 AVAILABILITY OF MIXED I/O MODULES - As a minimum, the following discrete output modules shall be available: Description Points/Module 24 VDC Optically Isolated, 0.5A 8 in, 8 out 24 VDC Optically Isolated, 0.5A 16 in, 16 out (j) ANALOG I/O. GENERAL SPECIFICATIONS - For the conversion of analog to digital and digital to analog conversion required by an application, the following shall be available:

13 ANALOG INPUT - The standard analog voltage input module shall be capable of converting 8 channels of inputs in the following ranges: Voltage: -10 to +10 volts, 1-5 volts, -5 volts to +5 volts, -1 to +1 volts, mv to +500 mv, -250 mv to +250 mv, -80 volts to +80 volts. Thermocouple: Type J, Type K, Type N, Type E, Type L RTD: Pt100 and Ni100 in standard and climactic ranges 4 Wire Transmitter: -20 to +20 ma, 4 to 20 ma, 0 to 20 ma, -10 ma to +10 ma, and -3.2 ma to +3.2 ma 2 Wire Transmitter: 4 to 20 ma Resolution of the converted analog voltage input signal shall be configurable from 9 to 14 bits binary depending on the user s desired integration time. All of the channels of converted analog voltage input signals shall be updated on the module and transferred to the PLC upon request. The conversion speed for all of the analog voltage input channels shall be no less than 2.5 milliseconds and no greater than 100 milliseconds.. ANALOG VOLTAGE OUTPUT - The analog voltage output module shall be capable of converting 2 or 4 channels of digital data to analog outputs in the following ranges: Voltage: -10 to +10 volts, 0 to 10 volts, 1 to 5 volts Current: -20 to +20 ma, 0 to 20 ma, 4 to 20 ma Resolution of the converted output signal shall be 12 bits or 16 bits. All channels of analog output data shall be updated each scan from the analog module. Analog outputs with diagnostics shall be configurable to hold-last-state in the event of a CPU failure. MODULE AVAILABILITY - As a minimum, the following analog modules shall be available: Description Channels/Module Input 2, 4,

14 Output 2, 4 Combo Analog Inputs/Outputs 2, 4 (k) Communications. PEER/PEER COMMUNICATIONS - The PLC shall have the capability to communicate on a token passing peer-to-peer, noise immune network providing high-speed transfer of control data with no additional user programming required. The peer-to-peer communications will be configurable to broadcast data to and receive data from up to 16 other CPUs on the MPI network. Each CPU can exchange up to 4 packets of 22 bytes of data each. The communication medium used by this peer/peer communications network shall be a high energy and noise immune single shielded twisted pair cable transmitting data at an adjustable rate from Kbaud to 12 Mbaud. The distance of the communication shall be up to 50 meters without a repeater, 9100 meters via fiber optic cables or 23.8 km with 16 star couplers and Optical Link Modules. MASTER/SLAVE COMMUNICATIONS - The CPU shall provide 2 distinct communication protocols, The CPU will be able to be designated as a PROFIBUS Master in a communication scheme that allows the PLC to interrogate other PLCs for data. The CPU will also be able to be designated as a PROFIBUS Slave in a communication scheme that allows other PLCs to interrogate it for data. (3) Electrical Requirements. (a) Data Performance Requirements. The unit shall support RS-232D or latest. (b) Data Rate. The unit shall be transparent to all data rates up to 64 kbps. (c) Construction. Terminal blocks shall be easily removable, and common to all discrete and analog I/O to allow for convenient pre-wiring of field devices. Various types of terminal blocks should be made available to the user for connection flexibility. Each I/O module shall contain a hinged, plastic, terminal block cover (door) with a removable label. The door of the module shall have the module description, catalog number, and circuit wiring diagram for that module type, and the outside of the label shall have a user legend space to record circuit identification information. The terminal blocks will have 2 positions: 1) wiring the module with no power to the terminal block, and 2) connection of the terminal block to the I/O circuitry

15 Once a terminal block is attached to an I/O module, the terminal block shall have a feature that allows the terminal block to be connected to a module of the same type to ensure user and equipment safety. (d) Power Requirements. The power supply shall be AC In/DC Out operating from a voltage source in the range of 110 to 230 VAC on the input side. Available power shall be 2 / 5 / 10 Amps at a +24 VDC output. The power supply shall contain an isolated, internal 24VDC power source for I/O modules requiring 24VDC power. The power supply shall contain a switch which determines the input voltage level for either 110 VAC or 230 VAC. The power supply shall be modular in design, separate from the CPU and rack mounted for easy replacement. The power supply shall be universal in design, compatible with main CPU racks, as well as with expansion racks. (e) Radio Interference. Shall comply with the limits for Class A computing device in accordance with the specifications in Subpart J of Part 15 of FCC rules. (4) Mechanical Requirements. (a) Connectors. The unit shall house 9 DB25 female connectors. (b) LEDs. The unit shall at a minimum visually indicate via LEDs slave port status as active or inactive and status of power. (c) The unit shall be rack mounted. (5) Environmental Requirements. All components of the controller system shall meet the following environmental specifications: (a) Operating Humidity. Five to 95% relative humidity, noncondensing. (b) Operating Temperature. -10 F to 140 F (-25 C to 60 C). 3. Construction Methods. (1) General. The equipment design and construction shall utilize the latest available techniques with a minimum number of parts, subassemblies, circuits, cards, and modules to standardization and commonality. The equipment shall be designed for ease of maintenance. All component parts shall be readily accessible for inspection and maintenance. (2) Electronic Components. All electronic components shall comply with Special Specification, "Electronic Components"

16 (3) Mechanical Components. All external screws, nuts, and locking washers shall be stainless steel; no self-tapping screws shall be used unless approved by the Engineer. All parts shall be made of corrosion resistant material, such as plastic, stainless steel, anodized aluminum, or brass. All materials used in construction shall be protected from fungus growth and moisture deterioration. Dissimilar metals shall be separated by an inert dielectric material. 4. Equipment Installation and Integration. The Contractor shall install programmable logic controller units to perform the functions shown on the plans. The Contractor shall also be required to integrate the PLC units and existing field equipment so that this equipment and the equipment and software provided in accordance with Special Specification Item, Human Machine Interface Software form a fully functioning system capable of performing the functional requirements shown on the plans. 5. Documentation Requirements. The documentation requirements shall be in accordance with the Special Specification, Testing, Training, Documentation, Final Acceptance and Warranty, Article Testing. Each port shall perform at or less than one bit error per 1x10^6 bits on a continuous data stream, on a standard 511 block test for a period of 24 hours. The testing shall be in accordance with the Special Specification, Testing, Training, Documentation, Final Acceptance and Warranty, Article Training. The training shall be in accordance with the Special Specification, Testing, Training, Documentation, Final Acceptance and Warranty, Article Warranty. The Warranty shall be in accordance with the Special Specification, Testing, Training, Documentation, Final Acceptance and Warranty, Article Measurement. This Item will be measured as each unit furnished, installed, integrated and made fully operational and tested in accordance with these Special Specifications. 10. Payment. The work performed and materials furnished in accordance with this Item and measured as provided under Measurement will be paid for at the unit price bid for "Programmable Logic Controller". This price shall include all equipment described under this Item with all cables and connectors, all documentation and testing; all equipment integration, and shall include the cost of furnishing all labor, materials, training, warranty, equipment, and incidentals necessary to complete the work