Name: ESE370 Fall 2012

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1 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2012 Final Friday, December 14 Problem weightings shown. Calculators allowed. Closed book = No text or notes allowed. Final answers here. Additional workspace in exam book. Note where to find work in exam book if relevant. Sign Code of Academic Integrity statement at back of exam book. Name: 1

2 Default technology: 22nm Low Standby Power Process (LSTP) γ = 1 V dd =900mV nominal V thn = V thp =600mV C 0 = F (for W = 1 device) I d,sat0 = 10µA (for W = 1 device) I sd,leak0 = 0.3 pa (for W = 1 device) velocity saturated operation R wire = 700KΩ/cm C wire = 1.7pF/cm prefix scale G Giga 10 9 M Mega 10 6 K Kilo 10 3 c centi 10 2 m milli 10 3 µ micro 10 6 n nano 10 9 p pico f femto Optimally buffered wiring: R0 (γ + 1)C 0 L seg = 2 (1) R wire C wire Transmission line: W buf = w = R0 C wire 2R wire C 0 (2) c ɛr µ r (3) where c = m/s. 2

3 1. Communication over a distance. For this problem, you want to send a signal across 1 cm of an integrated circuit chip. You will evaluate delay and energy for 3 scenarios then estimate how one will change when we scale technology. Show symbolic equations and final absolute numbers (ns, J). (a) What is R 0 and τ for this technology? [5pts] R 0 (b) What is the delay to send a bit from one end of the wire to the other on an unbuffered wire driven by a minimum size (W = 1) inverter? [5pts] τ (c) What is the energy per bit transmitted for the unbuffered scenario above? [5pts] 3

4 (d) If you buffered the wire with a W buf =74 every L seg =3.3mm and try to drive the wire with minimum delay, what is the delay to send a bit from one end of the wire to the other, starting from a minimum size inverter as the input? Describe all the buffers you add to drive the wire and their size and placement. [10pts] Hint: Write down equations will all the terms. Don t omit any before evaluating magnitude. This should have been optimally buffered with L seg =0.033mm as a slight simplification on 0.034mm. R0 (γ + 1)C 0 L seg = 2 = R wire C wire /cm /cm = 2 3 2cm (4) 10 6 L seg = 2 3 2cm = cm (5) Buffers and sizing 4

5 (e) What is the energy per bit transmitted for the buffered scenario above? [5pts] 5

6 (f) Consider transmitting the bit for the 1 cm distance by sending it off chip through a Z = 50Ω transmission line on a PCB with ɛ r = 4, µ r = 1. Your design should include the circuitry for driving and terminating the transmission line with minimum delay starting from a minimum size inverter. What is the delay to send a bit from this inverter, through the output driver, across 1 cm on the PCB, through a receiver back onto the IC, including any settling time necessary? [10pts] Show circuit and sizing (g) For the above case, assuming a pulse width equal to the delay found in part (f), what is the energy per bit transmitted for this off-chip transmission line scenario? [5pts] 6

7 (h) How does the energy and delay for the transmission line case change when we scale to an 11nm process? PCB parameters are unchanged. Process technology parameters at 11nm are: V dd =670mV C 0 = F I d,sat0 = 8µA R wire = 7MΩ/cm C wire = 1.4pF/cm Give the final energy and delay for transmission line case at 11nm. [5pts] Trans. Line (f) Delay Energy 7

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9 2. Sequentially Accessed Memory. In this problem, we will consider an N-bit memory that we wish to read from sequentially (read 0, read 1,... read N-1, read 0, read 1...). For this problem, ignore wire delay and wire capacitance. You will add that in Problem 3. Answer for this question will include N as a parameter, but otherwise should be reduced to constants. Show your symbolic formulation, circuit assumptions, and sizing details. (a) Consider using the or-tree shown. Each stage uses one bit of the address to select the subtree, and only sends the address down the selected subtree. Provided optimize transistor-level logic in each tree stage to reduce the delay and report the resulting total delay per bit read. You may (should) change the exact decomposition into gates, choice of gates, and sizing as long as you achieve the same logical behavior. [10pts] read enable address counter read data out read enable Mem bit W=1 data bit both access transistors have W=1; R0 drive for Mem bit. en a3 a2 a1 read data L.enable R.enable L.a1 R.a1 L.a0 R.a0 L.data R.data See next page for figure correction. 9

10 Should be: read enable address counter read data out read enable Mem bit W=1 data bit both access transistors have W=1; R0 drive for Mem bit. en a2 a1 a0 read data L.enable R.enable L.a1 R.a1 L.a0 R.a0 L.data R.data (answers on following page) 10

11 Show optimized tree stage logic at transistor level. Hierarchical schematics acceptable. Annotate delay of gates at the logic gate stage level along the critical path. 11

12 (b) For the above design, what is the average energy per bit read? i. on the data read path (from the enabled memory cell to the data read output). [5pts] Data Read ii. on the address path (from the counter to the enables at the memory cells). [5pts] Hint: How much energy is switched for when address bit a i switches? How many times does bit a i switch when reading through the entire memory? You may use an upper bound approximation that is within a factor of two or leave results formulated as a summation. Addressing 12

13 (c) What benefits do we get for delay and energy from using an or gate at each tree level in the previous design as opposed to a monlithic pass-gate mux design as shown below? Give an explanation using equations, but you do not need to calculate specific constants. [5pts] read enable address counter read data out read enable Mem bit data bit en a3 a2 a1 read data L.enable R.enable L.a1 R.a1 L.a0 R.a0 Explanation: L.data R.data 13

14 3. Scaling of Sequentially Accessed Memory. For this problem, we consider scaling the memory to a full chip with N = We also consider the impact of wire delay in the or-tree (2a). Assume the top wire in the tree is 1cm long and every second tree level the wire lengh halves (1cm, 1cm, 0.5cm, 0.5cm, 0.25cm,...). When wires are longer than L seg =3.3mm, buffer wires with W = 74 inverters as in 1d. Size up the or gates to match the wire buffering. Hint: You should be able to adapt your results from problems 1d and 2a to answer a and b. Answers for this question should be reduced to absolute constants. Show your symbolic formulation and sizing details. (a) What is the delay to read a bit? [5pts] (b) What fraction of the delay is due to the wires and wire buffering? (if C wire = 0, what fraction of the delay would go away?) [5pts] 14

15 (c) At your identified delay time (assuming you use that as the cycle time) and assuming each memory bit leaks at 2I sd,leak0 and accounting for leakage within the addressing and or-tree, what is the leakage energy per read cycle? [5pts] Hint: There are roughly four times as many total and gates in the original tree as or gates. You may use this relation to simplify your calculation. 15

16 4. Bus data sequence. Consider the address bus from the previous problem. Particularly, consider the wires at the top of the tree that run side-by-side for a long distance. For the sequential access case, if we use a simple binary counter to address the memory, the value transitions on this bus are not random. If we are only accessing the values in sequence, we could recode the address sequence to use a Gray Code that has the property that successive values differ in a single bit position (e.g. for a 3-bit Gray Code: ). Assume the wire-to-wire capacitance is equal to the wire-to-ground capacitance. Without loss of generality, consider the timing impact on the middle bit in a 3-bit bus. (a) Identify how the worst-case transmission speed of the middle bit differs in the three cases (random data, binary-counter sequence, Gray Code sequence). For full credit, explain why it is different in each case and estimate the magnitude of the difference. [5pts] Case Delay Explain (compare random) random 0 binary counter Gray Code counter 16

17 (b) Assuming the counter and the bus buffers for the entire bus all share a V dd pin and a ground pin, how does the worst-case noise on these power pins differ between the two cases (binary counter, Gray Code counter). For full credit, explain why it is different in each case and estimate the magnitude of the difference. [5pts] Case binary 0 counter Change in Explain noise level Gray Code counter 17

ESE370 Fall ESE370, Fall 2015 Project 2: Memory Design Wednesday, Nov. 11

ESE370 Fall ESE370, Fall 2015 Project 2: Memory Design Wednesday, Nov. 11 ESE370 Fall 205 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Project 2: Memory Design