Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
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1 Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs Roel Maes 1, Pim Tuyls 1,2, Ingrid Verbauwhede 1 1. COSIC, K.U.Leuven and IBBT 2. Intrinsic-ID, Eindhoven Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne
2 Overview 1. Introduction 2. Key generation with SRAM PUFs 3. Toeplitz-based Universal Hashing 4. Implementation Results 5. Conclusion Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 2
3 Introduction Tampering attacks threaten secure key storage Traditional tampering countermeasures induce large overhead (cost/size/power/ ) IBM 4764 $ 8600 Need for low-overhead physical protection of sensitive data PUFs Challenge PUF Physics Response Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 3
4 Overview 1. Introduction 2. Key generation with SRAM PUFs Related Work Soft Decision Helper Data Datapath Design 3. Toeplitz-based Universal Hashing 4. Implementation Results 5. Conclusion Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 4
5 Related work: The SRAM PUF Random manufacturing variability in ICs is a fact Power-up state of SRAM cells efficiently measures intrinsic device variability SRAM PUF [GKST-CHES07] (SRAM) PUF responses are noisy and non-uniform fuzzy secret Challenge: memory address Power-up: SRAM cell Response: power-up state 0 Intra-device variation: Same device, many measurements Inter-device variation: Same measurement, many devices Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 5
6 Related work: Helper Data Algorithms HDA or Fuzzy Extractor extracts a secure key from a fuzzy secret ω C R K PUF Helper Data PUF HDA generate (ω,σ) C R K HDA reproduce R ECC Correct ω HDA reproduce σ Universal Hash K Efficient implementation possible [BGSST-CHES08] ECC Correct Linear Block Codes: Golay Repetition or Reed-Muller Repetition Universal Hash = = LFSR-based Toeplitz Universal Hash [Krawczyk-Crypto94] Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 6
7 SRAM PUF Response Characteristics C SRAM PUF Repeated measurement of the same response R (0) R (1) R (2) R (3) R (4) Histogram of P e from 6592 bits estimated from 350 measurements = Distribution according to previous work [GKST-CHES07;BGSST-CHES08] = Distribution according to our new model [MTV-ISIT09] Average Response ~ Bit Probability Most-likely Response (R ML ) Individual Bit-error Probability (P e ) Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 7
8 Soft Decision HDA Regular error-correcting algorithms assume fixed bit error probability for every bit Additional reliability information of every response bit is available enables Soft-Decision error correction (SD) improves efficiency of ECC algorithm P e H (R ω HD ) H (R ω SD, P e ) H (R) SD decoding reduces min-entropy loss Less SRAM cells needed for key extraction R (i) ω ECC ECC Soft Decision Correct Correct ω R ML Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 8
9 Soft Decision Error Correction Reliability information Log-likelihood ratio Soft-Decision Maximum Likelihood Decoding (SDML) exponential complexity in code dimension ok for repetition codes Generalized Multiple Concatenated decoding (GMC) of Reed-Muller Codes P e L Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 9 SDML-decoding: SD-Repetition-Decode(L) = (L i ) SD-Degenerate-Decode(L) = L GMC-decoding: RM r-1,m RM r,m RM r-1,m-1 RM 1,m = Repetition Code SDML RM r,r = Degenerate Code SDML
10 Soft-decision decoder: Datapath Data In Arithmetic Unit Input Register File 64x8-bit MUX 8 8 +/-/0 +/-/0 Accumulate Register >> Instruction Decode Output Register File 32x8-bit Data Out Controller Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 10
11 Overview 1. Introduction 2. Key generation with SRAM PUFs 3. Toeplitz-based Universal Hashing Related Work Datapath Design 4. Implementation Results 5. Conclusion Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 11
12 Related Work: Toeplitz Universal Hash (2-)Universal Hash Family H = {h i : A B} i=1..n œ a 1 a 2 0 A and r [1,n]: Pr[h r (a 1 )=h r (a 2 )] B -1 Multiplication with random Toeplitz matrix is Universal Hash yields efficient LFSR-based implementation [Krawczyk-Crypto94] Straightforward implementation not optimized for FPGA e.g. if Message = 64 bit and Hash = 128 bit then: 128-bit LFSR + 64-bit SR bit accumulator = 320 flip-flops = at least 160 FPGA slices Message 64 Shift Register LFSR Accumulate Register 128 Hash Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne
13 Toeplitz Hash: Datapath Optimize for FPGA: use resource-efficient shift registers based on Look-up-tables (LUTs) 11 LUTs Message 160 LFSR 176-bit LUTs Register File 16x4-bit 4 11 [10..7] [4..1] [3..0] 11 LUTs Total: 26 LUTs = at least 13 FPGA slices for implementing (shift) registers vs 160 with flip-flops! Shift Register 16-bit Shift Register 16-bit Hash Shift Register 16-bit Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 13
14 Overview 1. Introduction 2. Key generation with SRAM PUFs 3. Toeplitz-based Universal Hashing 4. Implementation Results 5. Conclusion Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 14
15 Implementation Results Implemented on Xilinx Spartan 3E-500 FPGA Compare with best results from [BGSST-CHES2008] Setting: Results: Average response bit error probability: 15% Min-entropy of response bits: 78% Extract 128-bit key Proposed SD-HDA Implementation [BGSST-CHES2008] PUF-optimized DP [BGSST-CHES2008] HDA-optimized DP HDA size (slices) Cycles Performance 50.2MHz 151.5MHz 175.4MHz SRAM PUF size 1536 bit 3696 bit 6160 bit Helper Data length bit 3824 bit 6288 bit Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 15
16 Overview 1. Introduction 2. Key generation with SRAM PUFs 3. Toeplitz-based Universal Hashing 4. Implementation Results 5. Conclusion Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 16
17 Conclusion PUF-based secret key storage is very appealing, but implementation overhead should be small! Efficient Soft-Decision Decoder reduces minentropy loss of HDA smaller PUF (-58.4%) Using FPGA-optimized shift registers significantly reduces implementation cost of Universal Hash smaller HDA (-44.8%) Increased Helper Data length and more effort during enrollment are trade-offs Thank you! Workshop on Cryptographic Hardware and Embedded Systems, CHES 2009, Lausanne 17
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