The Versatile Link PLUS Project V

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1 The Versatile Link PLUS Project V Francois Vasey and Jan Troska, Physics Department, CERN, Geneva, Switzerland Daniel Ricci and Simao Machado, Engineering Department, CERN, Geneva, Switzerland Alan Prosser, Electronic Systems Engineering (ESE) department, Fermilab, USA Todd Huffman and Tony Weidberg, Department of Physics, Oford University, United Kingdom Jingbo Ye, Department of Physics, Southern Methodist University, Dallas TX, USA Ping Gui, Department of Electrical Engineering, Southern Methodist University, Dallas TX, USA 1 General Project Description 1.1 Introduction Radiation tolerant, high speed optoelectronic data transmission links are fundamental building blocks in today s large scale HEP detectors, as eemplified by the four LHC eperiments commissioned in The Versatile Link project 1 (VL), active from 2008 to 2012, developed a common link platform for the phase I upgrades of the ALICE, ATLAS, CMS and LHCb eperiments. It also found applications in the machine sector (beam instrumentation) and at GSI (CBM eperiment). It successfully developed a point-to-point, uni- or bidirectional, single- or multi-mode data link operating at 4.8Gbps, and resistant to calorimeter-grade radiation levels. The Versatile Link PLUS project (VL + ) targets the phase II upgrades of the ATLAS and CMS eperiments. It will develop a data link resisting tracker-grade radiation levels, covering 5-10Gbps data rates in the upstream direction and 2.5-5Gbps rates in the downstream, and will achieve a smaller footprint and higher channel count than its predecessor at the front-end. A low-profile package will be developed that allows volume production at reduced costs, but which nevertheless can be configured at assembly time to suit the individual needs of different detectors (number of channels, directionality, etc.). 1.2 Structure The VL + project is broken down into 7 concurrent workpackages (see section 1.4 below). Each workpackage is under the technical and financial responsibility of one institute. A steering board composed of one representative from each partner institute steers the versatile link project under the guidance of the project manager. The institutes report to their respective funding agencies regarding their workpackage(s). The project as a whole reports to the eperiments via the ATLAS and CMS HL-LHC upgrade steering groups. The VL + project will operate in much the same way as its predecessor. Periodic (bi-monthly) phone conferences, complemented by less frequent (but at least annual) face-to-face meetings will ensure the cohesion of the developments. General status reports will be presented at common workshops (ACES, TWEPP, etc.) and dedicated reports will be given to specific eperiments upon request. Information and documentation will be shared in a dedicated sharepoint site

2 1.3 Partners The VL + project workpackages and partners are listed in Table 1 below. Project partners may collaborate with associate partners to work on specific, well defined tasks (see the workpackage description for more details). Workpackage WP 7 has not yet been assigned. Additional partners are thus welcome to join the project. Workpackage Description Project Partner in charge Contact Person Proj. mgmt Presides project steering board CERN Francois Vasey WP 1 10Gbps LDD - Array Southern Methodist University Jingbo Ye Ping Gui - Discrete channel WP 2 Opto Die (PIN & VCSEL) CERN-PH Jan Troska WP 3 Opto Module (VTR+) CERN-PH Jan Troska WP 4 Opto Module Reliability University of Oford Tony Weidberg WP 5 Passive Components CERN-EN Simao Machado WP 6 Backend FNAL Alan Prosser WP 7 System unassigned Table 1 Workpackages and Project Partners in charge 1.4 Workpackages Each workpackage is under the responsibility of one institute (see Table 1). The project-level description given in this section is a general outline. More details are to be found in section 2, where each workpackage is presented individually as a sub-project WP 1. 10Gbps LDD The VL + data link will operate at up to ~10Gbps in the upstream direction and up to 5Gbps in the downstream (as a comparison, the VL operates at 4.8Gbps in both directions). This will necessitate the development of a new 10Gbps Laser Diode Driver (LDD), resistant to tracker grade radiation levels. The laser will be of the VCSEL type, requiring a compliance voltage of at least 2.5V. Its anode will be directly bonded to the single ended driver output. Its cathode will be at common ground potential. Two LDD developments are envisaged for the first phase of the project: a single channel circuit capable of driving individual VCSEL die, and a 4-channel array circuit capable of driving a VCSEL array with a 250μm channel pitch WP 2. Opto Die The very small footprint of the VL + module requires moving away from the TOSA/ROSA concept used by the VL legacy project. This implies that, even though the chip performance specifications will not differ significantly from their VL counterpart, new bare VCSEL and PIN chips must be sourced and qualified to tracker grade radiation levels. In the case of VCSELs, both single channel and arrays will need to be qualified. In the case of PINs, both InGaAs and AlGaAs diodes will need to be compared in terms of responsivity and leakage current at high fluences. The evaluated devices shall be compatible with the ASICs and modules developed by WP1 and WP WP 3. Opto Module (VTR + ) The VTR + module is epected to be multi-channel and configurable. This will be achieved either by populating discrete T and R channels in a package according to end-user requirement, or by turning on/off channels in a 4- channel array. A lot of uncertainty eists at this stage as to the final form the module might take. At least two concepts will be investigated: a) work closely with manufacturers to implant VL + die into an already developed commercial module (discrete channels or array), or b) develop in-house a full custom package based on commercially available optical coupling elements. Progress with these approaches during the first project phase will indicate which are the most promising candidate schemes to be further investigated in subsequent phases WP 4 Opto-Module reliability In contrast to the VTR module where the optical elements are based on sealed commercial ROSA and TOSA assemblies, the VTR + project relies on bare die assembled on a PCB substrate and directly bonded to the driving and receiving electronics. This puts a lot of importance on the long term reliability of these components and assemblies. A robust reliability test program will include: accelerated ageing, 85/85 damp heat, ESD, Highly Accelerated Lifetime Test (HALT), etc.

3 1.4.5 WP 5. Passive Components The market for passive optical components is in constant evolution, driven by the needs of large data centers to increase their interconnect density and bandwidth. Emerging fiber, cable and connector types will need to be qualified for use in VL + systems, in synergy with tests being conducted for the LHC machine. Apart from radiation resistance, issues to be addressed will include: OM3 vs OM4 fiber type, ribbon vs micro-tube cables, MT/MPO vs MXC (or others) array connectors, etc. This will require a rolling market survey and evaluation program, as well as frequent radiation resistance test campaigns in the cold and at room temperature WP 6. Back-End With the advent of 100G and 400G Ethernet compliant networked devices, new generations of active multi-channel TR small form factor pluggable modules are being introduced that run at increased speeds and reduced power. FPGA serializers and deserializers are also announced that will move the current 10Gbps benchmark datarate to 25Gbps or above in the net couple of years. With this evolution in mind, the task of WP6 will be to identify modern commercial back-end TR multi-channel modules compatible with: a) the 2.5-5Gbps downstream and 5-10Gbps upstream datarates to and from the Front-End, and b) the latest FPGA series likely to be used in the final back-end electronics of the eperiments. Interestingly, this might result in a selection of conservative components when compared to state of the art products, a position difficult to hold in a rapidly evolving market WP 7. System WP7 ensures that the components developed by the other project workpackages will interoperate reliably during the lifetime of the system. It establishes the power and timing budgets, and checks (on paper and eperimentally) the margins in all corners of the operating space. It also demonstrates the interface of the VL+ components with frontend and back-end LP-GBT electronics. Much of the work already carried out in the contet of the VL project applies also to the VL+, so there is no immediate need for new information to be available before starting the project. WP7 is thus delayed until a partner (ideally, an informed user from an eperiment) shows interest. This delay should not be longer than project phase Timescales The VL + project was officially announced at ACES 2014 and started on 1 Apr It is subdivided in three phases of 18 months each: - Phase 1: proof of concept (Apr 2014 Oct 2015) - Phase 2: feasibility demonstration (Oct 2015 Apr 2017) - Phase 3: pre-production readiness (Apr 2017 Oct 2018) A detailed schedule will be defined before each phase to account for possible variations in resources, timescales and technical difficulties. 1.6 Deliverables Phase 1: proof of concept (Apr 2014 Oct 2015) - Tentative specifications for components and system based on eperience - Non-ehaustive portfolio of components shown to meet (even partially) the tentative specifications - Development of test bench(es) for components and system - Development of a Front-End Transceiver prototype based on components provided or tested by VL+ workpackage partners - Preliminary functionality test results for all components - Preliminary irradiation test results - Preliminary reliability test results - Recommendations for phase 2 Phase 2: Feasibility study (Oct 2015 Apr 2017) - Detailed specifications for components and system based on phase 1 recommendations and interactions with users - Components and Variants shortlist - Front-end Transceiver package definition and prototype fabrication integrating ASICs and validated optoelectronics - Complete set of functionality test results for all components - Complete set of irradiation test results for front-end and passive components - Complete set of reliability test results for front-end components - System demonstrators with validated components - Preliminary evaluation of production costs versus volume

4 Phase 3: Pre-production readiness (Apr 2017 Oct 2018) - Specification freeze - Formal market survey - Validation of samples supplied in market survey framework (functionality and radiation hardness) - Manufacturers shortlist - Production cost matri 2 Detailed Workpackage description 2.1 WP 1. 10Gbps LDD Project partner: Southern Methodist University, Work Package Coordinators: Jingbo Ye (array laser driver), Ping Gui (single channel laser driver) Associate partner: Institute of Physics, Academia Sinica, Taiwan (Suen Hou and P.K. Teng) Workplan for Single Channel Laser Driver Phase 1: proof of concept Activities and Deliverables (Apr 2014 Oct 2015) - Tentative specification of the low-power 10Gb/s GBLD (LpGBLD) - Investigation on the electrical characteristics and modeling of the VCSEL diodes - Investigation on different output driver architectures and design of the 10 Gb/s Output driver - Investigation on different pre-emphasis techniques and design of the pre-emphasis circuit - Layout of the output driver and the pre-emphasis circuits - Design and layout of the limiting amplifier (LA) - Integration of the LA with the output driver and pre-emphasis, including ESD diode - Design and layout of the digital-to-analog converters (DACs) for the laser biasing, modulation and preemphasis stages. Synthesis/Design of the digital control circuits including the I 2 C interface - Design of the I/O circuitry - Full chip layout integration and top-level simulation - Delivery of the final gds for fabrication - In-lab measurements of the LpGBLD including the electrical and optical test - Irradiation tests of the LpGBLD chip - Distribution of the LpGBLD to other workpackages, if required Phase 2 (Feasibility) Activities and Deliverables (Oct2015 Apr 2017) - Detailed specifications of LpGBLD based on phase 1 recommendations and interaction with users - Circuit modifications and tape-out of the final version of LpGBLD. - Measurement of the final LpGBLD - Full characterization of the LpGBLD with both electrical and optical tests - Full evaluation in radiation to HL-LHC eperiments tracker grade radiation levels - Distribution of the LpGBLD to other workpackages, if required - Complete design documents and user manual Phase 3 (Pre-Production Readiness) Activities and Deliverables (Apr 2017 Oct 2018) - Finalization of the design and specification - Final submission and full evaluation - Transfer the design to CERN for production readiness Workplan for Array Laser Driver Phase 1 (Proof of Concept) Activities and Deliverables (Apr 2014 Oct 2015) - Tentative Specification of the array VCSEL driver for members of the other work packages. - Prototype submission in Dec based on an eisting design in 0.25 um SOS technology. - Tests of this prototype will be in March May of 2015, based on the MOI/Prizm active alignment scheme developed at SMU, to prove the open-drain design concept of the array driver. If needed, I2C interface will be added in a later submission (maybe Oct. 2015). - Distribution of the array VCSEL driver to other workpackages, if required. - Reliability tests of array VCSELs are carried out at IPAS. We will rely on the chip manufacturer for the ASIC reliability. Design details will be documented. - TID and SEE tests will be carried out on this prototype chip together with the VCSELs.

5 - Once the open-drain design concept is proved to be successful for array VCSEL drivers, we plan to migrate the design to 65 nm CMOS to reach higher speeds. Phase 2 (Feasibility) Activities and Deliverables (Oct 2015 Apr 2017) - Test of the SOS array VCSEL driver, if iterated in Oct Detailed array driver specification, compliant to system/user requirements. - Prototype with 65 nm CMOS and demonstrate 10 Gbps operation. - Fully characterized with electrical and optical tests. - Distribution to other workpackages, if required - Full evaluation in radiation to HL-LHC eperiments tracker grade radiation levels. - Complete user manual. Phase 3 (Pre-Production Readiness) Activities and Deliverables (Apr 2017 Oct 2018) - Finalized design and specification. - Final submission and final full evaluation. - Transfer the design to CERN for production readiness. 2.2 WP 2. Opto Die Project partner: CERN (Physics Department), Work Package Coordinators: Jan Troska Associate partner: Institute of Physics, Academia Sinica, Taiwan (Suen Hou and P.K. Teng) The major goal of this work package is to identify opto-electronic die suitable for inclusion in the VTR+ modules. This means both VCSEL transmitters and photodiodes capable of operating at the data-rates of interest (up to 10 Gb/s for transmitters and up to 5 Gb/s for receivers) in the environment of the LHC detectors (low-temperature, magnetic- and radiation fields) Work Plan for Phase 1 (Apr 2014 Oct 2015) The first step will be to identify and build-up relationships with vendors capable of supplying VCSEL and photodiode die. It will be important to be able to source sample quantities of these die that will remain available over the lifetime of the project. The starting point for this will be to work with the vendors that are known to us from the preceding Versatile Link project. In order to be able carry out further testing, the bare die will be minimally packaged to be able to perform static functional and environmental evaluations. We will work with local packaging houses to be able to obtain simple TOSA- and ROSA packages for this testing. Functional evaluations will be carried out to show that the candidate devices can operate at the target data-rates. Initial specifications for the optical characteristics that will be tested will be based upon the Versatile Link specifications. Test benches for functional evaluation that are currently in use for the Versatile Link project will be re-used for this stage of the project. The Tracker-grade of the Versatile Link project will be used to set the environmental requirements on the VL+ die. This means a magnetic field of 4T, a temperature range of -30 to +60 C, and a radiation field of 500 kgy ionizing dose and n/cm 2 20 MeV neutrons. The performance of candidate VCSEL and photodiode die will be evaluated during eposure to these environments Deliverables Specification for single VCSEL die operating at 850 nm with multimode fibre Specification for 4 VCSEL array die operating at 850 nm with multimode fibre Specification for photodiode die operating at 850 nm with multimode fibre Test report on Radiation testing of candidate components Test report on Environmental testing of candidate components Test report on Functionality testing of candidate components Portfolio (vendor & part list) of candidate components 2.3 WP 3. Opto Module (VTR+) Project partner: CERN, PH Department Work Package Coordinator: Jan Troska The major goal of this work package is the development of a multi-channel optical module that will be configurable at build time. It will have up to four optical channels, with up to two receiver channels per module. The likely initial configuration will be one transmit- and one receive channel. The module will be miniaturized with a direct optical connection (i.e. it will not be pigtailed).

6 2.3.1 Work Plan for Phase 1 (Apr 2014 Oct 2015) Two lines of enquiry will be pursued in the development of a suitable Opto Module: customization of an eisting commercially-available module design to suit our needs; and in-house design of a fully custom optical module based on commercially-available optics for fibre-connection of the opto die. Work will be carried out on the former with industrial partners that have already been identified, while the latter will start with optics that has also already been identified. This will serve to inform the discussions with the commercial partners as the module development matures. Once prototypes are available, they will be evaluated against tentative functional and environmental specifications that will be based upon the eisting Versatile Link specifications. The environmental specifications will be based upon the Versatile Link Tracker grade as detailed under section above. In the first phase of development only temperature testing will be carried out in order to confirm the opto die specifications. Full environmental testing will be carried out at a later stage in the project, together with device robustness tests such as ESD and Highly Accelerated Lifetime (HALT) tests. Functional testing will be carried out using eisting test benches that will be minimally modified to operate at the higher transmit data-rate of 10 Gb/s. These test benches will use a miture of instruments and FPGAs to evaluate the performance of the candidate Opto Modules Deliverables Tentative list of configurations (combinations of T/R channels) Tentative specifications for module Test report on Environmental testing Test report on Functionality testing Prototype modules for system testing 2.4 WP 4 Opto-Module reliability Project partner: University of Oford, Work Package Coordinator: Tony Weidberg Associate partner: Institute of Physics, Academia Sinica, Taiwan As the VTR + project relies on bare die assembled on a PCB substrate and directly bonded to the driving and receiving electronics a robust reliability test program will be required. The tests will focus on the VCSELs as their reliability is more difficult to ensure but there will also be some studies for the p-i-n diodes. Accelerated aging tests will be performed by operating devices in an environmental chamber. Simple DC optical power tests will be performed on bare die VCSELs using LAPDs to measure the optical power. AC testing of completed modules would also be performed with the active devices in an environmental chamber, operating at 85C/85% RH. The tests would use a Digital Communications Analyser (DCA) to perform an eye diagram analysis of the performance. The performance would also be studied by measuring the BER as a function of optical power during accelerated ageing tests. Computer controlled switches will allow for multiple devices to be tested at the same time. We will also perform studies of mechanical reliability by operating devices in an environmental chamber and using temperature cycling from -40C to +80C Work Plan Phase 1: proof of concept (Apr 2014 Oct 2015) - Perform DC accelerated ageing test of OSA VCSELs (11 devices) from the current generation of VL; - Perform DC accelerated ageing tests for bare die VCSELs form a range of manufacturers; - Develop infrastructure for AC tests using DCA and BER scans; - Start AC testing of 11 VTR devices from current generation of VL project. Phase 2: feasibility demonstration (Oct 2015 Apr 2017) - Complete AC testing of current generation VTR devices; - Perform mechanical reliability testing for VTR devices; - DC accelerated ageing tests for proposed VL+ VCSELs; - Start AC testing for prototype VL+ packages. Phase 3: pre-production readiness (Apr 2017 Oct 2018) - Perform high statistics DC accelerated ageing studies for selected VCSEL (~ 100 devices); - Perform accelerated ageing tests for selected VL+ package; - Perform mechanical reliability testing for selected VL+ package.

7 2.5 WP 5. Passive Components Project partner: CERN, EN Department Work Package Coordinator: Simao Machado Work Plan Phase 1: proof of concept (Apr 2014 Oct 2015) Collection of specific requirements from VL+ members for the implementation of the fibre passive cabling system by JUL 2015: o Physical 3D path profile (total length, number of bends, required bending radius, available space in PP0/PP1/PPX); o Channel Insertion loss; o Radiation profile from the front-end electronics toward the back-end, including epected dose rates along the fibre path; Tentative specification and Portfolio of the fibre passive cabling system between the front-end and the back-end, including the optical fibres, optical fibre connectors, cable types, ducts and termination equipment by SEP 2015: o Inside the sub-detector, between the front-end and the PP1 (included) based on generic requirement from VL+ members; o Outside of the sub-detector, from PP1 (ecluded) till the back-end electronics; Preliminary results on irradiation tests on conventional multi-mode OM3, OM4 and radiation resistant multi-mode fibres by SEP 2015; Analysis and recommendations for phase 2; Phase 2: feasibility demonstration (Oct 2015 Apr 2017) Completion of irradiation tests on conventional multi-mode OM3, OM4 and radiation resistant multi-mode fibres by JAN 2016; o Provided by CERN frame contracts o Provided by other alternative manufacturers from the VL+ team members; Irradiation tests on cables materials by MAR 2017 o Provided by CERN frame contracts Irradiation tests on connectors by XX.XX.XXXX; Detailed specification for the fibre passive cabling system based on phase 1 recommendations; o Inside the sub-detector, between the front-end and the PP1 (included) based on generic requirement from the VL+ team members; o Outside of the sub-detector, from PP1 (ecluded) till the back-end electronics; Specification of quality control procedures, tests and criteria Market survey for required components: Design and installation of a prototype for validating the components; Preliminary cost estimation versus volume; Phase 3: pre-production readiness (Apr 2017 Oct 2018) Completion of specification; Formal market survey for required components inside the sub-detector, between the front-end and the PP1 (included); Validation of samples provided; Final cost assessment versus volume; Final submission and final full evaluation.

8 2.6 WP 6. Back-End Project partner: Fermilab Work Package Coordinator: Alan Prosser Work Plan for Phase 1 (Apr 2014 Oct 2015) In CY2015, Fermilab will complete or deliver the following: a. Identification of suitable commercially available components. The identification of commercial components suitable for use as back end components requires a thorough understanding of the performance and ease of use of these components, especially within the contet of operation in a system with the radhard on-detector components developed as part of this program. The selection of acceptable components must be based not only on specifications from the vendors but also on thorough testing of samples of these components to verify that their performance meets the special link requirements of these detector readout links. b. Development of required demonstration hardware. Fermilab will design evaluation platforms as needed to operate and test promising optical components These boards will utilize the FMC connector standard to make them available for use with commercially available and custom FPGA boards equipped with high speed SerDes ports. The boards will support transmitter, receiver, and transceiver devices and include control signals from an FPGA for the necessary configuration of the optical modules. If it is more economical or more feasible to utilize vendor provided evaluation hardware, that will be done prior to designing custom demonstration hardware. c. Environmental testing. To verify the operation of components under a range of temperature and humidity conditions, we will employ an environmental chamber to test samples of components. d. Complete set of engineering documentation. As part of the evaluation of back end components, Fermilab will document all test results in a formal test report in which the performance of a given device can be compared with (1) the component specifications for the optical links being engineered and (2) other components which are candidates for use in the back end of such optical links. Standard measurements will be documented in a test plan and the components which are tested will be ranked in order to illustrate what appear to be the best choices for selection. In addition, system level requirements and specifications will be documented for the end to end range of components (front end optoelectronics, fiber plant, connectors, and back end optoelectronics) as well as test methodologies to guide engineers in the development and verification of links provisioned to these specifications. Finally, a cost book with estimates of price as a function of quantity will be maintained. The following lists the schedule for activities to be carried out as part of the work program for VL+. The dates listed here represent the calendar year quarters during which the proposed activities will be carried out. Activity Survey commercial components for use as backend components (transmitters, receivers, transceivers, and FPGAs) Procure samples of components for electrical and optical tests Develop component test procedures, test boards, and perform component tests Development of system specifications and test procedures CY14 Q1 CY14 Q2 CY14 Q3 CY14 Q4 CY15 Q1 CY15 Q2 CY15 Q3 CY15 Q4

9 2.6.2 Deliverables Component Test Plan: The procedures to be used in evaluating candidate components will be thoroughly documented and agreed upon by the members of the collaboration. The procedures will be drawn from common practices and measurement techniques such as those used by the vendors of optoelectronic components. Many of these techniques will be identical or similar to those employed in the Versatile Link project. However, there may be new points of emphasis to be eplored due to the increased focus on parallel channel devices (which includes new performance metrics such as optical and electrical channel crosstalk). The result of this effort will be a formal test plan which will be periodically reviewed for completeness. Component Test Reports: The testing of components to be carried out using the methods and measurements just documented will result in frequently updated test results documentation (updated as new components are added to the inventory of tested devices). This was done for the Versatile Link project on an on-going basis and results for VL+ will similarly be captured. The results for tested components will be reported in a set of standard plots which enable interested researchers to quickly evaluate the performance of an individual multichannel device, as well as discern its relative strengths and weaknesses when comparing it to other devices being evaluated. Component and System Specification Documentation: As the constraints imposed by the performance limitations of the various components to be used in optical link configurations are learned, such knowledge will drive the specification of acceptable components (including back end devices) which may be used to engineer links. For eample, if the suite of available on-detector receivers does not include components as sensitive as one would hope, it may be possible to identify a limited set of back end transmitters suitable for use with these receivers to meet the performance requirements of the overall link. This would be possible if transmitters which typically output a higher optical power are readily available and their performance verified through testing. This is an eample where the system requirements drive the refinement of specifications for components. Thus the specification for components in the link will be closely related to the required overall performance for the link. Sample Engineering Designs and Application Notes: Fermilab has gained eperience in the construction of optoelectronics test stand hardware design as part of its on-going investigation into emerging products. Fermilab has contributed to the suite of components which are compatible for use with the Gigabit Link Interface Board (GLIB) project. Eamples of these are the fabrication of an FPGA Mezzanine Card (FMC) standard daughter card to carry a Versatile Link Transceiver (VTR) and a Twin Transmitter (VTT). As a supplier of some of these GLIB Ecosytem components, Fermilab works closely with hardware and system engineers at CERN to ensure compatibility. Where necessary, application notes, engineering schematics, and any other useful information will be provided to facilitate the use of any components that Fermilab engineers create for use with an FPGA board equipped with an FMC connector. Component Inventory. Fermilab will maintain a small inventory of components which represent best in class eamples of devices for use in back end applications. These components will represent reference components and the performance of other components will be compared with these. The following lists deliverables for the work program represented in this proposal. The dates listed here represent the calendar year quarter during which the proposed milestone will be achieved. Milestones have dates listed more than once because products will continuously be updated or tested. Milestone Component Test Plan Component Test Report (several iterations) Component specification Assemble demonstration test stand (COTS FPGA Board based or custom board) Sample engineering designs and application notes CY15 Q1 CY15 Q2 CY15 Q3 CY15 Q4

10 2.7 WP 7. System Project partner: Fermilab, others? Work Package Coordinator: Fermilab will participate in the delivery of the following as part of its collaboration on system specification and test for the VL+ project. Update to System Specifications. Fermilab will co-author system specifications in accordance with the collaborative effort listed above to develop updated specifications. Development of System Test Framework. Fermilab will partner to develop hardware/firmware/software to represent a test framework that is accessible to eperiments wishing to verify links based upon the project specifications. Verification of VL+ links Using System Test Stand Demonstrator. Fermilab will demonstrate the use of a project system test stand to verify the performance of links developed according to the project specifications.