MM912_637. Xtrinsic Battery Sensor with LIN for 12 V Lead-acid Batteries. Freescale Semiconductor Advance Information

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1 Freescale Semiconductor Advance Information Document Number: MM912_637D1 ev. 3.0, 1/2012 Xtrinsic Battery Sensor with LIN for 12 V Lead-acid Batteries Freescale's Xtrinsic MM912_637 battery sensors are fully integrated battery monitoring devices. The devices allow simultaneous measurement of battery current and voltage for precise determination of SOC (State of Charge), SOH (State of Health), and other parameters. MM912_637 EP SUFFIX (PB-FEE) 98ASA00343D 48-PIN QFN The integrated temperature sensor combined with the close proximity to the battery allows battery temperature measurement. Multiple application-specific hardware blocks reduce MCU overhead and related power consumption. Configurable low-power modes with automated battery state observation and sophisticated wake-up capability further reduce current consumption. The integrated LIN 2.1 interface allows communication and control of battery monitoring functions. Features Battery voltage measurement Battery current measurement in up to eight ranges On chip temperature measurement Normal and two low-power modes Current threshold detection and current averaging in standby => wake-up from low-power mode Triggered wake-up from LIN and periodic wake-up Signal low pass filtering (current, voltage) PGA (programmable low-noise gain amplifier) with automatic gain control feature Accurate internal oscillator (an external quartz oscillator may be used for extended accuracy) Communication via a LIN 2.1, LIN2.0 bus interface S12 microcontroller with 128 kbyte flash, 6.0 kbyte AM, 4.0 kbyte data flash Background debug module External temperature sensor option (TSUP, VTEMP) Optional 2nd external voltage sense input (VOPT) Four x 5.0 V GPIO including one ake-up capable high voltage input (PTB3/L0) Eight x MCU general purpose I/O including SPI functionality Industry standard EMC compliance MM912_637 ADC Supply 2.5 V Supply 5.0 V Supply VDDA AGND ADCGND VDDL VDDH VDDD2D VDDX VDDX Internal Temp Sense Module LIN LGND TSUP VTEMP VOPT VSENSE (optional) Battery Positive Pole + LIN Interface Optional Temp Sense Input and Supply Voltage sense Module Digital Ground eset 5.0 V Digital I/O Debug and External Oscillator MCU Test DGND VSSD2D VSSX ESET ESET_A PA0/MISO PA1/MOSI PA2/SCK PA3/SS PA4 PA5 PA6 PA7 BKGD/MODC PE0/EXTAL PE1/XTAL TEST VSUP ISENSEL ISENSEH PTB0 PTB1 PTB2 PTB3/L0 GNDSUB TCLK TEST_A 4 Battery Negative Pole _ Shunt Chassis Ground Power Supply Current Sense Module -5.0 V GPI/O shared with TIME, SCI and LIN -PTB3 high voltage AKE capable Analog Test Figure 1. Simplified Application Diagram This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Freescale Semiconductor, Inc., All rights reserved.

2 Ordering Information 1 Ordering Information Device (Add an 2 suffix for Tape and eel orders) Temperature ange (T A ) Table 1. Ordering Information Package Maximum Input Voltage Analog Option Flash (kb) MM912I637AM2EP C to 125 C 2 MM912J637AM2EP QFN-EP 42 V MM912I637AV1EP C to 105 C 1 MM912J637AV1EP Part Identification This section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 Description Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received. 2.2 Format and Examples Part numbers for a given device have the following format, followed by a device example: Table 3 - Part Numbering - Analog EMBEDDED MCU + POE : MM 9 cc f xxx r v PPP - MM912I637AM2EP 2.3 Fields Table 2. Analog Options Feature Analog Option 1 Analog Option 2 Cranking Mode Not Characterized or Tested Fully Characterized and Tested External ake-up (PTB3/L0) No Yes External Temperature Sensor Option (VTEMP) No Yes Optional 2nd External Voltage Sense Input (VOPT) No Yes These tables list the possible values for each field in the part number (not all combinations are valid). Freescale Semiconductor 2

3 Part Identification Table 3. Part Numbering - Analog EMBEDDED MCU + POE FIELD DESCIPTION VALUES MM Product Category 9 Memory Type cc f Micro Core Memory Size MM- Qualified Standard SM- Custom Device PM- Prototype Device 9 = Flash, OTP Blank = OM 08 = HC08 12 = HC12 A 1 k B 2 k C 4 k D 8 k E 16 k F 32 k G 48 k H 64 k I 96 k J 128 k xxx Analog Core/Target Assigned by Marketing r evision (default A) t Temperature ange I = 0 C to 85 C C = -40 C to 85 C V = -40 C to 105 C M = -40 C to 125 C v Variation (default blank) PPP Package Designator Assigned by Packaging Tape and eel Indicator Freescale Semiconductor 3

4 Table of Contents 1 Ordering Information Part Identification Description Format and Examples Fields Pin Assignment MM912_637 Pin Description ecommended External Components Pin Structure Electrical Characteristics General Absolute Maximum atings Operating Conditions Supply Currents Static Electrical Characteristics Dynamic Electrical Characteristics Thermal Protection Characteristics Electromagnetic Compatibility (EMC) Functional Description and Application Information MM912_637 - Analog Die Overview Analog Die - Power, Clock and esets - PC Interrupt Module - IQ Current Measurement - ISENSE Voltage Measurement - VSENSE Temperature Measurement - TSENSE Channel Acquisition indow atchdog Basic Timer Module - TIM (TIM16B4C) General Purpose I/O - GPIO LIN Serial Communication Interface (S08SCIV4) Life Time Counter (LTC) Die to Die Interface - Target Embedded Microcontroller - Overview MCU - Port Integration Module (9S12I128PIMV1) MCU - Interrupt Module (S12SINTV1) Memory Map Control (S12PMMCV1) MCU - Debug Module (S12SDBG) MCU - Security (S12XS9SECV2) Background Debug Module (S12SBDMV1) S12 Clock, eset, and Power Management Unit (S12CPMU) MCU - Serial Peripheral Interface (S12SPIV5) kbyte Flash Module (S12FTMC128K1V1) MCU - Die-to-Die Initiator (D2DIV1) MM912_637 - Trimming Introduction IF Trimming Content and Location Memory Map and egisters Packaging Package dimensions evision History Freescale Semiconductor

5 Temp Sense Supply TSUP VOPT VBAT / VOPT Sense Module VSENSE VDDA 16 Bit -ADC Low Pass Filter ADC And AGND egulator Control ADCGND ISENSEH Current Sense Module (PGA with auto Gain Control) ISENSEL Internal Chip Temp Sense 16 Bit VTEMP with optional external input ADC ake Up Control Module (with Current Threshold and Current Averaging) PTB3 (L0) 4 Channel Timer PTB2 GPIO PTB1 SCI LIN PTB0 Physical Layer GNDSUB GNDSUB GNDSUB GNDSUB LGND LIN Internal Bus TEST_A TCLK Test Interface eset Control Module Trimming / Calibration Interrupt Control Module Die To Die Interface Cascaded Voltage egulators VDDH = 2.5V (D2D Buffer) VDDL = 2.5V (Internal Digital) VDDX = 5V (MCU Core) BIAS VSUP ESET_A Analog Die DGND D2DCLK D2DDAT7 D2DDAT3 D2DDAT6 D2DDAT2 D2DDAT5 D2DINT VDDL VDDX Single-ire Background Debug Module COP atchdog Periodic Interrupt Interrupt Module Debug Module include 64 byte Trace Buffer AM D2DI MCU Die VDDD2D VSSD2D ESET BKGD/MODC eset Generation and Test Entry M68HCS12 CPU ALU CPU egister Flash 128k Bytes with ECC Dataflash 4k Bytes with ECC AM 6k Byte SS SCK MOSI SPI PTA DDA MISO PA7 PTE1 / XTAL TEST PA5 PA4 PA3 D2DDAT1 PA2 D2DDAT4 D2DDAT0 VDDH PC0 PD7 PD3 PD6 PD2 PD5 PD1 PD4 PD0 PC1 Internal Bus VEG 1.8V Core 2.7V Flash VDDX VSSX PA6 PTE0 / EXTAL PA1 PA0 16 Bit -ADC PTE Amplitude Controlled [1:0] Low Power Pierce Osc. PLL with Freq. Modulation option OSC Clock Monitor Figure 2. Sample Block Diagram Freescale Semiconductor 5

6 Pin Assignment 3 Pin Assignment PA7 BKGD/MODC ESET ESET_A DGND TEST_A VDDL GNDSUB TCLK PTB0 PTB1 PTB PA PTB3 / L0 PTE0/EXTAL 2 35 VOPT PTE1/XTAL 3 34 VSENSE TEST 4 33 ADCGND PA ISENSEH PA4 PA3/SS 6 7 EP ISENSEL GNDSUB PA2/SCK 8 29 TSUP PA1/MOSI 9 28 VTEMP PA0/MISO AGND VSSX VDDA VDDX NC NC (VFUSE) LGND LIN VSUP GNDSUB VDDH DGND VDDX GNDSUB NC VDDD2D VSSD2D 3.1 MM912_637 Pin Description Figure 3. MM912_637 Pin Connections The following table gives a brief description of all available pins on the MM912_637 device. efer to the highlighted chapter for detailed information Table 4. MM912_637 Pin Description Pin # Pin Name Formal Name Description 1 PA6 2 PE0/EXTAL MCU PA6 MCU Oscillator General purpose port A input or output pin 6. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". EXTAL in one of the optional crystal/resonator drivers and external clock pins, and the PE0 port may be used as a general purpose I/O. On reset, all the device clocks are derived from the internal reference clock. See Section 5.22, S12 Clock, eset, and Power Management Unit (S12CPMU)". Freescale Semiconductor 6

7 Pin Assignment MCU Oscillator XTAL is one of the optional crystal/resonator drivers and external clock pins, and 3 PE1/XTAL the PE1 port may be used as a general purpose I/O. On reset all the device clocks are derived from the internal reference clock. See Section 5.22, S12 Clock, eset, and Power Management Unit (S12CPMU)". 4 TEST MCU Test This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must be tied to VSSX in user mode. 5 PA5 MCU PA5 General purpose port A input or output pin 5. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". 6 PA4 MCU PA4 General purpose port A input or output pin 4. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". MCU PA3 / SS General purpose port A input or output pin 3, shared with the SS signal of the 7 PA3 integrated SPI interface. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". MCU PA2 / SCK General purpose port A input or output pin 2, shared with the SCLK signal of the 8 PA2 integrated SPI interface. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". MCU PA1 / MOSI General purpose port A input or output pin 1, shared with the MOSI signal of the 9 PA1 integrated SPI interface. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". MCU PA0 / MISO General purpose port A input or output pin 0, shared with the MISO signal of the 10 PA0 integrated SPI interface. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". 11 VSSX MCU 5.0 V Ground External ground for the MCU - VDDX return path. 12 VDDX MCU 5.0 V Supply 5.0 V MCU power supply. MCU core- (internal 1.8 V regulator) and flash (internal 2.7 V regulator) supply. 13 VSSD2D MCU 2.5 V Ground External ground for the MCU - VDDD2D return path. 14 VDDD2D MCU 2.5 V Supply 2.5 V MCU power supply. Die to die buffer supply. 15 NC Not connected This pin must be grounded in the application. 16 GNDSUB Substrate Ground Substrate ground connection to improve EMC behavior. 17 VDDX 18 DGND 19 VDDH Voltage egulator Output 5.0 V 5.0 V main voltage regulator output pin. An external capacitor (C VDDX ) is needed. See Section 5.2, Analog Die - Power, Clock and esets - PC". Digital Ground This pin is the device digital ground connection. See Section 5.2, Analog Die - Power, Clock and esets - PC". Voltage egulator Output 2.5 V 2.5 V high power main voltage regulator output pin to be connected with the VDDD2D MCU pin. An external capacitor (C VDDH ) is needed. See Section 5.2, Analog Die - Power, Clock and esets - PC". 20 GNDSUB Substrate Ground Substrate ground connection to improve EMC behavior. 21 VSUP Power Supply This pin is the device power supply pin. A reverse battery protection diode is required. See Section 5.2, Analog Die - Power, Clock and esets - PC". 22 LIN LIN Bus I/O This pin represents the single-wire bus transmitter and receiver. See Section 5.11, LIN". 23 LGND LIN Ground Pin This pin is the device LIN ground connection. See Section 5.2, Analog Die - Power, Clock and esets - PC". 24 NC Not connected (reserved) This pin must be grounded in the application. 25 NC Not connected This pin must be grounded in the application. 26 VDDA 27 AGND Analog Voltage egulator Output Analog Ground Table 4. MM912_637 Pin Description Pin # Pin Name Formal Name Description Low power analog voltage regulator output pin, permanently supplies the analog front end. An external capacitor (C VDDA ) is needed. See Section 5.2, Analog Die - Power, Clock and esets - PC". This pin is the device analog voltage regulator and LP oscillator ground connection. See Section 5.2, Analog Die - Power, Clock and esets - PC". Freescale Semiconductor 7

8 Pin Assignment 28 VTEMP 29 TSUP Temperature Sensor Input Temperature Sensor Supply Output External temperature sensor input. See Section 5.6, Temperature Measurement - TSENSE". Supply for the external temperature sensor. TSUP frequency compensation option to allow capacitor CTSUP. See Section 5.6, Temperature Measurement - TSENSE". 30 GNDSUB Substrate Ground Substrate ground connection to improve EMC behavior. 31 ISENSEL 32 ISENSEH 33 ADCGND 34 VSENSE 35 VOPT 36 PTB3 / L0 37 PTB2 38 PTB1 39 PTB0 Current Sense L Current Sense H Analog Digital Converter Ground Voltage Sense Current sense input Low. This pin is used in combination with ISENSEH to measure the voltage drop across a shunt resistor. See Section 5.4, Current Measurement - ISENSE". Current sense input high. This pin is used in combination with ISENSEL to measure the voltage drop across a shunt resistor. See Section 5.4, Current Measurement - ISENSE". Analog digital converter ground connection. See Section 5.2, Analog Die - Power, Clock and esets - PC". Precision battery voltage measurement input. This pin can be connected directly to the battery line for voltage measurements. The voltage preset at this input is scaled down by an internal voltage divider. The pin is self protected against reverse battery connections. An external resistor ( VSENSE ) is needed for protection. See Section 5.5, Voltage Measurement - VSENSE". Optional Voltage Sense Optional voltage measurement input. See Section 5.5, Voltage Measurement - VSENSE". General Purpose Input 3 - High Voltage Input 0 General Purpose I/O 2 General Purpose I/O 1 General Purpose I/O 0 Table 4. MM912_637 Pin Description Pin # Pin Name Formal Name Description This is the high voltage general purpose input pin 3, based on VDDX with the following shared functions: Internal clamping structure to operate as a high voltage input (L0). hen used as high voltage input, a series resistor (L0) and capacitor to GND (C L0 ) must be used to protect against automotive transients, when used to connect outside the PCB. 5.0 V (VDDX) digital port input Selectable internal pull-down resistor Selectable wake-up input during low power mode. Selectable timer channel input Selectable connection to the LIN / SCI (Input only) See Section 5.10, General Purpose I/O - GPIO". This is the general purpose I/O pin 2 based on VDDX with the following shared functions: Bidirectional 5.0 V (VDDX) digital port I/O Selectable internal pull-up resistor Selectable timer channel input/output Selectable connection to the LIN / SCI See Section 5.10, General Purpose I/O - GPIO". This is the general purpose I/O pin 1, based on VDDX with the following shared functions: Bidirectional 5.0 V (VDDX) digital port I/O Selectable internal pull-up resistor Selectable timer channel input/output Selectable connection to the LIN / SCI See Section 5.10, General Purpose I/O - GPIO". This is the general purpose I/O pin 0 based on VDDX with the following shared functions: Bidirectional 5.0 V (VDDX) digital port I/O Selectable internal pull-up resistor Selectable timer channel input/output Selectable connection to the LIN / SCI See Section 5.10, General Purpose I/O - GPIO". Freescale Semiconductor 8

9 Pin Assignment Test Clock Input Test mode clock input pin for Test mode only. This pin must be grounded in user 40 TCLK mode. 41 GNDSUB Substrate Ground Substrate ground connection to improve EMC behavior. 42 VDDL 43 TEST_A 44 DGND 45 ESET_A 46 ESET 47 BKGD 48 PA7 Low Power Voltage egulator Output Test Mode 2.5 V low power voltage regulator output pin. See Section 5.2, Analog Die - Power, Clock and esets - PC". Analog die Test mode pin for Test mode only. This pin must be grounded in user mode. Digital Ground This pin is the device digital ground connection. See Section 5.2, Analog Die - Power, Clock and esets - PC". eset I/O MCU eset MCU Background Debug and Mode MCU PA7 Table 4. MM912_637 Pin Description Pin # Pin Name Formal Name Description eset output pin of the analog die. Active low signal with internal pull-up. V DDX based. See Section 5.2, Analog Die - Power, Clock and esets - PC". Bidirectional reset I/O pin of the MCU die. Active low signal with internal pull-up. V DDX based. See Section 5.2, Analog Die - Power, Clock and esets - PC". The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of ESET. The BKGD pin has a pull-up device. See Section 5.19, MCU - Debug Module (S12SDBG)". General purpose port A input or output pin 7. See Section 5.16, MCU - Port Integration Module (9S12I128PIMV1)". Freescale Semiconductor 9

10 Pin Assignment 3.2 ecommended External Components Figure 4 and Table 5 list the required / recommended / optional external components for the application. Battery Plus Pole D1 VOPT VSENSE CVBAT Battery Minus Pole ISENSEL CISENSEL VOPT ISENSEL VSENSE VSUP VDDL VDDD2D VDDH VDDX VDDX SHUNT ISENSEH CISENSEH CISENSEHL ISENSEH DGND VSSD2D CVDDX CVDDH Chassis Ground VSSX VTEMP LIN CLIN LIN LGND PTB3 / L0 GNDSUB GNDSUB GNDSUB GNDSUB Exposed Pad (EP) TSUP VDDA AGND ADCGND VTEMP CVDDA CTSUP L0 CL0 Note: Module GND connected to Battery Minus or Chassis Ground based on configuration. Figure 4. equired / ecommended External Components Table 5. equired / ecommended External Components Name Description Value Connection Comment D 1 everse Battery Diode n.a. VSUP-VBAT C VBAT Battery Blocking Capacitor 4.7 µf/100 nf VSUP-GND Ceramic VSENSE VSENSE Current Limitation 2.2 k VSENSE-VBAT VOPT VOPT Current Limitation 2.2 k VOPT-signal optional (1) SHUNT Current Shunt esistor 100 µ ISENSEH-ISENSEL ISENSEL EMC esistor 500 max ISENSEH EMC esistor 500 max C ISENSEL EMC Capacitor TBD C ISENSEHL EMC Capacitor TBD C ISENSEH EMC Capacitor TBD select for best EMC performance select for best EMC performance select for best EMC performance select for best EMC performance select for best EMC performance Freescale Semiconductor 10

11 Pin Assignment Table 5. equired / ecommended External Components Name Description Value Connection Comment C VDDH Blocking Capacitor 1.0 µf VDDH-GND C VDDX Blocking Capacitor 220 nf VDDX-GND C VDDA Blocking Capacitor 47 nf VDDA-GND C VDDL Blocking Capacitor n.a. VDDL-GND not required C LIN LIN Bus Filter n.a. LIN-LGND not required L0 PTB3 / L0 Current Limitation 47 k L0 C L0 PTB3 / L0 ESD Protection 47 nf L0-GND C TSUP Blocking Capacitor 220 pf TSUP-GND not required (2) VTEMP VTEMP Current Limitation 20 k VTEMP-signal optional (1) 1.equired if extended EMC protection is needed 2.If an external temperature sensor is used, EMC compliance may require the addition of CTSUP. In this case the ECAP bit must be set to ensure the stability of the TSUP power supply circuit. See Section , Block Diagram". 3.3 Pin Structure Table 6 documents the individual pin characteristic. Table 6. Pin Type / Structure Pin # Pin Name Alternative Pin Function Power Supply Structure 1 PA6 n.a. VDDX n.a. 2 PE0 EXTAL VDDX PUPEE / OSCPINS_EN 3 PE1 XTAL VDDX PUPEE / OSCPINS_EN 4 TEST n.a. n.a. n.a. 5 PA5 n.a. VDDX n.a. 6 PA4 n.a. VDDX n.a. 7 PA3 SS VDDX n.a. 8 PA2 SCK VDDX n.a. 9 PA1 MOSI VDDX n.a. 10 PA0 MISO VDDX n.a. 11 VSSX n.a. GND 12 VDDX n.a. 13 VSSD2D n.a. GND 14 VDDD2D n.a. 15 NC n.a. 16 GNDSUB n.a. GND 17 VDDX n.a. VDDX 18 DGND n.a. GND B2B-Diode to GNDSUB 19 VDDH n.a. VDDH Negative Clamp Diode, Dynamic ESD (transient protection) 20 GNDSUB n.a. GND GNDSUB 21 VSUP n.a. VSUP Negative Clamp Diode, >42 V ESD 22 LIN n.a. VSUP No Negative Clamping Diode (-40 V), >42 V ESD 23 LGND n.a. GND B2B-Diode to GNDSUB Freescale Semiconductor 11

12 Pin Assignment Table 6. Pin Type / Structure Pin # Pin Name Alternative Pin Function Power Supply Structure 24 NC n.a. n.a. Negative Clamp Diode, >15 V ESD 25 NC n.a. n.a. n.a. 26 VDDA n.a. VDDA Negative Clamp Diode, Dynamic ESD (transient protection) 27 AGND n.a. GND B2B-Diode to GNDSUB 28 VTEMP VDDA Negative Clamp Diode, >6.0 V ESD 29 TSUP TSUP Negative Clamp Diode, Dynamic ESD (transient protection) 30 GNDSUB GND GND 31 ISENSEL n.a. Negative Clamp Diode, 2nd Clamp Diode to VDDA 32 ISENSEH n.a. Negative Clamp Diode, 2nd Clamp Diode to VDDA 33 ADCGND GND B2B-Diode to GNDSUB 34 VSENSE n.a. No Negative Clamping Diode (-40 V), >42 V ESD 35 VOPT n.a. No Negative Clamping Diode (-40 V), >42 V ESD 36 PTB3 / L0 VDDX Negative Clamp Diode, >6.0 V ESD 37 PTB2 VDDX Negative Clamp, Dynamic 5.5 V ESD 38 PTB1 VDDX Negative Clamp, Dynamic 5.5 V ESD 39 PTB0 VDDX Negative Clamp, Dynamic 5.5 V ESD 40 TCLK VDDX Negative Clamp, Dynamic 5.5 V ESD 41 GNDSUB GND GND 42 VDDL VDDL Negative Clamp Diode, Dynamic ESD (transient protection) 43 TEST_A VDDX Negative Clamp, positive 10 V Clamp 44 DGND GND B2B-Diode to GNDSUB 45 ESET_A VDDX Negative Clamp, positive 10 V Clamp 46 ESET VDDX Pull-up 47 BKGD MODC VDDX BKPUE 48 PA7 VDDX n.a. Freescale Semiconductor 12

13 Electrical Characteristics 4 Electrical Characteristics 4.1 General This section contains electrical information for the microcontroller, as well as the MM912_637 analog die. 4.2 Absolute Maximum atings Absolute maximum ratings are stress ratings only. A functional operation under or outside these maximums is not guaranteed. Stress beyond these limits may affect the reliability, or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. eliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground, unless otherwise noted. Table 7. Absolute Maximum Electrical atings - Analog Die atings Symbol Value Unit VSUP pin voltage V VSUP -0.3 to 42 V VSENSE pin voltage (3) V VSENSE -16 to 42 V VOPT pin voltage V VOPT -16 to 42 V VTEMP pin voltage V VTEMP -0.3 to V DDA V ISENSEH and ISENSEL pin voltage V ISENSE -0.5 to V DDA V ISENSEH and ISENSEL pin current I ISENSE -1 to 1 ma LIN pin voltage V BUS -33 to 42 V LIN pin current (internally limited) I BUSLIM on page 18 ma L0 pin voltage with PTB3 V PTB3-0.3 to 42 max. V Input / Output pins PTB[0:2] voltage V PTB to V DDX +0.5 V Pin voltage at VDDX V DDX -0.3 to 5.75 V Pin voltage at VDDH V DDH -0.3 to 2.75 V VDDH output current I VDDH internally limited A VDDX output current I VDDX internally limited A TCLK pin voltage V TCLK -0.3 to V DDX +0.5 V ESET_A pin voltage V IN -0.3 to V DDX +0.5 V 3.It has to be assured by the application circuit that these limits will not be exceeded, e.g. by ISO pulse 1. Table 8. Maximum Electrical atings - MCU Die atings Symbol Value Unit 5.0 V supply voltage V DDX -0.3 to 6.0 V 2.5 V supply voltage V DDD2D -0.3 to 3.6 V Digital I/O input voltage (PTA0...7) V IN -0.3 to 6.0 V EXTAL, XTAL V IN -0.3 to 2.16 V Instantaneous maximum current single pin limit for all digital I/O pins (4) I D -25 to 25 ma Instantaneous maximum current single pin limit for EXTAL, XTAL I DL -25 to 25 ma 4.All digital I/O pins are internally clamped to V SSX and V DDX. Freescale Semiconductor 13

14 Electrical Characteristics 4.3 Operating Conditions This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted. 4.4 Supply Currents This section describes the current consumption characteristics of the device, as well as the conditions for the measurements Measurement Conditions Table 9. Maximum Thermal atings atings Symbol Value Unit Storage temperature T STG -55 to 150 C Package thermal resistance (5) JA 25 typ. C/ 5. JA value is derived using a JEDEC 2s2p test board Table 10. Operating Conditions atings Symbol Value Unit Functional operating supply voltage - Device is fully functional. All features V SUP 3.5 to 28 V are operating. Extended range for AM Content is guaranteed. Other device functionary is V SUPL 2.5 to 3.5 V limited. ith cranking mode enabled (seesection , Low Voltage Operation - Cranking Mode Device Option"). Functional operating VSENSE voltage (6) V SENSE 0 to 28 V Functional operating VOPT voltage V OPT 0 to 28 V External temperature sense input - VTEMP V TEMP 0 to 1.25 V LIN output voltage range V VSUP_LIN 7 to 18 V ISENSEH / ISENSEL terminal voltage V ISENSE -0.5 to 0.5 V MCU 5.0 V supply voltage V DDX 3.13 to 5.5 V MCU 2.5 V supply voltage V DDD2D 2.25 to 3.6 V MCU oscillator f OSC 4 to 16 MHz MCU bus frequency f BUS max MHz Operating ambient temperature T A -40 to 125 C Operating junction temperature - analog die T J_A -40 to 150 C Operating junction temperature - MCU die T J_M -40 to 150 C 6.Values V SENSE > 28 V are flagged in the VSENSE All measurements are without output loads. The currents are measured in MCU special single chip mode, and the CPU code is executed from AM, unless otherwise noted. For un and ait current measurements, PLL is on and the reference clock is the IC1M, trimmed to MHz. The bus frequency is MHz and the CPU frequency is MHz. Table 11 and Table 12 show the configuration of the CPMU module for un, ait, and Stop current measurements. Table 13 shows the configuration of the peripherals for run current measurements Freescale Semiconductor 14

15 Electrical Characteristics Table 11. CPUM Configuration for un/ait and Full Stop Current Measurement CPMU EGISTE CPMUSYN CPMUPOSTDIV CPMUCLKS CPMUOSC Bit settings/conditions VCOFQ[1:0]=01,SYNDIV[5:0] = MHz POSTDIV[4:0]=0, PLLSEL=1 OSCE=0, eference clock for PLL is f EF =f IC1M trimmed to MHz Table 12. CPMU Configuration for Pseudo Stop Current Measurements CPMU EGISTE CPMUCLKS CPMUOSC CPMUTI CPMUCOP Bit settings/conditions PLLSEL=0, PSTP=1, PE=PCE=TIOSCSEL=COPOSCSEL=1 OSCE=1, External square wave on EXTAL f EXTAL =16 MHz, V IH = 1.8 V, V IL =0 V TDEC=0, T[6:4]=111, T[3:0]=1111; COP=1, C[2:0]=111 Table 13. MCU Peripheral Configurations for un Supply Current Measurements Peripheral Configuration SPI D2DI configured to master mode, continuously transmit data (0x55 or 0xAA) at 1.0 Mbit/s continuously transmit data (0x55 or 0xAA) COP COP atchdog ate 2 24 TI DBG enabled, TI Control egister (TICTL) set to $FF The module is enabled and the comparators are configured to trigger in outside range. The range covers all the code executed by the core. Table 14. Analog Die Configurations for Normal Mode Supply Current Measurements Peripheral D2D LIN TIME LTC Channels Configuration maximum frequency enabled, recessive state enabled enabled Current, voltage, and temperature measurement enabled, LPF and Auto Gain enabled Freescale Semiconductor 15

16 Electrical Characteristics Table 15. Supply Currents (7) atings Symbol Min Typ. (8) Max Unit MM912_637 COMBINED CONSUMPTION Normal mode current both dice. I UN ma ANALOG DIE CONTIBUTION - EXCLUDING MCU AND EXTENAL LOAD CUENT, (3.5 V V SUP 28 V; -40 C T A 125 C) Normal mode current measured at V SUP I NOMAL ma Stop mode current measured at V SUP Continuous base current (9) Stop current during cranking mode Current adder during current trigger event - (typ. 10 ms duration (10), temperature measurement = OFF) I STOP µa Sleep mode measured at V SUP Continuous base current (9) Current adder during current trigger event - (typ. 10 ms duration (10), temperature measurement = OFF) MCU DIE CONTIBUTION, V DDX = 5.5 V un Current, T A 125 C I UN ma I STP ait current, T A 125 C I AIT ma Stop current I STP T A = 125 C T A = 25 C µa T A = -40 C Pseudo stop current, TI and COP enabled T A = 150 C T A = 25 C µa T A = -40 C See Table 11, Table 12, Table 13, and Table 14 for conditions. Currents measured in Test mode with external loads (100 pf) and the external clock at 64 MHz. 8.Typical values noted reflect the approximate parameter mean at T A = 25 C. 9.From V SUP 6.0 to 28 V 10.Duration based on channel configuration. 10ms typical for Decimation Factor = 512, Chopper = ON. 4.5 Static Electrical Characteristics All characteristics noted under conditions 3.5 V V SUP 28 V, -40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T A = 25 C under nominal conditions, unless otherwise noted. I SLEEP µa Static Electrical Characteristics Analog Die Table 16. Static Electrical Characteristics - Power Supply atings Symbol Min Typ Max Unit Low Voltage eset L (PO) Assert (measured on VDDL) Cranking Mode Disabled Low Voltage eset L (PO) Deassert (measured on VDDL) Cranking Mode Disabled V POL V POH V V Freescale Semiconductor 16

17 Electrical Characteristics Low Voltage eset L (PO) Assert (measured on VDDL) Table 16. Static Electrical Characteristics - Power Supply atings Symbol Min Typ Max Unit Cranking Mode Enabled (11) V POCL Low Voltage eset A (LVA) Assert (measured on VDDA) V LVAL V Low Voltage eset A (LVA) Deassert (measured on VDDA) V LVAH V Low Voltage eset X (LVX) Assert (measured on VDDX) V LVXL V Low Voltage eset X (LVX) Deassert (measured on VDDX) V LVXH V Low Voltage eset H (LVH) Assert (measured on VDDH) V LVHL V Low Voltage eset H (LVH) Deassert (measured on VDDH) V LVHH V Under-voltage Interrupt (UVI) Assert (measured on VSUP), Cranking Mode Disabled V UVIL V Under-voltage Interrupt (UVI) Deassert (measured on VSUP), Cranking Mode Disabled V UVIH V Under-voltage Cranking Interrupt (UVI) Assert (measured on VSUP) Cranking Mode Enabled V UVCIL V Under-voltage Cranking Interrupt (UVI) Deassert (measured on VSUP) Cranking Mode Enabled V UVCIH V VSENSE/VOPT High Voltage arning Threshold Assert (12) V TH 28 V 11.Deassert with Cranking off = V POH V < V SUP < 28 V, Digital Threshold at the end of channel chain (incl. compensation) V Table 17. Static Electrical Characteristics - esets atings Symbol Min Typ Max Unit Low-state Output Voltage I OUT = 2.0 ma V OL 0.8 V Pull-up esistor PU kohm Low-state Input Voltage V IL 0.3V DDX V High-state Input Voltage V IH 0.7V DDX V eset elease Voltage (VDDX) V STV V ESET_A pin Current Limitation I LIMST 10 ma Freescale Semiconductor 17

18 Electrical Characteristics Analog Voltage egulator - VDDA (13) Table 18. Static Electrical Characteristics - Voltage egulator Outputs atings Symbol Min Typ Max Unit Output Voltage 1.0 ma I VDDA 1.5 ma V DDA V Output Current Limitation I VDDA 10 ma Low Power Digital Voltage egulator - VDDL (13) Output Voltage V DDL V High Power Digital Voltage egulator - VDDH (14) Output Voltage 1.0 ma I VDDH 30 ma V DDH V Output Current Limitation I VDDH 65 ma 5.0 V Voltage egulator - VDDX (14) Output Voltage 1.0 ma I VDDX 30 ma V DDX V Output Current Limitation I VDDX ma 13.No additional current must be taken from those outputs. 14.The specified current ranges does include the current for the MCU die. No external loads recommended. Table 19. Static Electrical Characteristics - LIN Physical Layer Interface - LIN atings Symbol Min Typ Max Unit Current Limitation for Driver dominant state. V BUS = 18 V I BUSLIM ma Input Leakage Current at the eceiver incl. Pull-up esistor SLAVE ; Driver OFF; V BUS = 0 V; V BAT = 12 V I BUS_PAS_DOM -1.0 ma Input Leakage Current at the eceiver incl. Pull-up esistor SLAVE ; Driver OFF; 8.0 V V BAT 18 V; 8.0 V V BUS 18 V; V BUS V BAT I BUS_PAS_EC 20 µa Input Leakage Current; GND Disconnected; GND DEVICE = V SUP ; 0 < V BUS < 18 V; V BAT = 12 V I BUS_NO_GND ma Input Leakage Current; V BAT disconnected; V SUP_DEVICE = GND; 0 < V BUS < 18 V I BUS_NO_BAT 100 µa eceiver Input Voltage; eceiver Dominant State V BUSDOM 0.4 V SUP eceiver Input Voltage; eceiver ecessive State V BUSEC 0.6 V SUP eceiver Threshold Center (V TH_DOM + V TH_EC )/2 V BUS_CNT V SUP eceiver Threshold Hysteresis (V TH_EC - V TH_DOM ) V BUS_HYS V SUP Voltage Drop at the serial Diode D SE_INT V LIN Pull-up esistor SLAVE kohm Low Level Output Voltage, I BUS =40 ma V DOM 0.3 V SUP High Level Output Voltage, I BUS =-10 µa, L =33 kohm V EC VSUP-1 V J2602 Detection Deassert Threshold for VSUP level V J2602H V J2602 Detection Assert Threshold for VSUP level V J2602L V J2602 Detection Hysteresis V J2602HYS mv BUS ake-up Threshold V LINUP V Freescale Semiconductor 18

19 Electrical Characteristics Table 20. Static Electrical Characteristics - High Voltage Input - PTB3 / L0 atings Symbol Min Typ Max Unit ake-up Threshold - ising Edge V TH V Input High Voltage (digital Input) V IH 0.7V DDX V DDX +0.3 V Input Low Voltage (digital Input) V IL V SS V DDX V Input Hysteresis V HYS mv Internal Clamp Voltage V L0CLMP V Input Current PTB3 / L0 (V IN = 42 V; L0 =47 kohm) I IN 1.1 ma Internal pull-down resistance (15) PD kohm PTB3 / L0 Series esistor PTB kohm PTB3 / L0 Capacitor C L nf 15.Disabled by default. Table 21. Static Electrical Characteristics - General Purpose I/O - PTB[0...2] atings Symbol Min Typ Max Unit Input High Voltage V IH 0.7V DDX V DDX +0.3 V Input Low Voltage V IL V SS V DDX V Input Hysteresis V HYS mv Input Leakage Current (pins in high-impedance input mode) (V IN = V DDX or V SSX ) I IN µa Output High Voltage (pins in output mode) Full drive I OH = 5.0 ma V OH V DDX -0.8 V Output Low Voltage (pins in output mode) Full drive I OL = 5.0 ma V OL 0.8 V Internal Pull-up esistance (V IH min. > Input voltage > V IL max) (16) PUL kohm Input Capacitance C IN 6.0 pf Maximum Current All PTB Combined (17) I BMAX ma Output Drive strength at 10 MHz C OUT 100 pf 16.Disabled by default. 17.Overall VDD egulator capability to be considered. Freescale Semiconductor 19

20 Electrical Characteristics Table 22. Static Electrical Characteristics - Current Sense Module (18) atings Symbol Min Typ Max Unit Gain Error (19), (20) with temperature based gain compensation adjustment with default gain compensation I GAINE -0.5 Offset Error (21), (22) I OFFSETE 0.5 µv esolution I ES 0.1 µv ISENSEH, ISENSEL terminal voltage differential signal voltage range Differential Leakage Current: differential voltage between ISENSEH/ ISENSEL, 200 mv -1.0 V INC V IND / % mv I SENSE_DLC na ake-up Current Threshold esolution I ESAKE 0.2 µv esistor Threshold for OPEN Detection OPEN MOhm V V SUP 28 V, after applying default trimming values - see Section 6, MM912_637 - Trimming". 19.Gain Compensation adjustment on calibration request interrupt with TCALSTEP %, including lifetime drift for gain 256 and Chopper Mode = ON, Gain with automatic gain control enabled 22.Parameter not tested. Guaranteed by design and characterization Gain Error (24) 18 V V IN 28 V 3.5 V V IN 18 V 3.5 V V IN 5.0 V (25) 5.0 V V IN 18 V (25),(27) Table 23. Static Electrical Characteristics - Voltage Sense Module (23) atings Symbol Min Typ Max Unit V GAINE -0.5 Offset Error (26),(28) V OFFSETE mv esolution with VSENSE = 2.2 kohm V ES 0.5 mv V V SUP 28 V, after applying default trimming values - see Section 6, MM912_637 - Trimming". 24.Including resistor mismatch drift 25.Gain Compensation adjustment on calibration request interrupt with TCALSTEP 26.Chopper Mode = ON %, including lifetime drift 28.Parameter not tested. Guaranteed by design and characterization % Table 24. Static Electrical Characteristics - Temperature Sense Module (29) atings Symbol Min Typ Max Unit Measurement ange T ANGE C Accuracy T ACC -40 C T A 60 C (30) -40 C T A 50 C K esolution T ES 8.0 mk TSUP Voltage Output, 10 µa I TSUP 100 µa V TSUP V TSUP Capacitor with ECAP = 1 C TSUP pf Freescale Semiconductor 20

21 Table 24. Static Electrical Characteristics - Temperature Sense Module (29) Electrical Characteristics atings Symbol Min Typ Max Unit Max Calibration equest Interrupt Temperature Step T CALSTEP K V V SUP 28 V, after applying default trimming values - see Section 6, MM912_637 - Trimming". 30.Temperature not tested in production. Guaranteed by design and characterization Static Electrical Characteristics MCU Die Table 25. Static Electrical Characteristics - MCU atings Symbol Min Typ Max Unit Power On eset Assert (measured on VDDX) V POA V Power On eset Deassert (measured on VDDX) V POD V Low Voltage eset Assert (measured on VDDD2D) V LVA V Low Voltage eset Deassert (measured on VDDD2D) V LVD V Low Voltage Interrupt Assert (measured on VDDD2D) V LVIA V Low Voltage Interrupt Deassert (measured on VDDD2D) V LVID V Table 26. Static Electrical Characteristics - Oscillator (OSCLCP) atings Symbol Min Typ Max Unit Startup Current i OSC 100 A Input Capacitance (EXTAL, XTAL pins) C IN 7.0 pf EXTAL Pin Input Hysteresis V HYS,EXTAL 180 mv EXTAL Pin oscillation amplitude (loop controlled Pierce) V PP,EXTAL 0.9 V Table V I/O Characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins (4.5 V < V DDX < 5.5 V; T J : 40 C to +150 C, unless otherwise noted) atings Symbol Min Typ Max Unit Input High Voltage V IH 0.65*V DDX V Input High Voltage V IH V DDX +0.3 V Input Low Voltage V IL 0.35*V DDX V Input Low Voltage V IL V SSX 0.3 V Input Hysteresis VHYS 250 mv Input Leakage Current (pins in high-impedance input mode) (31) VIN = VDDX or VSSX I IN A Freescale Semiconductor 21

22 Input Leakage Current (pins in high-impedance input mode) (32) VIN = VDDX or VSSX T A = 40 C T A = 25 C T A = 70 C T A = 85 C T A = 105 C T A = 110 C T A = 120 C T A = 125 C T A = 130 C T A = 150 C Electrical Characteristics Output High Voltage (pins in output mode), I OH = 4.0 ma V OH V DDX 0.8 V Output Low Voltage (pins in output mode), IOL = 4.0 ma V OL 0.8 V Internal Pull-up Current, V IH min > input voltage > V IL max I PUL A Internal Pull-down Current, V IH min > input voltage > V IL max I PDH A Input Capacitance C in 7 pf Injection Current (33) Table V I/O Characteristics for all I/O pins except EXTAL, XTAL, TEST, D2DI, and supply pins (4.5 V < V DDX < 5.5 V; T J : 40 C to +150 C, unless otherwise noted) Single pin limit Total device Limit, sum of all injected currents atings Symbol Min Typ Max Unit I IN I ICS 2.5 I ICP Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the temperature range from 50 C to 125 C. 32.Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8.0 C to 12 C in the temperature range from 50 C to 125 C. 33.efer to Section , Current Injection" for more details na ma Current Injection The power supply must maintain regulation within the V DDX operating range during instantaneous and operating maximum current conditions. If positive injection current (V IN > V DDX ) is greater than I DDX, the injection current may flow out of VDDX and could result in the external power supply going out of regulation. Ensure that the external V DDX load will shunt current greater than the maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if the clock rate is very low, which would reduce overall power consumption. Freescale Semiconductor 22

23 Electrical Characteristics 4.6 Dynamic Electrical Characteristics Dynamic characteristics noted under conditions 3.5 V V SUP 28 V, -40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T A = 25 C under nominal conditions, unless otherwise noted Dynamic Electrical Characteristics Analog Die Table 28. Dynamic Electrical Characteristics - Modes of Operation atings Symbol Min Typ Max Unit Low Power Oscillator Frequency f OSCL 512 khz Low Power Oscillator Tolerance over full temperature range f TOL_A Analog Option % Analog Option Low Power Oscillator Tolerance - synchronized ALFCLK (34) f TOLC_A ALF clock cycle = 1.0 ms f TOL -0.2 f TOL +0.2 ALF clock cycle = 2.0 ms f TOL -0.1 f TOL +0.1 % f TOL ALF clock cycle = 4.0 ms f TOL f TOL ALF clock cycle = 8.0 ms f TOL f TOL Parameter not tested. Guaranteed by design and characterization. Table 29. Dynamic Electrical Characteristics - Die to Die Interface - D2D atings Symbol Min Typ Max Unit Operating Frequency (D2DCLK, D2D[0:3]) f D2D MHz Table 30. Dynamic Electrical Characteristics - esets atings Symbol Min Typ Max Unit eset Deglitch Filter Time t STDF µs eset elease Time for D and H t STT 32 µs Table 31. Dynamic Electrical Characteristics - ake-up / Cyclic Sense atings Symbol Min Typ Max Unit Cyclic ake-up Time (35) t AKEUP ALFCLK TIM4CH ms Cyclic Current Measurement Step idth (36) t STEP ALFCLK 16Bit ms 35.Cyclic wake-up on ALFCLK clock based 16 Bit TIME with maximum 128x prescaler (min 1x) 36.Cyclic wake-up on ALFCLK clock with 16 Bit programmable counter Table 32. Dynamic Electrical Characteristics - indow atchdog atings Symbol Min Typ Max Unit Initial Non-window atchdog Timeout t IDTO see Figure 2 ms Freescale Semiconductor 23

24 Electrical Characteristics Table 33. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN atings Symbol Min Typ Max Unit Bus ake-up Deglitcher (Sleep and Stop Mode) t POPL µs Fast Bit ate (Programming Mode) B FAST 100 kbit/s Propagation delay of receiver t X_PD 6.0 µs Symmetry of receiver propagation delay rising edge w.r.t. falling edge t X_SYM µs LIN DIVE KBIT/S; BUS LOAD CONDITIONS (C BUS ; BUS ): 1.0 NF; 1.0 K / 6,8 NF;660 / 10 NF;500 Duty Cycle 1: D1 TH EC(MAX) = x V SUP TH DOM(MAX) = x V SUP 7.0 V V SUP 18 V; t BIT = 50 µs; D1 = t BUS_EC(MIN) /(2 x t BIT ) Duty Cycle 2: D TH EC(MIN) = x V SUP TH DOM(MIN) = x V SUP 7.6 V V SUP 18 V; t Bit = 50 µs D2 = t BUS_EC(MAX) /(2 x t BIT ) LIN DIVE KBIT/S; BUS LOAD CONDITIONS (C BUS ; BUS ): 1.0 NF; 1.0 K / 6,8 NF;660 / 10 NF;500 Duty Cycle 3: D3 TH EC(MAX) = x V SUP TH DOM(MAX) = x V SUP 7.0 V V SUP 18 V; t Bit = 96 µs D3 = t BUS_EC(MIN) /(2 x t BIT ) Duty Cycle 4: TH EC(MIN) = x V SUP TH DOM(MIN) = x V SUP 7.6 V V SUP 18 V; t BIT = 96 µs D4 = t BUS_EC(MAX) /(2 x t BIT ) LIN Transmitter Timing, (V SUP from 7.0 to 18 V) - See Figure 5 Transmitter Symmetry t TAN_SYM < MAX(ttran_sym60%, t TAN_SYM 40%) t TAN_SYM 60% = t TAN_PDF 60% - t TAN_PD 60% t TAN_SYM 40% = t TAN_PDF 40% - t TAN_PD 40% D4 t TAN_SYM µs TX BUS 60% 40% ttran_pdf60% ttran_pdr40% ttran_pdf40% ttran_pdr60% Figure 5. LIN Transmitter Timing Freescale Semiconductor 24

25 Electrical Characteristics Table 34. Dynamic Electrical Characteristics - General Purpose I/O - PTB3 / L0] atings Symbol Min Typ Max Unit ake-up Glitch Filter Time t UPF 20 µs Table 35. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0...2] atings Symbol Min Typ Max Unit GPIO Digital Frequency f PTB 10 MHz Propagation Delay - ising Edge (37) t PDr 20 ns ise Time - ising Edge (37) t ISE 17.5 ns Propagation Delay - Falling Edge (37) t PDf 20 ns ise Time - Falling Edge (37) t FALL 17.5 ns 37.Load PTBx = 100 pf Table 36. Dynamic Electrical Characteristics - Current Sense Module atings Symbol Min Typ Max Unit Frequency Attenuation (38),(39) <100 Hz (f PASS ) db 3.0 >500 Hz (f STOP ) 40 Signal Update ate (40) f IUPDATE khz Signal Path Match with Voltage Channel f IVMATCH 2.0 µs Gain Change Duration (Automatic GCB active) (41) t GC 14 µs 38.Characteristics identical to Voltage Sense Module 39.ith default LPF coefficients 40.After passing decimation filter 41.Parameter not tested. Guaranteed by design and characterization. Table 37. Dynamic Electrical Characteristics - Voltage Sense Module atings Symbol Min Typ Max Unit Frequency attenuation (42),(43) Hz (f PASS ) db >500 Hz (f STOP ) Signal update rate (44) f VUPDATE khz Signal path match with Current Channel (45) f IVMATCH 2.0 µs 42.Characteristics identical to Voltage Sense Module 43.ith default LPF coefficients 44.After passing decimation filter 45.Parameter not tested. Guaranteed by design and characterization. Freescale Semiconductor 25

26 Table 38. Dynamic Electrical Characteristics - Temperature Sense Module Electrical Characteristics atings Symbol Min Typ Max Unit Signal Update ate (46) f TUPDATE khz khz with Chopper Enabled, 4.0 khz with Chopper Disabled (fixed decimeter = 128) Dynamic Electrical Characteristics MCU Die NVM Timing Parameters The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as f NVMOP. The NVM module does not have any means to monitor the frequency, and will not prevent program or erase operations at frequencies above or below the specified minimum. hen attempting to program or erase the NVM module at a lower frequency, a full program or erase transition is not assured. The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing parameters are a function of the bus clock frequency, f NVMBUS. All program and erase times are also a function of the NVM operating frequency, f NVMOP. A summary of key timing parameters can be found in Table Erase Verify All Blocks (Blank Check) (FCMD=0x01) The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify, plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given by: 1 t check = f NVMBUS Erase Verify Block (Blank Check) (FCMD=0x02) The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify, plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: 1 t pcheck = f NVMBUS Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by: 1 t dcheck = f NVMBUS Erase Verify P-Flash Section (FCMD=0x03) The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (N VP ) and is given by: 1 t N VP f NVMBUS ead Once (FCMD=0x04) The maximum read once time is given by: Freescale Semiconductor 26