Specification and Design Guide

Transcription

1 Specification and Design Guide Revision 1.00 May, 2011 Revision Date Comment /20/2009 Pre-release /1/2009 Initial release version /16/2010 Update finger drawings; remove LPC bus /26/2010 Update component height drawing and top side mounting dimensions /2/2010 Define FeaturePak USB and update host connector PCB footprint /22/2010 Update connector list, reset, PCB footprints /11/2010 Update mounting holes, connector PCB footprint, finger dimensions /6/2010 Update mounting holes and drawing /22/2010 Reflect transfer of ownership to FeaturePak Trade Association /12/2010 Corrections to host PCB footprint drawing and description FeaturePak and the FeaturePak logo are trademarks of The FeaturePak Trade Association. Copyright FeaturePak Trade Association FeaturePak Specification and Design Guide Revision 1.00 Page 1 of 22

2 DISCLAIMER THIS SPECIFICATION IS PROVIDED "AS IS" AND WITHOUT ANY WARRANTY OR REPRESENTATION OF ANY KIND, EXPRESS OR IMPLIED. WITHOUT LIMITATION, THERE IS NO WARRANTY OF MERCHANTABILITY, NO WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE, NO WARRANTY OF NON-INFRINGEMENT AND NO REPRESENTATION THAT THE SPECIFICATION OR ANY PRODUCT OR TECHNOLOGY UTILIZING THE SPECIFICATION OR ANY SUBSET OF THE SPECIFICATION WILL BE FREE FROM ANY CLAIMS OF INFRINGEMENT OF ANY INTELLECTUAL PROPERTY, INCLUDING PATENTS, COPYRIGHTS, AND TRADE SECRETS. FURTHER, NO LICENSE, EXPRESS OR IMPLIED BY ESTOPPEL, OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREIN. ALL WARRANTIES ARE EXPRESSLY DISCLAIMED. USER ASSUMES THE FULL RISK OF USING THIS SPECIFICATION, INCLUDING RESPONSIBITY FOR SECURING ANY INTELLECTUAL PROPERTY LICENSES OR RIGHTS WHICH MAY BE NECESSARY TO IMPLEMENT OR BUILD PRODUCTS COMPLYING WITH THIS SPECIFICATION. IN NO EVENT SHALL THE FEATUREPAK TRADE ASSOCIATION BE LIABLE FOR ANY ACTUAL, DIRECT, INDIRECT, PUNITIVE, OR CONSEQUENTIAL DAMAGES ARISING FROM SUCH USE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FeaturePak Specification and Design Guide Revision 1.00 Page 2 of 22

3 CONTENTS 1 Overview Concept and Features System Architecture Example Applications Host Interfaces Minimum Feature Requirements FeaturePak Module Mechanical Drawing PCB Finger Patterns Top side finger pattern Bottom side finger pattern Finger plating Component Keepout Areas Top and Bottom Component Height PCB Thickness Mounting Holes FeaturePak Connector Description Module Height Above Baseboard Connector Suppliers Current Capacity PCB Footprint FeaturePak Connector pinout Overview Pinout Diagrams Functional Descriptions FeaturePak Host Baseboard Design Guidelines Module Mounting Position Mounting Hardware Connector Identification Component Height Limits Under a FeaturePak Module Reset Functions Slot ID Present UART Signals I/O Connector Types I/O Connector Signal Routing FeaturePak Specification and Design Guide Revision 1.00 Page 3 of 22

4 1 OVERVIEW 1.1 Concept and Features FeaturePak I/O modules provide a compact and low-cost method of adding I/O to an embedded CPU or other electronic design. FeaturePak is intended for use as an expansion method in standard off the shelf CPU boards as well as functional blocks in custom boards. All connections to a FeaturePak module, including power, host interface, and I/O are provided through a single low-cost, high-density MXM connector, originally designed for use with notebook computer graphics modules. The use of a single low-cost connector plus gold fingers on the FeaturePak module results in the lowest possible cost for a mezzanine board interconnect solution. The MXM connector provides 230 I/O contacts and is rated for 2.5Gbps operation, fast enough for PCI Express Gen 1 and other high speed serial interfaces. FeaturePak modules are fixed into place with two screws to provide resistance to shock and vibration. Performance has been verified to MIL-STD-202G specifications. FeaturePak modules utilize a 230-pin MXM type connector on the host board for all I/O. The host interface signals are toward the right side of the module (near the orientation slot), and the user I/O signals are on the left side. The connector pinout is different from the MXM graphics standard and other standards, such as Qseven, that use MXM connectors. It includes power, a variety of high-speed and lows-peed serial interfaces, and up to 100 I/O pins. Several pins are reserved for future upgrade of the standard. FeaturePak modules operate on 3.3VDC and may use 5VDC power for auxiliary functions. FeaturePak Specification and Design Guide Revision 1.00 Page 4 of 22

5 1.2 System Architecture The diagram below provides a logical overview of FeaturePak system architecture. FeaturePak Specification and Design Guide Revision 1.00 Page 5 of 22

6 1.3 Example Applications FeaturePak modules simplify the design of embedded computing systems and other electronics by providing off the shelf I/O modules in place of in-house designed I/O circuitry. This helps reduce design effort, project risk, and time to market. When used with computer-on-module processors, FeaturePak modules can reduce the design effort to as little as placing I/O connectors on the baseboard. The illustration below shows a custom baseboard using a COM module for the processor and a FeaturePak module for the I/O. Up to 6 FeaturePak modules can be used on one baseboard. The photo below shows a FeaturePak module used as a technology building block to provide I/O in an industry-standard form factor module. In this case, the carrier board is designed to the industry standard and adopts the personality of whatever FeaturePak module is installed in it. Since FeaturePak modules are smaller than most industry standard I/O modules, this technique can be used to create I/O modules in many different form factors from just one FeaturePak module. This reuse of technology reduces development effort and provides consistent performance across multiple form factors. Industry-standard carrier board MXM connector FeaturePak module 50-pin I/O connector 50-pin I/O connector FeaturePak Specification and Design Guide Revision 1.00 Page 6 of 22

7 1.4 Host Interfaces FeaturePak provides several serial interfaces for communication with the host. The interfaces and governing specifications are listed here. Feature Quantity / Notes Governing Standard PCI Express 2 x1 links PCI Express Base Specification USB 2 ports, version 1.1 or 2.0 Universal Serial Bus 2.0 Specification, Revision 2.0, April 27, UART 1 port with logic level TX, RX, RTS, CTS EIA232-D specification SMBus Provided System Management Bus Specification, Version 2.0, August 3, Minimum Feature Requirements The FeaturePak standard defines two types of expansion slots: FeaturePak and FeaturePak USB. Each type defines a minimum feature set for interchangeability with the open market of FeaturePak modules. The only difference between the two is the number of PCIe and USB links. A host board must provide the following minimum features to the MXM connector to be called FeaturePak compliant or FeaturePak USB compliant. Feature Requirements for FeaturePak Compliant Host Socket Requirements for FeaturePak USB Compliant Host Socket +3.3VDC Present, minimum 1A available Present, minimum 1A available +5VDC Present, minimum 1A available Present, minimum 1A available PCIe Reset Present, active low Present, active low PCIe 1 x1 link minimum None USB 1 port minimum, 1.1 or better 2 ports, 1.1 or better Slot ID Must start with 001 and end with 110 (6 slots maximum) Must start with 001 and end with 110 (6 slots maximum) FeaturePak Specification and Design Guide Revision 1.00 Page 7 of 22

8 2 FEATUREPAK MODULE 2.1 Mechanical Drawing The general mechanical drawing is shown below. Detailed finger patterns, component height restrictions, and other information is described in later sections. The finger edge of the board should have a bevel of.25mm /.01 on both top and bottom sides. See side view drawing below. FeaturePak Specification and Design Guide Revision 1.00 Page 8 of 22

9 2.2 PCB Finger Patterns Top side finger pattern Dimensions are in inches (mm). Note the missing fingers and special finger numbering on the left Bottom side finger pattern Dimensions are in inches (mm). Note the missing fingers and special finger numbering on the left Finger plating The fingers are gold plated with a minimum thickness of /.00075mm (30 micro-inches). FeaturePak Specification and Design Guide Revision 1.00 Page 9 of 22

10 2.3 Component Keepout Areas There are two keepout areas for components shown in the mechanical drawing. Components must remain out of these areas to avoid interference with the FeaturePak connector. 2.4 Top and Bottom Component Height Tall and short component regions are specified on both top and bottom sides of the board. In addition, both Standard and Tall module heights are defined. A Standard height module mounted in a FeaturePak connector on a carrier board can have a PC/104 or similar stacking board with 0.6 spacing installed above it. The short component region on the top side is provided to enable the board to install properly at an angle in the MXM connector. The tall component region on the bottom side is provided to increase flexibility in component selection and placement. The connector pinout assigns all power connections to the bottom side, so a typical layout would provide power supply bypass capacitors in this tall component region. FeaturePak Specification and Design Guide Revision 1.00 Page 10 of 22

11 2.5 PCB Thickness The required nominal thickness of a FeaturePak module PCB is.047 / 1.2mm. This thickness is defined by the MXM connector. Any deviation from this thickness may cause unpredictable mating or reliability problems. 2.6 Mounting Holes FeaturePak modules use two mounting holes for increased ruggedness and reliability. The holes are.110 / 2.8mm diameter with a circular copper pad of.220 / 5.6mm diameter minimum on both top and bottom sides. They are designed to be used with M2.5 x 0.45 panhead screws. The copper pads are not required to be connected to ground or shield, however they may be connected to provide an improved path from the module to the baseboard. The pads may also be used for thermal connections to the baseboard if desired. FeaturePak Specification and Design Guide Revision 1.00 Page 11 of 22

12 3 FEATUREPAK CONNECTOR 3.1 Description FeaturePak modules use the MXM connector to connect to the baseboard. The MXM connector provides 230 contacts organized into two rows of 115 contacts, with 0.5mm pitch. The connector is rated for 2.5Gbps operation, making it suitable for PCI Express, USB, and other high speed signals. It contains an alignment bar to ensure proper orientation of the FeaturePak module during insertion. The alignment bar is the primary reference point for the relative position of the module and the connector. Sample illustration of MXM connector showing board insertion side and alignment bar 3.2 Module Height Above Baseboard MXM connectors are available with different board to board heights. The standard host board configuration uses a connector with 5.0mm spacing between the host board and the FeaturePak module, a shown in the illustration below. However a host board may use a taller connector if desired in order to provide higher clearance for host board components under the module. In all cases, care should be taken that the connector is not placed where the module may interfere with other boards installed over it. 3.3 Connector Suppliers Suggested vendors and part numbers of acceptable FeaturePak connectors are listed below. Vendor Foxconn Foxconn Aces Part number AS0B326-S78N-7F AS0B321-S78N-7F D0K 3.4 Current Capacity Each MXM connector contact is rated for 0.5A maximum. The connector pinout definition includes the following power capabilities. Actual power capability is limited by the system power supply. Supply Voltage No. of pins Total power capacity 3.3V 8 12W 5V W FeaturePak Specification and Design Guide Revision 1.00 Page 12 of 22

13 3.5 PCB Footprint The 50-signal I/O section of the FeaturePak connector includes special no-connect pins (shown in shading in section 4.2, 50-pin I/O connector pinout below) to provide for increased isolation between the intervening I/O signals. In these locations, FeaturePak boards should not have fingers, and baseboards should have narrower pads as shown in the footprint drawing below. The illustration below shows a typical FeaturePak connector PCB footprint. In this illustration, the FeaturePak module inserts into the connector at the lower edge. Note the position of pin 1 on the connector. The lower edge of the connector in this illustration corresponds to the lower side of the FeaturePak module PCB. The FeaturePak standard defines 34 unused contacts in the I/O area of the connector, intended to provide increased isolation between I/O signals. See section 4.2 for identification of these contacts. In these unused locations, the PCB pads are only / 0.2mm wide, instead of the / 0.36mm width shown in the above illustration. This is intended to provide sufficient area for a reliable solder joint to hold the connector leads in place, while maintaining maximum isolation between pads. FeaturePak Specification and Design Guide Revision 1.00 Page 13 of 22

14 4 FEATUREPAK CONNECTOR PINOUT 4.1 Overview The FeaturePak module connector pinout is different from the MXM graphics standard and other standards, such as Q7, that use MXM connectors. FeaturePak modules are not compatible with MXM connectors designed for use with these other standards. By definition, the odd numbered pins are on the bottom side of the FeaturePak module, and the even numbered pins are on the top. All power connections except the auxiliary +12V are on the odd, or bottom, side of the connector to simplify board layout and power supply bypassing. The connector pinout is divided into three sections: Section 1: Host interface This section includes PCIe, USB, Serial interfaces along with reset, auxiliary, and slot ID signals. Section 2: Secondary I/O signal group This section includes 5V power and the 50 I/O signals for the baseboard secondary I/O connector. Section 3: Primary I/O signal group This section includes 5V power and the 50 I/O signals for the baseboard primary I/O connector. This connector includes special isolation considerations on 34 signal pairs to support signals such as high precision analog, Ethernet, and optoisolated I/O. FeaturePak Specification and Design Guide Revision 1.00 Page 14 of 22

15 4.2 Pinout Diagrams Section 1: System Interface +3.3V V +3.3V 3 4 PS-Current Ground 5 6 Ground PCIe-TX PCIe-RX1+ PCIe-TX PCIe-RX1- Ground Ground PCIe-CLK PCIe-CLK2+ PCIe-CLK PCIe-CLK2- Ground Ground PCIe-TX PCIe-RX2+ PCIe-TX PCIe-RX2- Ground Ground PCIe-Reset Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Ground Ground USB-Ch USB-Ch2+ USB-Ch USB-Ch2- Ground Ground +3.3V USB-OC1/ V Serial-RX Serial-TX Serial-CTS Serial-RTS SMBclk SMBalert# SMBdata Slot ID Slot ID 1 Slot ID Present- JTAG-TDI JTAG-TDO JTAG-CLK JTAG-TMS Sys-Reset Reserved +3.3V Ground +3.3V Ground Reserved Reserved Reserved Reserved +3.3V Ground Reserved Reserved Reserved Reserved +3.3V Ground Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FeaturePak Specification and Design Guide Revision 1.00 Page 15 of 22

16 Section 2: Secondary I/O Signal Group +5V Ground +5V Ground I/OB I/OB-49 I/OB I/OB-47 I/OB I/OB-45 I/OB I/OB-43 I/OB I/OB-41 I/OB I/OB-39 I/OB I/OB-37 I/OB I/OB-35 I/OB I/OB-33 I/OB I/OB-31 I/OB I/OB-29 I/OB I/OB-27 I/OB I/OB-25 I/OB I/OB-23 I/OB I/OB-21 I/OB I/OB-19 I/OB I/OB-17 I/OB I/OB-15 I/OB I/OB-13 I/OB I/OB-11 I/OB I/OB-9 I/OB I/OB-7 I/OB I/OB-5 I/OB I/OB-3 I/OB I/OB-1 FeaturePak Specification and Design Guide Revision 1.00 Page 16 of 22

17 Section 3: Primary I/O Signal Group This section includes special no-connect pins (shown in shading below) to provide for increased isolation between the intervening I/O signals. These signals may optionally used as differential pairs as shown in the table. In these locations, FeaturePak boards should not have fingers, and baseboards should have narrower pads. +5V Ground +5V Ground +5V Ground I/OA I/OA-49 I/OA I/OA-47 I/OA I/OA-45 I/OA I/OA-43 I/OA I/OA-41 I/OA I/OA-39 I/OA I/OA-37 I/OA I/OA-35 (NC) (NC) Diff pair 16 / I/OA I/OA-33 / Diff pair 15 (NC) (NC) Diff pair 16 / I/OA I/OA-31 / Diff pair 15 (NC) (NC) Diff pair 14 / I/OA I/OA-29 / Diff pair 13 (NC) (NC) Diff pair 14 / I/OA I/OA-27 / Diff pair 13 (NC) (NC) Diff pair 12 / I/OA I/OA-25 / Diff pair 11 (NC) (NC) Diff pair 12 / I/OA I/OA-23 / Diff pair 11 (NC) (NC) Diff pair 10 / I/OA I/OA-21 / Diff pair 9 (NC) (NC) Diff pair 10 / I/OA I/OA-19 / Diff pair 9 (NC) (NC) I/OA I/OA-17 (NC) (NC) Diff pair 8 / I/OA I/OA-15 / Diff pair 7 (NC) (NC) Diff pair 8 / I/OA I/OA-13 / Diff pair 7 (NC) (NC) Diff pair 6 / I/OA I/OA-11 / Diff pair 5 (NC) (NC) Diff pair 6 / I/OA I/OA-9 / Diff pair 5 (NC) (NC) Diff pair 4 / I/OA I/OA-7 / Diff pair 3 (NC) (NC) Diff pair 4 / I/OA I/OA-5 / Diff pair 3 (NC) (NC) Diff pair 2 / I/OA I/OA-3 / Diff pair 1 (NC) (NC) Diff pair 2 / I/OA I/OA-1 / Diff pair 1 FeaturePak Specification and Design Guide Revision 1.00 Page 17 of 22

18 4.3 Functional Descriptions In the table below, all directions are from the point of view of the FeaturePak module. All logic signals are 3.3V logic compatible. NOTE: FeaturePak modules are designed to work with 3.3V logic. Do not attempt to drive any input with 5V logic as damage may occur to the FeaturePak module. Name Type Default Definition PS_Current Input Optional analog sense input for on-board power supply PCIe-TX[1-0]+/- Input PCI Express TX signals from host PCIe-RX[1-0]+/- Output PCI Express RX signals to host PCIe-CLK[1-0]+/- Input PCI Express clock signals from host PCIe-Reset- Input High PCI Express reset signal from host USB-Ch[1-2]+/- Bidir USB data signals USB-OC1/2- Output High USB overcurrent indicator, shared by both USB channels Serial-TX Input Low Logic level UART transmit data from host / receive to module Serial-RX Output Low Logic level UART receive data to host / send from module Serial-RTS Input Low Logic level UART ready to send signal from host Serial-CTS Output Low Logic level UART clear to send signal to host SMBalert# Output High SMBus alert signal to host SMBData Bidir SMBus data signal SMBClk Input SMBus clock Slot ID[2-0] Input Slot ID indicator, hardwired on baseboard; all slots must have unique slot ID numbers. See text for more information. Present- Output Low A FeaturePak module must drive this signal low (e.g. hard connection to ground). This signal is pulled high on the baseboard through a 10K ohm resistor. It may be read by a GPIO pin on the baseboard to indicate whether a module is installed in the socket. Reserved FeaturePak reserved pins for future expansion. SYS-Reset- Output High System reset, input to host; This can be used by a FeaturePak module to command a system reset, for example upon timeout of a watchdog timer circuit. JTAG-xxx Standard JTAG signals; may be connected to a JTAG connector on the baseboard or to GPIO pins to generate JTAG signals; used to program logic and memory devices on a FeaturePak module. I/OA[1-50] I/O signals from the primary 50-pin I/O connector; definition is provided by the FeaturePak module manufacturer. I/OB[1-50] I/O signals from the secondary 50-pin I/O connector; definition is provided by the FeaturePak module manufacturer. NC These locations are left unconnected on the baseboard and the module to allow for greater isolation between I/O signals on the module. +3.3V Power Input Primary power source for FeaturePak modules +5V Power Input Secondary power source for FeaturePak modules, e.g. for an analog power supply. +12V Signal Input This pin may be used as a system health monitor to measure the 12V system power if present. This is not a power pin. Ground Power supply and signal reference for FeaturePak modules. FeaturePak Specification and Design Guide Revision 1.00 Page 18 of 22

19 5 FEATUREPAK HOST BASEBOARD DESIGN GUIDELINES 5.1 Module Mounting Position The FeaturePak module position on the baseboard relative to the MXM connector is shown below. Note that the lower edge of the module is aligned with an imaginary line running between the centers of the MXM connector PCB alignment holes. This drawing may be used to position the mounting holes on the baseboard relative to the FeaturePak connector. 5.2 Mounting Hardware The mounting hardware for a FeaturePak module is quantity 2 5.0mm (0.197 ) high female spacers with M2.5 x 0.45 internal thread and 5mm max outer diameter. The spacers may be soldered or press fit into the baseboard, or they may be fastened with an M2.5 screw from the bottom side. At least 3mm of thread depth should be available on the top side of the spacers for installing screws to hold the FeaturePak module in place. The top side screws should be M2.5 x 0.45 panhead screw with mm length. The screw head diameter must be less than or equal to the diameter of the module s mounting hole top side pad (0.220 / 5.6mm). FeaturePak module mounting holes should be tied directly to a ground plane on the host PCB. This connection provides a path for optional heat sinking from the module to the baseboard through the mounting spacers. 5.3 Connector Identification To avoid confusion with MXM connectors used for other boards, a FeaturePak connector on a host board should have the following cautionary note written in silkscreen along its length, either inside or outside the module outline, in either mixed or upper case: FeaturePak Module Only FeaturePak Specification and Design Guide Revision 1.00 Page 19 of 22

20 5.4 Component Height Limits Under a FeaturePak Module This section describes hose board component height limitations based on the standard 5mm module mounting height. If a taller FeaturePak connector is used, the limits for the host board components are adjusted accordingly. However the height limitations of the FeaturePak module components are obviously independent of the selection of the baseboard FeaturePak connector and therefore do not change. Components installed in the area of the host PCB directly underneath the tall component area of a FeaturePak module must be no more than 1.5mm high. Components installed in the area of the host PCB directly underneath the short component area of a FeaturePak module, as well as in a band.040 / 1mm wide around the 3 exposed sides of the FeaturePak module, must be no more than 2.5mm high. These height limitations allow for.020 / 0.5mm clearance between the baseboard components and the FeaturePak module. FeaturePak Specification and Design Guide Revision 1.00 Page 20 of 22

21 5.5 Reset Functions FeaturePak defines 2 reset signals: PCIe Reset-: This reset input signal is active low. It is an input to the FeaturePak module and is driven by the host. All FeaturePak modules should use PCIe Reset- as their master reset input. A host board that does not provide a PCIe interface to a FeaturePak connector should provide a suitable active-low master reset signal to this pin. SYS-Reset-: This reset output signal is active low. It is an output from the FeaturePak module to the host and should be incorporated into the host reset circuitry. This signal may be used by the module to generate a master reset, for example during a watchdog timer timeout. 5.6 Slot ID Each slot in a FeaturePak system has a unique 3-bit slot ID. The first slot is always numbered 1 (001 binary), and each successive slot is numbered one higher, until the highest slot number 6 (110). The maximum number of slots in one system is 6. Slot ID numbers 0 and 7 (000 and 111 binary) are reserved and should not be used. The slot ID is hardwired by the host using the 3.3V supply and ground. Each FeaturePak module treats these lines as signal inputs and does not drive them, pull them up or down, or use them for power. A FeaturePak module may make the value of the slot ID readable in a register, so that the system software can identify which module is in which slot. The Slot ID system is required on the host board but is optional in a FeaturePak module. 5.7 Present- Each FeaturePak connector in a system has a unique Present- signal pulled high on the host board with a 10K ohm resistor. Each FeaturePak module must drive the Present- signal low with a hard connection to ground. This indicates to the host that a module is present in the slot. The Present- signals may be read by the host using GPIO pins. The use of the Present- signaling system is optional. If unused by the host, the Present- pins may be left unconnected. 5.8 UART Signals The UART signals are logic level, not RS-232 level. A FeaturePak module using these signals should accept 3.3V or 5V logic level UART signals and should drive 3.3V level UART signals. FeaturePak Specification and Design Guide Revision 1.00 Page 21 of 22

22 5.9 I/O Connector Types The FeaturePak standard defines two user I/O connectors with a total of 100 I/O pins. Two methods of connection are supported, internal and external. The internal connector may be used with cables or daughterboards to provide user connections. The external connector is intended to be accessible outside the system enclosure (directly accessible by the user). The selection of internal or external connectors is at the option of the host board designer. Connector # pins Host connector, internal Host connector, external Primary pin.1 or 2mm dual-row male header 50-pin.1 dual-row male header Secondary pin.1 or 2mm dual-row male header 50-pin.1 dual-row male header These I/O pins can be defined and used in any way desired by the FeaturePak module designer. NOTE: No I/O connector power or ground pins are defined by the standard; all I/O pins connect directly to the MXM connector. Therefore if the designer desires to provide power or ground signals on the I/O connectors, these must be provided by the FeaturePak module. In systems where the designer will control both the FeaturePak module and the hosting baseboard with its I/O connectors, the designer is free to use these I/O pins in any way desired, and to define the baseboard connectors in any way desired. A FeaturePak module designed for the open market, or a host baseboard designed to be used with off the shelf FeaturePak modules, should conform to these connector groupings and connector types to maintain compatibility with other modules or baseboards that may be used with the product I/O Connector Signal Routing Because FeaturePak signals may consist of many types that are unknown at the time of baseboard design, special care must be taken to ensure that the PCB layout does not degrade the quality of the signals. Speed, crosstalk, and isolation are the main issues of concern. I/O signals should be routed from the FeaturePak connector to the user I/O connector in as direct a path as possible with a minimum number of vias. Signals for each connector group should be kept together in the same region and on the same layer if possible. Minimize routing other traces in the same region as the FeaturePak I/O signals. The primary 50-pin connector has additional layout requirements. This connector has 34 pins dedicated to special functions, including low-noise analog signals and high isolation signals such as optoisolated I/O or Ethernet. These 34 pins are organized into 16 pairs, as shown in the pinout diagram in section 4.2. The intervening connector contacts are unused (NC) on the FeaturePak module. To maximize isolation between signal pairs, the PCB has narrower pads in the locations of these NC pins; see section 3.5. The 16 pairs should be routed in a direct path between the FeaturePak connector and the I/O connector. Each pair should be kept together with equal length, equal spacing, and equal trace width. Maintain separation between trace pairs to maximize galvanic isolation. FeaturePak Specification and Design Guide Revision 1.00 Page 22 of 22