I N T E R C O N N E C T A P P L I C A T I O N N O T E. STEP-Z Connector Routing. Report # 26GC001-1 February 20, 2006 v1.0

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1 I N T E R C O N N E C T A P P L I C A T I O N N O T E STEP-Z Connector Routing Report # 26GC001-1 February 20, 2006 v1.0 STEP-Z CONNECTOR FAMILY Copyright 2006 Tyco Electronics Corporation, Harrisburg, PA All Rights Reserved

2 Table of Contents Item Page # I. INTRODUCTION...2 II. CONNECTOR OVERVIEW: STEP-Z...3 III. CONNECTOR DEFINITION...4 A. Dimensions...4 B. Fabrication Technology Pad Size Non-functional Pads Thermal Relief Antipad Size...7 C. High-Speed Via Design Counterboring Micro Vias...9 IV. ROUTING...10 A. Routing Channels...10 B. Trace Widths...11 C. Connector Footprint Options...11 D. Recommended Footprints...12 V. SUMMARY...13 VI. PART PLACEMENT...14 VII. ADDITIONAL INFORMATION...14 A. Gigabit Research and General Application Notes...14 B. Electrical Models...14 VIII. CONTACT INFORMATION...14 The information contained herein and the models used in this analysis are applicable solely to the specified Tyco Electronics connector as dated by the document. All information should be verified that it is representative of the current implementation of the connector. Alternative connectors may be footprint-compatible, but their electrical performance may vary significantly, due to construction or material characteristics. Usage of the information, models, or analysis for any other connector or previous implementation is improper, and Tyco disclaims any and all liability or potential liability with respect to such usage.

3 STEP-Z Connector Routing I. INTRODUCTION As engineers design systems that attempt to push serial speeds across system environments in the multi-gigabit per second range, the selection of the system s electrical connector becomes more significant. Electrical, mechanical, and manufacturing aspects of the connector must be considered simultaneously. At the board level these aspects combine with common board design practices to influence the design of the connector-to-board interface and how the board itself will be routed. The manner in which the connector is designed into the system can significantly impact the system s intended performance. Tyco Electronics has been actively researching these areas in an effort to help customers use the STEP-Z connector in applications requiring 10+ Gb/s data rates. The combination of interconnect research and intimate knowledge of the connector is presented to provide insight into the capability of a STEP-Z system design. This document provides specific design recommendations that will address layout, electrical performance, and manufacturability tradeoffs of the connector at the board level. PAGE 2 February 20, 2006

II. CONNECTOR OVERVIEW: STEP-Z Figure 1: STEP-Z Mezzanine Connectors The STEP-Z product family is a grid array mezzanine connector specifically designed for high speed and high density applications

4 II. CONNECTOR OVERVIEW: STEP-Z Figure 1: STEP-Z Mezzanine Connectors The STEP-Z product family is a grid array mezzanine connector specifically designed for high speed and high density applications operating at 10+ gigabit per second data rates. The STEP-Z connector is available in various high speed position sizes ranging from 104 to 296 signals per connector. The connector is also available in multiple stack heights within the range of mm to mm. The high density design, 158 signals per linear inch, provides for an array of high speed signal contacts enabling high signal pin counts. Outstanding features of the product family include dual beam signal contacts for a highly reliable interface connection, receptacle contacts fully protected with a plastic cover, and a polarized housing design to ensure proper mating. Both the receptacle and plug use a ball grid array attachment which minimizes the performance degradation found with through-hole connections and improves routing capabilities. These connectors use dedicated grounds to provide impedance matching and low cross-talk. This frees the signal contacts so they can be configured to the application requirements while limiting any impact on performance. The STEP-Z interconnection system is ideally suited to applications such as CPU/memory module interconnection, I/O port module interconnection, and interconnecting adjacent daughtercards. PAGE 3 February 20, 2006

5 III. CONNECTOR DEFINITION A. DIMENSIONS Full mechanical dimensioning and tolerances are available for all versions of the STEP-Z connector. These drawings can be located at Figure 2 shows the recommended PCB dimensions, in millimeters, for the STEP-Z connector. All dimensions within the footprint are identical for both the plug and receptacle components. The hole sizes mentioned in this document are driven by manufacturing guidelines and designed for optimal routing of the STEP-Z connector. Manufacturing dependant dimensions are discussed later in this document. Figure 2: STEP-Z Recommended PC Board Layout Although the above diagram provides dimensions for the PCB layout additional apertures are needed when routing the STEP-Z connector. Since the STEP-Z connector is a surface mount PAGE 4 February 20, 2006

6 ball grid array two options are available to break out of the footprint pattern Via-in-Pad and Escape Via. The most common approach is the Escape Via, which is shown below in Figure 3. For more information on the Via-in-Pad and Escape Via options refer to section IV.C Connector Footprint Options. Figure 3: STEP-Z Recommended PCB Layout with Escape Vias B. FABRICATION TECHNOLOGY Other important dimensions for board layout are determined by the capabilities of the circuit board fabricator. Current high-tech PCB industry fabrication technology (i.e. capability) requires minimum pad sizes ranging from D+10 mils through D+18 mils, where D is the diameter of the drilled hole size. These resultant pad sizes for a given technology are typically defined as the minimum pad size required maintaining 0.05 mm (0.002") of annular ring for a given PCB manufacturer s capability. Annular ring is an industry standard measure of the clearance between the pad edge and worst-case drill edge after manufacturing. For the STEP-Z connector this results in minimum escape via pad sizes ranging from 0.55 mm (0.021") to 0.73 mm (0.029"). Because the STEP-Z is typically used in high speed or dense applications where routing issues are most significant, all pad dimensions in this document will assume a D+12 mil pad size, unless otherwise specified. The escape pad diameter may be optimized for specific project needs, and should be evaluated on a project and vendor basis. Designing with a D+10 mil technology PCB or smaller could mean reduced yields or breakout, potentially adding cost to the PCB or violating industry specification compliance. Note: A minimum pad to trace clearance of 0.13 mm (0.005") will also be assumed for calculating routing dimensions. PAGE 5 February 20, 2006

7 1. PAD SIZE Two separate pads need to be examined for the STEP-Z connector. First is the solder pad, which is required in order to mate the connector to the PCB. The recommended solder pad, mm ( ), will provide an optimal mechanical and electrical interface between the connector and PCB. The second pad is the escape via pad required for manufacturability. The escape via, shown in figure 3, drives the escape via pad size. Based upon the D+12 mil fabrication technology assumption, a 0.58 mm (0.023") diameter escape via pad should be used. For higher-tech PCBs, (D+10 mil), the escape via pad would be decreased to 0.53 mm (0.021 ). Connector Pins Signal & GND Escape Via Pad size High-tech Low tech D+10 D+12 D+14 D+16 D mm 0.58 mm 0.63 mm 0.68 mm 0.73 mm (0.021 ) (0.023 ) (0.025) (0.027 ) (0.029 ) Table 1: Pad sizes for STEP-Z Escape Vias In some cases the reduced manufacturability of a D+10 mil technology PCB or smaller is required to reduce pad sizes. A reduced pad may potentially result in added cost of the PCB due to reduce yields, caused by breakout or open connections. Where possible the largest appropriate pad size should be used to provide the PCB manufacturer with the greatest flexibility, thereby reducing overall system costs. Although an increased pad size also reduces electrical performance by increasing the capacitance of the plated through-hole, this effect has only a minor impact when unused pads are removed from the signal via. 2. NON-FUNCTIONAL PADS The removal of non-functional internal pads will improve signal integrity and manufacturability of the PCB. However, some assembly facilities prefer that unused pads are retained in order to maintain hole integrity through various soldering processes. For electrical reasons it is recommended that unused pads be removed on internal layers. 3. THERMAL RELIEF Typical printed circuit board designs, mm ( ), which are intended to interface with the STEP-Z connector do not require thermal relief. If the STEP-Z connector is being designed into a non-typical application the customer should consult their assembly shop to determine if any mating features are required in the PCB design. PAGE 6 February 20, 2006

8 4. ANTIPAD SIZE Via Antipads, or plane clearances (Figure 4), are required to separate signal holes from reference voltages to avoid shorting. Pad Choosing the proper size of these Trace clearances is critical in determining several other design parameters: signal integrity, EMI, voltage breakdown, and manufacturability. Determining the proper antipad size for Plane Antipad STEP-Z depends upon system design goals. Several scenarios are exemplified Figure 4: Antipad Illustration below. Antipad sizes are minimized: To reduce noise by closely shielding adjacent pins with reference planes To reduce EMI by minimizing aperture sizes in reference planes To maintain a strong reference to ground for single-ended traces and ground referenced differential traces Antipad sizes are maximized: To maximize voltage breakdown spacing between the pin and the reference plane To increase manufacturability by reducing the chance of shorting. To reduce reflections in a high-speed gigabit serial system by reducing the capacitive effect of the plated through-hole. In cases where antipads are minimized, the recommended antipad size is the pad diameter plus 0.25 mm (0.010 ). This size maximizes trace coverage, while not risking shorting the plane to the barrel in the case of drill breakout. Using a minimal antipad will increase the capacitance of the via and could degrade system performance at high speeds. When antipads are maximized, the antipad geometry is dependent on the type of signals passing through the vias. PAGE 7 February 20, 2006

9 Antipad structures for the STEP-Z connector should be examined for the solder pad and the escape via pad. If the surface layer is a ground fill antipads will be required for both the solder pads and the escape via pads. The antipad size should be determined so it does not interfere with the routing channels. The recommended antipad for the solder pad is 0.83 mm (0.033 ). The suggested escape via antipad structure for the STEP-Z connector is shown below in Figure 5. These antipad recommendations are related to D+12 pad technology. The D+12 pad size, labeled as Escape Via Pad in Figure 5 is 0.58 mm (0.023 ) diameter. The resulting singleended antipad dimension of 0.83 mm (0.033 ) represents a geometry which maximizes routable trace widths and associated ground coverage. A board design that uses a non-d+12 pad size, could result in a difference in the antipad diameter. A board design that does not require the entire width of the routing channel (routable space between columns) should use a larger antipad diameter, to help with minimization of via capacitance. Routing geometries are further discussed in section IV. Escape Via 0.27mm (0.011 ) Trace Escape Via Pad 0.58 mm (0.023 ) Antipad 0.83mm (0.033 ) Plane Figure 5: Single-Ended Antipad Geometry PAGE 8 February 20, 2006

10 C. HIGH-SPEED VIA DESIGN At gigabit speeds, one of the limiting factors in system design is the effect caused by the via stub in the board. A via stub is the portion of via that is not in series with the transmission path of the signal, as shown in Figure 6. At high frequencies, this parallel path creates a significant capacitive discontinuity, which degrades the throughput of the link. Although it has a small impact at lower frequencies, this stub typically becomes critical at speeds greater than Gbps. Since the STEP-Z connector does not require plated thru-holes for interfacing the connector to the PCB considerable thought should be taken into the removal of any via stub. Several techniques can be applied to remove the stub. Consult your board fabrication facility regarding their capabilities for these advanced technologies. Figure 6 Via Stub 1. COUNTERBORING Counterboring is a technique that has been used for years by the microwave industry to treat vias in microwave designs. With digital signaling approaching microwave frequencies, similar techniques can be employed to enhance the signal integrity of a link. Counterboring is performed as one of the final steps in the board manufacturing process. After the multilayer board is laminated, drilled, and plated, designated holes are control-depth drilled to remove any via stub that is present. This controlleddepth drill should allow a minimum length of barrel to remain in the hole. Figure 7 illustrates a counterbored via. 2. MICRO VIAS An alternative approach that can be as effective as counterboring is the use of microvias. Several microvia formation technologies are currently in use including laser drilling, photovia, buried bump interconnectors (B2IT), plasma hole etching, and mechanical drilling. Of these five techniques, plasma and mechanical drilling are the least used. Photovia is extremely costly, while B2IT requires special licensing agreements. Laser drilling is most commonly used for microvias due to its low cost and wide range of dielectric materials with which it is compatible. Contact your local PCB fabrication shop for their capabilities with microvia technology. Figure 8 illustrates a standard microvia. Figure 7 Counterbored Via Figure 8 Micro Via PAGE 9 February 20, 2006

IV. ROUTING Because the STEP-Z connector can be used for both single-ended and differential signals, designing for the largest possible routing channel becomes important.

11 IV. ROUTING Because the STEP-Z connector can be used for both single-ended and differential signals, designing for the largest possible routing channel becomes important. Whether routing into or through the STEP-Z, pinfield, the general guidelines are the same. A. ROUTING CHANNELS A routing channel is defined by the space between adjacent vias in the connector pinfield. In STEP-Z, both vertical (between rows of vias) and horizontal (between columns of vias) routing can be achieved. Typical board routing is implemented horizontally, because this type of routing significantly reduces the number of routing layers. Full routing of the STEP-Z connector can be achieved with horizontal routing in 4 signal layers. As stated above vertical routing is also possible but this type of routing will require a significant increase in the number of routing layers. If vertical routing is implemented, the number of signals vs the number of signal layers need to be taken into account. Figure 9 shows horizontal and vertical routing for the STEP-Z connector. Figure 10 illustrates how the full STEP-Z connector can be routed in 4 signal layers. Figure 9: Routing Configuration PAGE 10 February 20, 2006

B. TRACE WIDTHS Figure 10: Horizontal Routing The maximum trace width that can be utilized in a routing channel is a function of via pitch, pad size, and trace-pad clearance.

12 B. TRACE WIDTHS Figure 10: Horizontal Routing The maximum trace width that can be utilized in a routing channel is a function of via pitch, pad size, and trace-pad clearance. If a D+12 pad size is utilized, the remaining space allows for a maximum trace geometry of differential lines with a intra-pair space. Table 2 illustrates the calculation of the available routing channel. Metric English Via pitch 1.30 mm Pad diameter (D+12) mm Trace-pad clearance (x 2) mm mm Available routing channel 0.46 mm Table 2: Backplane Routing Channel Calculation For trace width determination, it is also important to ensure that traces have adequate ground coverage underneath them at all times. When routing through the connector footprint, this coverage can be improved by reducing the antipad size on connector vias. However, antipad reduction can result in reduced performance of the via at high speeds. Conversely, with a narrower differential geometry, the antipad size may be increased to improve performance of the via at high speeds. When the recommended differential trace geometry is routed through the STEP-Z footprint the reference plane will provide full coverage of the differential trace geometry. Please refer to section III.B.4 for antipad size recommendations. C. CONNECTOR FOOTPRINT OPTIONS When the density offered in the STEP-Z connector is not required a partially loaded version may be an option. The partially loaded version offers the flexibility of adjusting pad and antipad sizes while maintaining large routing channels. The partially loaded version is not a standard option. In order to learn more about these connectors refer to section VIII. PAGE 11 February 20, 2006

Figure 12 is a fully loaded footprint that is via-in-pad. The recommended drill is 0.25-0.28 mm (0.010-0.011 ), this will allow for appropriate pad manufacturing tolorences.

13 D. RECOMMENDED FOOTPRINTS Figure 11 shows the recommended fully loaded STEP-Z footprint for optimal routing. This part has been referred to throughout this document and should be used for dense high speed applications. This footprint skew matches the differential pairs within the footprint. Figure 12 is a fully loaded footprint that is via-in-pad. The recommended drill is mm ( ), this will allow for appropriate pad manufacturing tolorences. The via-in-pad option will require plugging in order to mate the connector to the printed circuit board. Consult your PCB fabrication shop to learn more about via plugging. Figure 11: Fully Loaded Standard Part Figure 12: Fully Loaded Via-in-Pad PAGE 12 February 20, 2006

14 V. SUMMARY Table 3 is provided to summarize the recommendations provided in this document: Item Value Connector Dimensions: STEP-Z Signal Pin Column Pitch 1.30 mm (0.051 ) * STEP-Z Signal Pin Row Pitch 2.00 mm (0.079 ) * Number of Signal Positions (fully loaded) 104, 200 and 296 Number of Connector Columns 13, 25 and 37 Number of Connector Rows 18 Number of Signal Rows 8 Number of Ground Rows 10 Fully Loaded Standard Part Footprint Dimensions: Suggested Escape Via Drill 0.27 mm (0.011 ) Suggested Solder Pad 0.58 mm (0.023 ) Suggested Escape Via Pad 0.58 mm (0.023 ) Suggested Solder Pad Antipad 0.83 mm (0.033 ) Suggested Escape Via Pad Antipad 0.83 mm (0.033 ) Maximum Single-Ended Trace Width 0.46 mm (0.018 ) Suggested Differential Trace Width 0.13 mm (0.005 ) Suggested Differential Spacing 0.15 mm (0.006 ) Fully Loaded Via-in-Pad Footprint Dimensions: Suggested Drill 0.27 mm (0.011 ) Suggested Solder Pad 0.58 mm (0.023 ) Suggested Antipad 0.83 mm (0.033 ) Maximum Single-Ended Trace Width 0.58 mm (0.023 ) Suggested Differential Trace Width 0.15 mm (0.006 ) Suggested Differential Spacing 0.20 mm (0.008 ) Layer Requirements: Layers Required to Route out of a Fully Loaded STEP-Z connector 4 Table 3: Summary *Includes Stagger see customer drawing found in Section VI Part Placement PAGE 13 February 20, 2006

15 VI. PART PLACEMENT Part placement and spacing guidelines as well as associated up-to-date mechanical dimensions should be obtained in addition to this document. Placement related information is contained within the application specification, document # The full mechanical dimensioning and tolerances are available for all versions of the STEP-Z connector. All of this information can be found in the customer drawing, located at or by contacting your local Tyco Electronics support or the appropriate contact listed below. VII. ADDITIONAL INFORMATION A. GIGABIT RESEARCH AND GENERAL APPLICATION NOTES More information regarding Tyco Electronics research into the transmission of electrical signals at gigabit speeds or general application notes are available for download from the Internet at B. ELECTRICAL MODELS Electrical and Board Layout models for the STEP-Z connector may be requested at Mechanical CAD models may be requested at VIII. CONTACT INFORMATION The following key contacts can be used to obtain additional information on the STEP-Z product family. Technical Support Center PAGE 14 February 20, 2006

I N T E R C O N N E C T A P P L I C A T I O N N O T E. Z-PACK TinMan Connector Routing. Report # 27GC001-1 May 9 th, 2007 v1.0

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