Set Up a PLL Loop Filter on the ez80f91 MCU

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Application Note Set Up a PLL Loop Filter on the ez80f91 MCU AN017504-0108 Abstract This document provides information that will help an application developer effectively use the ez80f91 MCU s

1 Application Note Set Up a PLL Loop Filter on the ez80f91 MCU AN Abstract This document provides information that will help an application developer effectively use the ez80f91 MCU s on-chip Phase-Locked Loop (PLL) feature as a system clock source. The included circuits and procedures can help the developer select the appropriate external loop filter components, code the application s PLL initialization sequence, and verify proper PLL operation. ez80acclaimplus! Flash MCU Overview ez80acclaimplus! on-chip Flash Microcontrollers are an exceptional value for customers designing high performance, 8-bit MCU-based systems. With speeds up to 50 MHz and an on-chip Ethernet MAC, designers have the performance necessary to execute complex applications quickly and efficiently. Combining Flash and SRAM, ez80acclaimplus! devices provide the memory required to implement communication protocol stacks and achieve flexibility when performing in-system updates of application firmware. The ez80acclaimplus! Flash MCU can operate in full 24-bit linear mode, addressing 16 MB without a Memory Management Unit. Additionally, support for the Z80-compatible mode allows Z80/Z180 customers to execute legacy code within multiple 64-KB memory blocks with minimum modification. With an external bus supporting ez80, Z80, Intel and Motorola bus modes and a rich set of serial communications peripherals, designers have several options when interfacing to external devices. automation, communications, industrial control and facility monitoring, and remote control. Definitions Loop Bandwidth The loop bandwidth, BW, is the effective PLL control loop range. It determines the PLL control loop s ability to track loop perturbations and noise. The loop can only track noise within the bandwidth of the loop. Therefore, a wider bandwidth is preferable. Phase Margin Phase margin is a measure of real-time PLL frequency control loop stability. Higher phase margin equates to better overall control loop performance. As the phase margin increases, frequency lock time also increases. Increased lock time is not a concern for applications using the ez80f91 MCU. The Loop Bandwidth and Phase Margin values defined in the tables in the section that follows show the potential impact of different Loop Filter Component selections on overall PLL performance. Discussion The ez80f91 PLL is part of the System Clock Generation block, which includes an on-chip oscillator, PLL circuit, and system clock source selection logic, as diagrammed in Figure 1. Some of the many applications suitable for ez80acclaimplus! devices include vending machines, point-of-sale terminals, security systems, Copyright 2008 by Zilog, Inc. All rights reserved.

2 System Clock (F OSC<SCLK<F OSC*N) SCLK-MUX PLL_CTL1[0] = PLL Enable RTC_CLK (1MHz<F OSC<10MHz) x2 x1 Oscillator PFD Charge Pump VCO Off-Chip Loop Filter PLL_INT Lock Detect PLL_CTL0[7:6] C PLL1 R PLL C PLL2 Div N PLL_CTL0[3:2] {PLL_DIV_H, PLL_DIV_L} Figure 1. System Clock Generation Block The PLL is a programmable frequency multiplier designed to generate the 50-MHz system clock (SYSCLK) from a variety of lower-frequency reference sources. The PLL requires the user to select an off-chip PLL reference frequency, the loop filter components, and to set the PLL setup and control registers based on off-chip component selections. User selectability of the multiplier source, as opposed to using a fixed reference, is offered to accommodate component constraints set by cost points, stocking approach, or performance goals. PLL programmability is not intended to generate SYSCLK frequencies other than 50 MHz. Note: Operation at frequencies other than the design target of 50 MHz are not guaranteed to function in all cases. The PLL s F out value should be defined as 50 MHz for guaranteed operation across the device s complete temperature and silicon-processing parameter range. Zilog production testing confirms that the PLL functions at an F out value equal to 50 MHz. The ez80f91 PLL is a third-order phase lock loop that utilizes an on-chip oscillator with an external crystal that functions as a reference, a Phase Frequency Detector (PFD), a charge-pump loop filter with external loop filter passive components, a Voltage Controlled Oscillator (VCO), and a frequency divider (programmable downcounter). The ez80f91 MCU s primary oscillator generates the PLL reference. The oscillator must be driven by a 1 10 MHz fundamental frequency crystal (see Figure 2 and Table 1). Alternatively, the X IN input pin can also accept a CMOS-level clock input signal. If an external clock generator is used in the design, the X OUT pin should remain unconnected. AN Page 2 of 7

3 On-Chip Oscillator X IN 1-10 MHz Crystal (Fundamental Mode) X OUT C = 22 pf 1 R = 100 KΩ C = 22 pf 2 Figure MHZ Crystal Circuit Table 1. Crystal Specifications Parameter 1 MHz 10 MHz Units Comments Frequency 1 10 MHz Resonance Parallel Mode Fundamental Series Resistance (RS) Ω Maximum Load Capacitance (CL) pf Maximum Shunt Capacitance (CO) 7 7 pf Maximum Drive Level 1 1 mw Maximum The charge-pump loop filter filters the PFD phase error signal to create the DC voltage that drives the VCO. The charge pump is a selectable current source with four programmable values: 1.5 ma, 1 ma, 500 µa, and 100 µa. The selected current drive is sinked/sourced onto the loop filter pin according to the error (or difference) between the falling edges of the PFD output signals. Ideally, when the PLL is locked, there are no control loop errors (error = 0) and no current is sourced/sinked onto the off-chip loop-filter. In general, the higher the charge pump current, the less sensitive the PLL is to noise disturbing the loop filter node; for example, power supply noise. The external loop filter passive components include a series capacitor, C PLL2, and a series resistor, R PLL, in parallel with a capacitor, C PLL1 (see Figure 1). The loop filter operates in the 1 10 MHz PLL reference frequency range. Therefore, high-performance components are not required. The components should be placed as close as possible to the Loop Filter pin and achieve a common Ground with the PLL_V SS pin. AN Page 3 of 7

4 The loop filter bandwidth and phase margin define overall PLL noise and frequency stability control. Zilog recommends using as high a PLL reference frequency as possible (for example, 10 MHz) to create the widest loop filter bandwidth and largest phase margin. The divider is a user-programmable downcounter. The function of the divider is to divide the frequency of its input signal (VCO OUT ) by a programmable factor N and supply the result to the PFD circuit. Factor N is defined as the target SYSCLK frequency reference (X IN ) frequency. Div N is programmed by the PLL_DIV_L and PLL_DIV_D registers. Table 2 contains acceptable values for different reference source frequencies. See Table 3 for the values that Zilog recommends as starting points for components and for PLL setup parameters for the chargepump currents. Table 2. Loop Filter Circuit Values X IN (MHz) N (div) SYSCLK (MHz) R PLL ± 10% C PLL2 ± 10% C PLL1 ± 10% Charge Pump Current Phase Margin (Degrees) BW k 33 nf 100 pf 100 µa KHz µf 220 pf 500 µa KHz µf 220 pf 1.0 ma KHz µf 220 pf 1.5 ma KHz k 10 nf 47 pf 100 µa KHz nf 220 pf 500 µa KHz nf 220 pf 1.0 ma KHz nf 330 pf 1.5 ma KHz nf 100 pf 100 µa KHz nf 220 pf 500 µa KHz nf 220 pf 1.0 ma KHz nf 220 pf 1.5 ma KHz nf 100 pf 100 µa KHz nf 220 pf 500 µa KHz nf 220 pf 1.0 ma KHz nf 220 pf 1.5 ma KHz Notes: 1. Place the loop filter components as close as possible to the package pins. Provide a common analog ground with the PLL device Ground pin. 2. A charge pump current of 500 µa is the recommended starting point. 3. Operation of the PLL for output frequencies other than 50 MHz is not guaranteed over the entire standard temperature range for all devices. The 40-MHz SYSCLK in this table is provided for reference. Zilog production testing confirms that the PLL functions at a SYSCLK value equal to 50 MHz. 4. Zilog recommends interpolating the loop filter component values between the given X IN frequencies. AN Page 4 of 7

5 Table 3. Recommended Values Parameter Value Units X IN 10 MHz N 5 SCLK 50 MHz R PPL 100 Ω C PLL2 47 nf C PLL1 220 pf Charge Pump Current 500 µa Verifying PLL Operation For most applications, the component values in Table 2 for a 500-µA charge-pump current are the best configuration for the defined X IN frequencies. To test the PLL setup, the following must occur: The PLL must lock The PLL must lock within the defined lock criteria of 8 or 16 reference frequency cycles. To ensure that the PLL locks correctly: Check the device and PLL_V DD Check the reference frequency Check the loop filter components Use 16 cycles as the lock criteria Increase the loop filter bandwidth and/or phase margin Following lock and PLL SYSCLK source selection, the PHI pin must have the correct frequency. To ensure that the PHI pin frequency is correct: Check the PLL_DIV value Check the reference frequency During PLL SYSCLK source operation, the PLL must not generate unlocked interrupts, as such: Check all of the above items System V DD, PLL V DD, and Ground should be checked for noise Initialization Sequence The following steps provide an example of the onchip initialization sequence. 1. POR/System Reset a. CLK_MUX defaults to External Crystal Oscillator PLL reference frequency. b. PLL_ENABLE defaults to DISABLED. c. All ez80f91 registers can be accessed as defined in the ez80f91 Product Specification (PS0192). 2. Define PLL Interrupt Service Routines a. PLL interrupts default on reset to Priority 3. b. Both the Locked and Unlocked PLL interrupts require ISR routines. 3. Program PLL Registers a. PLL_DIV_L b. PLL_DIV_H must be set to 00h. Only the lower PLL_DIV six bits are valid for the reference frequency range of 1 10 MHz; PLL_DIV is WRITE ONLY; READs return a 00h. c. CHRP_CTL is as defined in Table 2. d. LDS_CTL is set to 8 or 16 cycles of 20-ns duration, default is 8 cycles; 400-ns options are not supported on the ez80f91 MCU. 4. Enable PLL Operation a. INT_LOCK_EN must be set to Enabled 1. b. INT_UNLOCK_E must be set to Disabled 0. c. PLL_ENABLE must be set to Enabled On PLL-Locked Interrupt a. CLK_MUX must be set to PLL 01. b. INT_LOCK must be set to Read to clear. c. INT_LOCK_EN must be set to Disabled 0. AN Page 5 of 7

6 d. INT_UNLOCK_E must be set to Enabled Execute application code at PLL F OUT. AN Page 6 of 7

7 Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer 2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. ez80, ez80acclaim!, and ez80acclaimplus! are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. AN Page 7 of 7 7

An Automatic Temperature Control System Using RZK

Application Note An Automatic Temperature Control System Using RZK AN019902-0908 Abstract This application note demonstrates how an application running on Zilog s Real-Time Kernel (RZK) can be used to