Evaluation Board for the High Performance 10-Bit Display Interface AD9981/PCB

Transcription

1 FEATURES Two analog input connectors for RGB or YPbPr input Separate, low-noise regulators for each AD power domain (VD, VDD, and PVD) 00-pin interface connector provides V input and AD outputs (syncs, clock, and data) APPLICATIONS For evaluation of AD as part of the AD evaluation kit Can also be adapted to end-user evaluation platform using the 00-pin interface connector PACKAGE CONTENTS AD evaluation board 0-bit display interface board (ADxEB) DEPL evaluation software including preset files DEPL evaluation board documentation V power supply USB and parallel port cables Evaluation Board for the High Performance 0-Bit Display Interface AD/PCB PRODUCT DESCRIPTION The purpose of the AD evaluation board is both to demonstrate the performance of the AD and to serve as an implementation example for design and layout. To aid in realworld evaluation, it was designed so that it could be connected as easily as possible into another PC board, such as a graphics controller board. This board is for IC device evaluation purposes only. Analog Devices does not recommend using this hardware outside of this stated usage. Further, Analog Devices provides no warranties for use of this equipment beyond the scope of IC device evaluation purposes. REQUIREMENTS ANALOG FLAT PANEL INTERFACE BOARD The requirements to use the AD evaluation board are a V power supply, graphics signals (through either of the -pin VGA connectors), and a means to program the internal chip registers. Hardware and software for programming the internal chip register are provided Figure. Board Shown in Centimeters Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 0, Norwood, MA 00-0, U.S.A. Tel: Fax:.. 00 Analog Devices, Inc. All rights reserved.

2 AD/PCB TABLE OF CONTENTS Evaluation Board Hardware... Typical Configuration... Power... Programming the Internal Chip Registers... Evaluation Board Software... Settting up the Software... AD Software Control... Sample Settings for The Evaluation Board... Schematics and Layout... Ordering Information... Bill of Materials... Ordering Guide... Contact Information... ESD Caution... REVISION HISTORY /0 Revision 0: Initial Version Rev. 0 Page of

3 AD/PCB EVALUATION BOARD HARDWARE TYPICAL CONFIGURATION In most cases, this evaluation board is used to digitize analog RGB graphics signals and pass the data to another board. To do this, connect the graphics signals to the -pin VGA connector, supply V to the board, and program the internal serial register. The digitized data, generated clock signals, and control signals are passed off the board through the right-side connector. POWER The AD evaluation board contains two. V voltage regulators and an adjustable regulator set for. V. These regulators supply power to the AD. The three regulators provide power to the three power supplies on the AD (refer to the AD data sheet). The best performance can be obtained from the AD when the analog supply (VD) and the PLL (PVD) supply have their own regulators separate from the primary. V supply (VDD). The three regulators work nominally when supplied with V, but work with a range of voltages. Power is applied to the board through the right-side connector (Pins of J). Typically, power is supplied from another board. In the AD evaluation kit, V is supplied by the 0-bit display interface board. PROGRAMMING THE INTERNAL CHIP REGISTERS Hardware and software for programming the AD internal registers are provided. The hardware consists of a standard printer cable and a receiver chip located on the panel driver board. The programming signals come onto the AD evaluation board through Pins and on Connector J. The software is included on the installation CD and is described in the Evaluation Board Software section. Rev. 0 Page of

4 AD/PCB EVALUATION BOARD SOFTWARE SETTTING UP THE SOFTWARE The display electronics product line (DEPL) evaluation software is a Visual Basic program requiring Windows, or later. It is on a self-installing CD package included with the evaluation board. When performing the software install, always use the most recent Windows files (DLL or OCX, for example) if prompted by the install software (these files may already be on your system). The AD register setup screen (similar to the DEPL Evaluation Software AD register setup window in Figure ) should be displayed at program execution after a successful installation. The DEPL evaluation software can control any of the DEPL ADx or ADx devices. It can also read and write to the 0-bit display interface board and includes useful tools such as a PLL Divisor calculator. Figure. DEPL Evaluation Software AD Register Setup Window Rev. 0 Page of

5 AD/PCB AD SOFTWARE CONTROL To select the AD as the target device for the DEPL evaluation software, select Device > AD. This displays the DEPL Evaluation Software AD register setup window, as shown in Figure. From this window you can control every bit within the AD. A detailed, bit-by-bit functional description is provided in the AD data sheet. To update the registers in the AD, click Load at the top of the window. This is true unless Load Register On Change is checked. In this case, the appropriate register is updated as soon as any change is made in the window. The five tabs in this control window enable you to display groups of registers. The selections are 00-0, -, -, or -0. Click the appropriate tab to view/control the register desired. PLL Settings The PLL settings are in Registers 0x0 to 0x0. The PLL Divisor setting ( bits) can be set bit-by-bit (the value toggles when clicking on the bit) by setting a value for Registers 0x0 and 0x0 (decimal value), by setting the -bit value (decimal value), or by moving the control bar left (to decrease) or right (to increase). When changing the value using one of these methods, the change is reflected in the other three. The values are not written to the AD until you click Load. The VCO Range and Charge Pump settings in Register 0x0 can be set by individual bit, by register, or by pull-down menu selection. The -bit Phase Adjust in Register 0x0 can be altered in the some manner as the PLL Divisor. Table contains example PLL register settings for various video modes. For PLL settings not included here, an Excel spreadsheet for calculating PLL settings can be accessed under the Design Tools section of the Analog Devices Display Electronics web site at Gain and Offset Settings The -bit gain control for the red, green, and blue video channels are contained in Registers 0x0 to 0x0A and can be changed bit-by-bit, by setting a value for the registers (decimal value), or by moving the control bar left (to decrease) or right (to increase). The -bit offset control for the red, green, and blue channels are contained in Registers 0x0B to 0x0. These can be set in the same manner as gain. Note that using the gain and offset control bars at the top of their respective sections changes all three channels by the same amount, regardless of their setting. In other words, if, in order to achieve color balance, your offset settings are 0, 0, and 0 for R, G, and B, respectively, the minimum settings are 0, 0, and 0. The maximum offset settings would then be 0,, and. To control the gain or offset of an individual channel, separate control bars for each color are also provided. Sync Separator Control Register 0x contains bits for setting the Sync Separator Threshold. The threshold can be changed bit-by-bit by setting a value for the register (decimal value), or by moving the control bar left (to decrease) or right (to increase). The resulting state of the register is reflected in the box to the right. Sync Control Registers 0x to 0x contain bits for controlling input and output Hsync and Vsync signals. You can toggle each bit by clicking on it. The resulting state of the bit is reflected in the box to the right of each bit. The HSOUT and VSOUT (if enabled) pulse widths can also be adjusted using the control bar to the right of their respective registers. Coast and Clamp Control Pre-Coast, Post-Coast, various Coast and Clamp controls, and Clamp Placement and Duration are controlled via Registers 0x to 0xB. You can toggle each bit by clicking on it. The resulting state of the bit is reflected in the box to the right of each bit. The pre- and post-coast as well as the Clamp Placement and Duration registers can also be controlled via the sliding bar to the right of their respective registers. Auto-Offset Control Register 0xB contains bits for controlling the auto-offset function. You can toggle each bit by clicking on it. The resulting state of the bit is reflected in the box to the right of each bit. For more details on this function, the application note Implementing the Auto-Offset Function of the AD can be downloaded from our web site. This information can also be found in the AD data sheet. SOG Control and Power Management Registers 0xD and 0xE contain bits for controlling the SOG, Input Selection,m and Power Management functions. You can toggle each bit by clicking on it. The resulting state of the bit is reflected in the box to the right of each bit. Output Control Registers 0x and 0x0 contain bits for controlling Output functions. You can toggle each bit by clicking on it. The resulting state of the bit is reflected in the box to the right of each bit. The Output Mode bits also have pull-down menus that can be used for output mode selection. Sync Pulse Filter Control Registers 0x to 0x contain the bits for controlling Sync Pulse Filter. These controls can be modified bit by bit, by changing the -bit (decimal) value or by using the slider bar to the right of each register. Rev. 0 Page of

6 AD/PCB Status Registers (Read-Only) Registers 0x to 0x are read-only registers that provide status for Hsync, Vsync, and SOG Detection (0x), Hsync, Vsync, Coast, and Clamp Polarity (0x), and the Hsync per Vsync Counter (0x to 0x). Performing a read (by clicking Read) lets you see the status of each of these bits. The status is also reflected in the text to the right of each of these bits. SAMPLE SETTINGS FOR THE EVALUATION BOARD Table. Sample Settings Mode Resolution Nominal Frequency Hs (khz) Nominal Pixel Clock (MHz) PLL Divider PLL Settings VCO Range (0x0 :) Charge Pump Current (0x0 :) VGA 0 0 at 0 Hz at Hz at Hz at Hz SVGA at Hz at 0 Hz at Hz at Hz at Hz XGA 0 at 0 Hz at 0 Hz at Hz at 0 Hz at Hz SXGA 0 0 at 0 Hz TV 0i p p i Hz The VCO Range and Charge Pump Current settings are preliminary and may need slight adjustments. ADC Setting Latch Select (0xD :) Rev. 0 Page of

7 AD/PCB SCHEMATICS AND LAYOUT J 0 J 0 TP TP TP VSY0 HSY0 BV0 GV0 RV0 FB FB FB TP VSY HSY BV GV RV FB FB FB NOTE: LABEL ALL TEST POINTS WITH THE APPROPRIATE NET NAME. HSY0 HSY VSY0 VSY W HSY W VSY R Ω BLU0 GRN0 RED0 R Ω R Ω R Ω BLU GRN RED R Ω R Ω C nf C C nf nf C C nf nf C0 C nf nf C nf BIN0 BIN GIN0 SOGIN0 GIN SOGIN RIN0 RIN REFLO REFCM REFHI 0 0 BAIN0 BAIN GAIN0 SOGIN0 GAIN SOGIN RAIN0 RAIN PWRDN/TRI-ST REFLO REFCM REFHI U AD ;,,,,,, 0,,,,, 0 VD;,,, OVDD;,,, PVD;,,, TP TP TP TP TP R 0kΩ RED_DATA_A[0:] DATA_CLOCK SOG_OUT HS_OUT VS_OUT ODD_EVEN~ PWRDN CON-HD-HF CON-HD-HF [:] DATACK SOGOUT HSOUT VSOUT/A0 O/EFIELD RED[0:] FILT CLAMP EXTCLK/COAST VSY0 HSY0 VSY HSY SCL SDA PVD R kω C 0.0µF C 0.00µF C 0.µF C C 0.µF 0.µF R.kΩ HSY VSY HSY0 VSY0 BLUE[0:] GREEN[0:] R kω [:] [:] R kω SCL SDA CLAMP COAST BLUE_DATA_A[0:] GREEN_DATA_A[0:] Figure. Rev. 0 Page of

8 AD/PCB Rev. 0 Page of VSY_OUT HSY_OUT SOG DATA_CLOCK_OUT DATA_CLOCK SOG_OUT HS_OUT VS_OUT RP RP RP RP RED_DATA_A GREEN_DATA_A BLUE_DATA_A BLUE_DATA_A0 RED_OUT_A GREEN_OUT_A BLUE_OUT_A BLUE_OUT_A0 RED_DATA_A GREEN_DATA_A BLUE_DATA_A BLUE_DATA_A RED_OUT_A GREEN_OUT_A BLUE_OUT_A BLUE_OUT_A RED_DATA_A GREEN_DATA_A GREEN_DATA_A0 BLUE_DATA_A RED_OUT_A GREEN_OUT_A GREEN_OUT_A0 BLUE_OUT_A RED_DATA_A GREEN_DATA_A GREEN_DATA_A BLUE_DATA_A RED_OUT_A GREEN_OUT_A GREEN_OUT_A BLUE_OUT_A RED_DATA_A RED_DATA_A0 GREEN_DATA_A BLUE_DATA_A RED_OUT_A RED_OUT_A0 GREEN_OUT_A BLUE_OUT_A RED_DATA_A RED_DATA_A GREEN_DATA_A BLUE_DATA_A RED_OUT_A RED_OUT_A GREEN_OUT_A BLUE_OUT_A RED_DATA_A GREEN_DATA_A BLUE_DATA_A RED_OUT_A GREEN_OUT_A BLUE_OUT_A RED_DATA_A GREEN_DATA_A BLUE_DATA_A RED_OUT_A GREEN_OUT_A BLUE_OUT_A RA GREEN_DATA_A[0:] RED_DATA_A[0:] BLUE_DATA_A[0:] Figure.

9 AD/PCB VCC VCC VCC C µf C µf C µf U ADP0-V NR IN OUT ERR SD U ADP0-V NR IN OUT ERR SD IN U ADP OUT FB SD C C C C 0.µF 0.µF 0.µF + C µf 0.µF C0 C C C 0.µF 0.µF 0.µF + C µf 0.µF.V R.kΩ + C µf C 0.µF C 0.µF C0 C 0.µF 0.µF VD OVDD PVD R0 kω TB X X VCC PR PR PR PR BLUE_OUT_A0 BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A BLUE_OUT_A GREEN_OUT_A0 GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A GREEN_OUT_A RED_OUT_A0 RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A RED_OUT_A DATA_CLOCK_OUT SOG HSY_OUT VSY_OUT ODD_EVEN~ DIG_DE CTL0 CTL NOTE: PINS,,,,,, AND ARE NOT DEFINED. VCC SCL SDA COAST CLAMP MOLEX_-00 J DATA_CLOCK_OUT CLOCK_INVERT HSY VSY PWRDN CTL CTL Figure. Rev. 0 Page of

10 AD/PCB Figure Figure Figure. Figure. Rev. 0 Page 0 of

11 ORDERING INFORMATION BILL OF MATERIALS Table. AD/PCB L/I QTY REFDES Description Part No. Mfgr. Dist. Dist. Part No. Sub? C, C µf, V, ALUM, ELECTRO, 'D' ECE-VCA0SP PANASONIC DIGIKEY PCECT-ND Y C C, C, C C,. µf, V, XR, 00, CER ECJ-VBE0K PANASONIC DIGIKEY PCCCT-ND Y C C, C, C, C0 C C, C C µf,. V, ALUM, ELECTRO ECE-V0JA0SR PANASONIC DIGIKEY PCE0CT-ND Y C C, C, C.0 µf, 0 V, XR, 00, CER ECJ-YBHK PANASONIC DIGIKEY PCCCT-ND Y C0, C.00 µf, 0 V, NPO, 00, CER ECU-VH0KBN PANASONIC DIGIKEY PCC0BT-ND Y C.0 µf, 0 V, XR, 00, CER ECJ-YBHK PANASONIC DIGIKEY PCCCT-ND Y C 00 pf, 0 V, XR, 00, CER ECU-VHKBG PANASONIC DIGIKEY PCCBT-ND Y FB FB 0 MHz BEAD, 00 00Z0 FAIR-RITE ALLIED -0 N J, J -PIN D-SUB CONN -0-- NORCOMP DIGIKEY RF-ND N 0 J 00-PIN MATED CONNECTOR -00 MOLEX FORCE -00 N R.0 kω, %, /0W 00 ERJ-ENF0V PANASONIC DIGIKEY P.0KCCT-ND Y R R.0 Ω, %, /0W 00 ERJ-ENFR0V PANASONIC DIGIKEY P.0CCT-ND Y R, R, R.00 kω, %, /0W 00 ERJ-ENF00V PANASONIC DIGIKEY P.00KCCT-ND Y R. kω, %, /0W 00 ERJ-ENFV PANASONIC DIGIKEY P.KCCT-ND Y R0 kω, %, /0W 00 ERJ-ENFV PANASONIC DIGIKEY PKCCT-ND Y R, R 0 Ω, %, /0W 00 ERJ-ENF00V PANASONIC DIGIKEY P0CCT-ND Y R0, R.00 kω, %, /0W 00 ERJ-ENF00V PANASONIC DIGIKEY P.00KCCT-ND Y RA Ω RPAK, /W, %, RES C00J CTS DIGIKEY C00JCT-ND Y RP, RP, RP, RP Ω RPAK, /W, %, RES C0J CTS DIGIKEY C0JCT-ND Y 0 TB NOT POPULATED U IC,0-BIT CONVERTER AD ADI ADI AD N U, U IC,. V REGULATOR ADP0AR-. ADI ADI ADP0AR-. N U IC, VAR REGULATOR ADP ADI ADI ADP N N/A PC BOARD GSO ADI PCSM GSO N N/A SCREW -0 X /" FOR J, J SPC NEWARK G Y N/A -0 HEX NUT FOR J, J SPC NEWARK F0 Y W, W -PIN HEADER 0-TN M MOUSER 0-TN Y ORDERING GUIDE Model AD/PCB Package Description Evaluation Board CONTACT INFORMATION Questions? Please us directly at flatpanel_apps@analog.com, visit our web site at or call the Analog Devices help line at -00-AnalogD. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V re adily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 Page of

12 AD/PCB NOTES 00 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB00 0 /0(0) Rev. 0 Page of