PCB Layout and Design Considerations for the CH7301C DVI Output Device

Transcription

1 Chrontel Application Notes PCB Layout and Design Considerations for the CH70C DVI Output Device. Introduction This application note focuses on basic PCB layout and design guidelines for the CH70C DVI Output Device. Guidelines in component placement, power supply decoupling, grounding, input signal interface and video components for DVI link implementation, are discussed in this document. The guidelines discussed here are intended to optimize the PCB layout and applications for this product. They are only for reference. Designers are urged to implement the configurations and evaluate the performance of the system prior to bringing the design to production. The discussion and figures that follow reflect and describe connections based on the -pin LQFP package of CH70C. Please refer to CH70C data sheet for the details of the pin assignments.. Component Placement and Design Considerations Components associated with the CH70C DVI transmitter should be placed as close as possible to the respective pins. The following discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement and layout of components associated with these pins.. Power Supply Decoupling The optimum power supply decoupling is accomplished by placing a 0.µF ceramic capacitor to each of the power supply pins as shown in Figure. These capacitors (C7, C8, C9, C, C, C, C7) should be connected as close as possible to their respective power and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the decoupling capacitors to the CH70C ground pins, in addition to ground vias... Ground Pins The analog and digital grounds of the CH70C should connect to a common ground plane to provide a low impedance return path for the supply currents. Whenever possible, each of the CH70C ground pins should connect directly to its respective decoupling capacitor ground lead, then connect the ground plane through a ground via. Short and wide traces should be used to minimize the lead inductance. See Table for the ground pins assignment... Power Supply Pins Separate digital (including the I/O supply voltage DVDDV), DVI, Analog, and DAC power planes are recommended. See Table for the Power supply pins assignment. Table : Power Supply Pins Assignment in CH70C Pin # # of Pins Type Symbol Description,, 9 Power DVDD Digital Supply Voltage (.V),, Power D Digital Ground Power DVDDV I/O Supply Voltage (.V to.v), 9 Power TVDD DVI Transmitter Supply Voltage (.V) 0,, Power T DVI Transmitter Ground 8 Power AVDD PLL Supply Voltage (.V) 7 Power A PLL Ground Power VDD DAC Supply Voltage (.V), 0 Power DAC Ground Rev.. 7//0

2 DVDDV & VREF Decoupling and Connection VREF is used as a reference level for pixel data input D[:0], HSY input and VSY input. Please refer to Figure for optimum decoupling. In general applications, VREF is derived from DVDDV divided by, i.e., VREF = / x DVDDV. Therefore, in Figure, both resistors should have the same value (Ω@ %). The decoupling capacitor is required as shown in Figure. Also, the DVDDV voltage supply should be connected to the graphics controller I/O supply voltage. Figure : Power Supply Decoupling and Distribution Notes: All the Ferrite Beads described in this document are recommended to have an impedance of less then 0.0Ω at DC; Ω at MHz & 7Ω at 00MHz. Please use Fair_Rite part# 7097 or an equivalent ferrite bead Rev.. 7//0

3 NI: Not Installed VCC _ (+.V) NI NI NI VCC VGA_Interface GPIO[:0] are general purpose I/O pins. In this case they are configured as inputs and are pulled to "low". R, R and R are not installed. For more information concerning the use of GPIO[:0], please refer to register Eh of the CH70C datasheet. R R R R R 7 C 0.uF 8 C 0.uF 0 GPIO[] DVDDV VREF GPIO[0] ISET CH70C -pin LQFP AS R8 0 R9 R7 C 0.uF R C 0.uF Figure : ISET, VREF, DVDDV, GPIO and AS connection. General Control ISET pin The ISET pin, pin, sets the DAC current. A 0Ω resistor should be placed as close as possible to the ISET pin using short and wide traces. Whenever possible, the ISET resistor ground pin should also be connected to pin. Otherwise, the ground reference of the ISET resistor should ideally be close to the CH70C. See Figure for design reference. Data Enable pin The Data Enable pin, pin, is an input pin and accepts the Data Enable signal from the VGA graphics chipset. Active video data is indicated when the VGA drives the Data Enable signal high. When the Data Enable signal is low, the video data will not be encoded and driven out of the DVI interface. The voltage levels are between 0V and DVDDV, and the VREF signal is used as the threshold level. GPIO [0] & GPIO[] pins GPIO[:0] are General Purpose I/O pins. To set the direction of these pins, register Eh, the GPIO Control Register must be set accordingly. The GPIO[] pin can be configured as an output for the DVI link detect signal. In this configuration, this pin will be driven low when a termination change has been detected on the HPDET input. AS pin The Address Select pin, pin 0, can be configured as shown in Figure. This pin determines the serial port address of the device. If AS is pulled low, then the serial port address is 0x7h, if AS is pulled high, then the serial port address is 0x7h. Note: To use the Intel driver for the CH70C, the AS pin must be pulled low Rev.. 7//0

4 Video Inputs (D[:0]) Since the digital pixel data and the pixel clock of the CH70C may toggle at speeds up tomhz (depending on the input mode), it is critical that the connection of these video signals between the graphics controller and the CH70C be kept short and isolated as much as possible from the analog outputs and analog circuitry. For optimum performance, these signals should not overlay the analog power or analog output signals. The DATA signals are single ended high speed signals that should be routed together as a bus. It is recommended that 8 mil traces be used in routing these signals.. Serial Port Interface SPD and SPC pins SPD (pin ) and SPC (pin ) function as a serial interface where SPD is bi-directional data and SPC is an input only serial clock. In the reference design, SPD and SPC are pulled up with. KΩ resistors..v CH70C SPD SPC R.k R.k SPD SPC. DVI Output and Control Figure : Serial Port Interface In DVI output mode, the multiplexed input data, sync and clock signals are input to the CH70C from the graphics controller s digital output port. Data will be X multiplexed, and the clock inputs can be X or X times the pixel rate. For correct DVI operation, the input data format must be selected to be one of the RGB input formats. The TDC0, TDC, TDC & TLC signals are high frequency differential signals that need to be routed with special precautions. Since the TDC0, TDC, TDC & TLC signals are differential they must be routed in pairs: TDC0 & TDC0*, TDC & TDC*, TDC & TDC*, TLC & TLC* signals. The lengths of the pair of signals must be kept as close to the same as possible. The maximum length difference must not exceed 00 mils for any of the pairs relative to each other. The number of bends should be kept to or less and degree is the maximum corner angle. These signals should be routed on the top layer directly to the DVI connector without any vias to the bottom layer. The pin placement of the TDC0, TDC, TDC & TLC signals allows for a direct route to the DVI connector. The CH70C is able to drive a DVI display at a pixel rate of up to MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device. In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each DVI Output (data and clock). International standard EN 0:998 establishes kv as the common immunity requirement for contact discharges in electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic systems. International standard EN 000--:99 / IEC 000--:99 establishes the immunity testing and measurement techniques. System level ESD testing to International standard EN 000--:99 / IEC 000--:99 has confirmed that the proper implementation of Chrontel's recommended diode protection circuitry, using Semtech RClamp 0M or Rev.. 7//0

5 R B Semtech RClamp 0P diode array devices, will protect the CH70C DVI output from DVI panel discharges of greater than 8kV (contact) and kv (air). Both Semtech RClamp devices have low I/O to I/O capacitance. (RClamp 0M = 0.7pF typical and RClamp 0 = 0.pF typical). This low capacitance will allow the DVI eye diagram to remain within specification. System level ESD testing to International standard EN 000--:99 / IEC 000--:99 has also confirmed that BATSLT diode device can protect pin 9 (HPDET) of the CH70C from DVI panel discharges greater than kv (contact) and 8kV (air). It is also highly recommended to protect the DDCCLK and DDCDATA signals on the DVI connector. Figure shows an example of the connection of the DVI output. In the figure a DVI-I Right Angle Connector is used to interface the CH70C DVI outputs to the monitor. TDC# TDC TDC# R C R +.V R 0 C8 0.uf U 0 Line 9 Line 8 VCC 7 Line Line Semtech RClamp 0 DDCCLK DDCDATA +.0V CR +.0V CR CON DATA DATA SHIELD DATA DATA 7 DDCCLK 8 DDCDATA 9 Vsync 0 DATA DATA SHIELD DATA DVI-I DATA VCC HPDET 7 DATA0 8 DATA0 9 SHIELD0 0 DATA DATA SHIELDCLK CLK CLK C 0.uf R +.0V C7 0uf 0K.V CR C9 0.uf R 7K HPDET TDC C0 7 MONVSY 7 MONRED 7 MONGREEN 7 MONBLUE 7 MONHSY G Hsync A C C C C C TLC# TLC TDC0 R7 C R9 +.V R8 0 C 0.uf U Line VCC Line 0 9 Line 8 7 Line C Semtech RClamp 0 TDC0# EMI Stuffing Options: A ohm and DVI output bridge circuit can be used further suppress electromagnetic emissions. ESD Protection Diodes Low capacitance, high speed ESD Protection Diodes for the DVI output is highly recommended. The Semtech 0 is shown above. CH70C Reference Schematic Title DVI Output Size Document Number Rev B Date: Monday, July, 0 Sheet of 7 Figure : DVI-I Output Connection DVI Link Detect Output (HPINT) (internal pull-up) The GPIO[]/HPINT pin can be used to output the DVI link detect signal (pulls low when a termination change has been detected on the HPDET input). This is an open drain output. To configure the GPIO[]/HPINT pin to function as a HPINT, the GOENB ( reg Eh[7] ) and HPIE ( reg 0h[7] ) bits of the CH70C must be set to. The HPINT function will pull low with an open drain output following a transition on the HPDET input. DVI Data Channel (TDC[:0] and TDC[:0]*) These pins (Pins 8,, for TDC[:0] and Pins 7,, for TDC[:0]*) provide the DVI differential outputs for data channel 0 (blue), channel (green) and channel (red) (See Figure ) Rev.. 7//0

6 DVI Link Clock Outputs (TLC and TLC*) These pins (Pins 0, ) provide the DVI differential clock outputs for the DVI interface corresponding to data on the TDC[:0] outputs (See Figure ). HPDET (DVI Hot Plug Detect) This input pin (Pin 9) determines whether the DVI link is connected to a DVI monitor. When terminated, the monitor is required to apply a voltage greater than. volts. Changes on the status of this pin will be relayed to the graphics controller via the GPIO[]/HPINT pin pulling low (See Figure ). VSWING (DVI Link Swing Control) This pin (Pin 9) sets the swing level of the DVI outputs. A.KΩ resistor should be connected between this pin and using short and wide traces.. Analog RGB Output The R, G, B (pins 8, 7, 9) signals are analog video signals. These signals should not be routed together. There should be a minimum of mils spacing between each of the R, G, B signals and 0 mils spacing between them and any digital trace. Typically these signals should be routed in a separate analog area without any digital signal running through the area. Corners for these traces should be at a maximum of degree. 90 degree corners should not be used due to cross coupling between adjacent traces. These traces should be kept on the top layer to minimize the use of vias on them. In order to minimize the hazard of ESD, it is highly recommended to use ESD protection diodes for each of the Analog RGB signals. In Figure, the input protection diodes D - D should be placed as close to the DVI connector as possible and the series termination resistors R-R should be placed as close to the CH70C as possible. If the analog outputs of the DVI-I connector are to be used, the ferrite beads L-L8 should be placed as close to the DVI-I connector as possible to reduce EMI emissions Rev.. 7//0

7 . Reference Design Example The following schematics are based on an Intel i8 / i8 / i8 Graphics chipset design and are to be used as a CH70C PCB design example only. It is not a complete design. Those who are seriously doing an application design with CH70C and would like to have a complete reference design schematic, should contact Applications within Chrontel, Inc.. Schematics of Reference Design Example Rev.. 7//0 7

8 Keep these traces short and straight (top layer only with gnd on layer ). Route trace as 0 ohm line D D0 D9 D8 D7 D D D D D D D0 XCLK* XCLK DE H V RESET* SPD SPC GPIO/HPINT GPIO0 AS HPDET VSY HSY TDC0* TDC0 TDC* TDC 7 TDC* 8 TDC TLC 0 TLC* BCINTR# VrefGC.V R 8.k().V R 8.k() R 0 R 0.V TDC0# TDC0 TDC# TDC TDC# TDC TLC TLC# CVBS Y C R 8.k(),, XCLK# XCLK DE H V RST# ICDATA_T ICCLK_T D[..0] IC Address = 00X D D0 D9 D8 D7 D D D D D D D0 U TEST DVDD0 DVDD DVDD D0 D D DVDDV TVDD0 TVDD T0 T T AVDD0 G 7 R 8 B C 0.uf C 0.uf C 0.uf C 0.uf C 0.uf C 7uf/0uf C7 7uf/0uf L BEAD.V 7uf/0uf implies use either value. L BEAD.V.V HPDET ISET A 9 R VSWING VDD 0 C9 C0 R7 R8 0 0.uf() 0.uf() 0.K VREF Empty Empty CH70C 7.V L BEAD 0 C8 C 0.uf 7uf/0uf.V R9 () R0 () C 0.uf C 7uf/0uf L BEAD.V AGP_VREF R 0 C 0.uf Title CH70C Reference Schematic CH70C Size Document Number Rev B Friday, September, 009 Date: Sheet of Rev.. 7//0

9 CR CR.V R C CR TDC# TDC TDC# TDC TLC# TLC TDC0 TDC0# R C0 R7 C R9 C +.V R 0 C8 0.uf U Line VCC Line 0 Line Line Semtech RClamp 0 +.V R8 0 C 0.uf U Line VCC Line 0 Line Line Semtech RClamp 0 EMI Stuffing Options: A ohm and DVI output bridge circuit can be used further suppress electromagnetic emissions. DDCCLK DDCDATA +.0V +.0V 7 MONVSY 7 MONRED 7 MONGREEN 7 MONBLUE 7 MONHSY ESD Protection Diodes Low capacitance, high speed ESD Protection Diodes for the DVI output is highly recommended. The Semtech 0 is shown above CON DVI-I DATA DATA DATA VCC SHIELD DATA HPDET DATA DATA0 DDCCLK DATA0 DDCDATA SHIELD0 Vsync DATA DATA DATA DATA SHIELDCLK SHIELD CLK DATA CLK V C 0.uf C7 0uf R 0K C9 R 0.uf 7K Title CH70C Reference Schematic DVI Output Size Document Number B Date: Monday, July, 0 Sheet of C C C C C R G B Hsync A Rev.. 7//0 9

10 C 0.uf D[..0] XCLK H, MIC_CLK, MIC_DATA ID0 ID ID ID AGP_VREF D0 D8 D D D D0 +.0V.V.V B B B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B7 B8 B9 B0 B B B B B B B7 B8 B9 B0 B B B B B B CON V A A.0V TYPEDET A.0V A A A A7 RST# A8 A9 VCC. VCC. A0 A A NA A A A ADD_ID0 ADD_ID A VCC. VCC. A7 ADD_ID ADD_ID A8 A9 A0 ADD_ID ADD_ID A ADD_ID ADD_ID7 A A A.VAUX A VCC. VCC. A DVOC_FLD/STL DVOBC_INTR# A7 DVOC_D0 DVOC_D A8 VCC. VCC. A9 DVOC_D8 DVOC_D9 A0 DVOC_D DVOC_D7 A A DVOC_CLK DVOC_CLK# A DVOC_D DVOC_D A VDDQ. VDDQ. A DVOC_D DVOC_D A DVOC_D0 DVOC_D A7 A8 DVOC_HSY DVOC_BLANK# A9 DVOC_VSY A0 VDDQ. VDDQ. A M_ICCLK M_DVI_DATA A M_ICDATA M_DVI_CLK A7 VDDQ. M_DDCDATA A8 A9 A0 ADD_DETECT A DVOB_BLANK# M_DDCCLK A VDDQ. VDDQ. A DVOB_FLD/STL DVOBC_CLKINT A DVOB_D0 DVOB_D A A DVOB_D8 DVOB_D9 A7 DVOB_D DVOB_D7 A8 VDDQ. VDDQ. A9 DVOB_CLK DVOB_CLK# A0 DVOB_D DVOB_D A A DVOB_D DVOB_D A DVOB_DO DVOB_D A VDDQ. VDDQ. A DVOB_VSY DVOB_HSY A VREFCG VREFGC.V.V D D9 D7 D D D R0 0 ID ID ID ID7 RST# BCINTR# XCLK# DE V MDDC_DATA MDDC_CLK POUT/DET# VrefGC R9 8.k() R 8.k() ADD ID Selector Stuff No Stuff.V R R7 R R9 8.K R8 R R0 R ID7 R ID R ID R ID R ID R 0 ohms ID R7 ID R ID0 R8 Default ID < ID[7:0] > : V Title CH70C Reference Schematic DVO/AGP Size Document Number Rev B. Friday, September, 009 Date: Sheet of Rev.. 7//0

11 Q N700LT Q N700LT Q N700LT Q N700LT ICDATA_P ICCLK_P Title CH70C Reference Schematic LS/Config.ROM Size Document Number Rev B. Friday, September, 009 Date: Sheet of Level Shifting MDDC_DATA MDDC_CLK, MIC_DATA, MIC_CLK R k R8 k.v R k.v R9 k.v R R.7k.k R.k R0.k +.0V R7.k.V R.k DDCDATA DDCCLK ICDATA_T, ICCLK_T, Config. ROM To Write Protect PROM, stuff resistor..v U A0 VCC A WP A SCL VSS SDA C R C 0() 0.uf ICCLK_P ICDATA_P Rev.. 7//0

12 . Revision History Revision Date Section Description.0 8/8/0 All First official release, Revision.0. 9//09 All Updated ESD related information. 7// Page,9 Modified the circuitry of HPDET Rev.. 7//0

13 Disclaimer This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel 0 O Toole Avenue, Suite 00, San Jose, CA 9- Tel: (08) 8-98 Fax: (08) sales@chrontel.com 0 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A Rev.. 7//0