EVALUATION KIT AVAILABLE High-Bandwidth, VGA 2:1 Switch with ±15kV ESD Protection

Transcription

1 19-5; Rev ; 1/9 EVALUATION KIT AVAILABLE High-Bandwidth, VGA :1 Switch General Description The integrates high-bandwidth analog switches, level-translating buffers, and level-translating FET switches to implement a complete :1 multiplexer for VGA signals. The device provides three very highfrequency 9MHz (typ) SPDT switches for RGB signals, two low-frequency clamping switches for the DDC signals, a pair of level-translating buffers for the H_ and V_ signals, and integrated extended ESD protection. Horizontal and vertical synchronization (H_/V_) inputs feature level-shifting buffers to support low-voltage controllers and standard 5V-TTL-compatible monitors, meeting the VESA requirement. Display Data Channel (DDC), consisting of SDA_ and SCL_, are FET switches that protect the low-voltage VGA source from potential damage from high-voltage presence on the monitor while reducing capacitive load. All seven output terminals of the feature high-esd protection to Q15kV Human Body Model (HBM) (see the Pin Description). All other pins are protected to QkV Human Body Model (HBM). The is specified over the extended -4NC to +85NC temperature range, and is available in a spacesaving, 8-pin, 4mm x 4mm TQFN package. Features S Low 5I (typ) On-Resistance (R_, G_, B_ Signals) S Low 5.5pF (typ) On-Capacitance (R_, G_, B_ Signals) S Independent, Selectable Logic Inputs for Switching S Similar Pin Configuration to MAX4885 S Ultra-Small, 8-Pin (4mm x 4mm) TQFN Package S Q15kV ESD HBM Ordering Information PART TEMP RANGE PIN-PACKAGE ETI+ -4NC to +85NC 8 TQFN-EP* +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Typical Operating Circuit +.V +5V 1μF V CC 1μF Applications Notebook Computer MXM/Switchable Graphics KVM for Servers MXM MODULE R1, G1, B1 R, G, B H1, V1 H, V SDA1, SCL1 SDA, SCL VGA PORT INTERNAL GRAPHICS R, G, B H, V SDA, SCL CPU SEL1 SEL GND Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 High-Bandwidth, VGA :1 Switch ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND unless otherwise noted.) V CC...-.V to +6V... -.V to (V CC +.V) R_, G_, B_, H, V, SDA, SCL... -.V to (V CC +.V) H1, H, V1, V, SDA1, SDA, SCL1, SCL, SEL1, SEL... -.V to ( +.V) Continuous Current through R_, G_, B_ Switches... Q5mA Continuous Current through SDA_, SCL_ Switches... Q5mA Continuous Current into SEL1, SEL, H1, H, V1, V... QmA Peak Current through all Switches (pulsed at 1ms, 1% duty cycle)... Q1mA Continuous Power Dissipation (T A = +7NC) 8-Pin TQFN (derate 8.6mW/NC above +7NC) mW Junction-to-Ambient Thermal Resistance (B JA ) (Note 1) 8-Pin TQFN...5NC/W Junction-to-Case Thermal Resistance (B JC ) (Note 1) 8-Pin TQFN...NC/W Operating Temperature Range... -4NC to +85NC Storage Temperature Range NC to +15NC Junction Temperature NC Lead Temperature (soldering, 1s)...+NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V CC = +4.5V to +5.5V, = +.V to V CC, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC V Logic Supply Voltage VL P V CC +. V CC V V CC Supply Current I CC V CC = +5.5V, = +.6V, SEL_ = H1 = H = V1 = V = GND Supply Current I L V CC = +5.5V, = +.6V, SEL_ = H1 = H = V1 = V = GND ANALOG SWITCHES 5 FA 1 FA On-Resistance (R_, G_, B_) R-HF- ON VIN = +.7V, I IN = Q1mA 5 8 I On-Resistance Match (R_, G_, B_) On-Resistance Flatness (R_, G_, B_) DR ON P V IN P +.7V, I IN = -1mA 1 I R FLAT(ON) P VIN P +.7V, I IN = -1mA.5 1 I Off Leakage Current (R_, G_, B_) I OFF V R_, V G_, V B_ = V or V CC FA On-Resistance (SDA_, SCL_) R-DDC ON VIN = +.7V, I IN = Q1mA 15 I Off-Leakage Current (SDA_, SCL_) I OFF V SDA_, V SCL_ = V or, V CC = = +5V FA

3 High-Bandwidth, VGA :1 Switch ELECTRICAL CHARACTERISTICS (continued) (V CC = +4.5V to +5.5V, = +.V to V CC, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SEL_, H1, H, V1, V) Input Threshold Low V IL.5 x V Input Threshold High V IH.55 x Input Hysteresis V HYST 1 mv Input Leakage Current I L FA SEL_ Enable/Disable Time t ON, t OFF RL =.ki, C L = 1pF, Figure 1 ns DIGITAL OUTPUTS (H, V) Output-Voltage Low V OL I OUT = 8mA, V CC = +4.5V.8 V Output-Voltage High V OH I OUT = -8mA, V CC = +4.5V.4 V Rise/Fall Time t R, t F RL =.ki, C L = 1pF, Figure 8 ns RGB AC PERFORMANCE Bandwidth f MAX RS = R L = 5I 9 MHz On-Loss I LOSS f = 1MHz, R S = R L = 5I, P V P +.7V, Figure V.4 db Crosstalk R_, G_, B_ V CT f = 5MHz, RS = R L = 5I, Figure -4 db Off-Capacitance C OFF f = 1MHz, R to R1/R, G to G1/G, B to B1/B (Note ) On-Capacitance C ON f = 1MHz, R to R1/R, G to G1/G, B to B1/B (Note ) ESD PROTECTION.5 pf pf R, G, B, SDA, SCL, H, V V ESD HBM (Notes, ) Q15 kv R, G, B, SDA, SCL, H, V V ESD IEC Contact (Notes, ) Q8 kv All Other Terminals V ESD HBM (Note ) Q kv Note : Guaranteed by design. Not production tested. Note : Tested terminal to GND, 1µF bypass capacitors on V CC and.

4 High-Bandwidth, VGA :1 Switch (V CC = +5.V, = +.V, T A = 5 C, unless otherwise noted.) RON (Ω) R ON vs. V RO * (RGB SWITCHES) *R, G, B ARE INTERCHANGEABLE T A = +85 C V RO (V) T A = +5 C T A = -4 C toc1 RON (Ω) R ON vs. V SDA * (DDC SWITCHES) *SDA, SCL ARE INTERCHANGEABLE = +.V T A = +85 C T A = +5 C T A = -4 C T A = -4 C V SDA (V) Typical Operating Characteristics = +5V T A = +85 C T A = +5 C toc OUTPUT-VOLTAGE HIGH (V) HV BUFFER OUTPUT-VOLTAGE HIGH vs. TEMPERATURE I OUT = 8mA TEMPERATURE ( C) toc OUTPUT-VOLTAGE LOW (V) HV BUFFER OUTPUT-VOLTAGE LOW vs. TEMPERATURE I OUT = 8mA toc4 SUPPLY CURRENT (μa) SUPPLY CURRENT vs. TEMPERATURE I L I CC toc5 ON-RESPONSE (db) ON-RESPONSE vs. FREQUENCY toc TEMPERATURE ( C) TEMPERATURE ( C) FREQUENCY (MHz) CROSSTALK (db) CROSSTALK vs. FREQUENCY FREQUENCY (MHz) toc7 4

5 High-Bandwidth, VGA :1 Switch V V CC SEL1, SEL 5% t OFF 5% 5% t ON R L =.kω C L = 1pF 5% V CC Test Circuits/Timing Diagrams 8% 8% % V H, V t R t F R L =.kω C L = 1pF % V H, V Figure 1. Enable/Disable Time Figure. Rise/Fall Time +.V 1μF +5V 1μF GND OR V CC SEL1, SEL R, G, B R1, G1, B1 R, G, B V IN V OUT MEAS 5Ω NETWORK ANALYZER 5Ω REF INSERTION-LOSS = log( VOUT V IN ) V OUT CROSSTALK = log( V IN ) 5Ω GND 5Ω 5Ω MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. INSERTION LOSS IS MEASURED BETWEEN R AND R1 OR R ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. Figure. Insertion Loss and Crosstalk 5

6 High-Bandwidth, VGA :1 Switch TOP VIEW G1 R1 SCL1 SDA1 GND V CC SEL R B1 G H1 B V1 1 I.C. V H V H B G 1 R SDA SCL *EP SCL SDA V CC SEL Pin Configuration TQFN (4mm 4mm) *EXPOSED PAD. CONNECT TO GROUND OR LEAVE UNCONNECTED. Pin Description PIN NAME FUNCTION 1 R RGB Red Output (Note 4) G RGB Green Output (Note 4) B RGB Blue Output (Note 4) 4 H Horizontal Sync Output (Note 4) 5 V Vertical Sync Output (Note 4) 6 SDA I C Data Output (Note 4) 7 SCL I C Clock Output (Note 4) 8 SEL Select Input. Switches SDA_ and SCL_ signals. 9 Supply Voltage. +.V P VL P V CC. Bypass to GND with a 1FF or larger ceramic capacitor. 1, 7 V CC Supply Voltage. VCC = +5.V Q1%. Bypass V CC to GND with a 1FF or larger ceramic capacitor. 11 SDA I C Input Data (Note 5) 1 SCL I C Input Clock (Note 5) 1 R RGB Red Input (Note 6) 14 G RGB Green Input (Note 6) 15 B RGB-Blue Input (Note 6) 16 H Horizontal Sync Input (Note 7) 17 V Vertical Sync Input (Note 7) 18 I.C. Internal Connection. Connect to ground or leave unconnected. 19 V1 Vertical Sync Input 1 (Note 7) H1 Horizontal Sync Input 1 (Note 7) 1 B1 RGB Blue Input 1 (Note 6) 6

7 High-Bandwidth, VGA :1 Switch PIN NAME FUNCTION G1 RGB Green Input 1 (Note 6) R1 RGB Red Input 1 (Note 6) 4 SCL1 I C Clock Input 1 (Note 5) 5 SDA1 I C Data Input 1 (Note 5) 6 GND Ground 8 SEL1 Select Input 1. Switches R_, G_, B_, H_, and V_ signals. EP Exposed Pad. Connect exposed pad to ground or leave unconnected. Note 4: Terminal with Q15kV HBM protection. Note 5: SCL1, SCL, SDA1, and SDA are identical and can be used interchangeably. Note 6: R1, R, G1, G, B1, and B are identical and can be used interchangeably. Note 7: H1, H, V1, and V are identical and can be used interchangeably. Pin Description (continued) Typical Applications Circuit +.V +5.V.1µF.1µF.kΩ.kΩ SCL SDA H MXM V GRAPHICS R G B.kΩ +.V.kΩ , SCL SDA H V R VGA COMMON OUTPUT SCL SDA H INTERNAL V GRAPHICS R G B , EP 8 8 G B SEL1 SEL NOTE: TWO VIDEO INPUT SOURCES BEING SWITCHED INTO ONE OUTPUT/SINK USING. 7

8 High-Bandwidth, VGA :1 Switch R1 R G1 G B1 B Functional Diagram R G B SCL1 SCL SCL SDA1 SDA SDA H1 H H V1 V V SEL1 SEL CONTROL 8

9 High-Bandwidth, VGA :1 Switch Detailed Description The integrates high-bandwidth analog switches and level-translating buffers to implement a complete :1 multiplexer for VGA signals. The device provides switching for RGB, HSYNC, VSYNC, SDA, and SCL signals. These signals are required in notebook VGA switching applications. The HSYNC and VSYNC inputs feature level-shifting buffers to support 5V-TTL output logic levels from lowvoltage graphics controllers. These buffered switches can be driven from +.V up to +5.5V. RGB signals are routed with high-performance analog switches. SDA_ and SCL_ are IC signals with pullups to their respective voltages. The protects the low-voltage side while effectively translating up to the high-voltage level. Two select inputs are provided to individually select groups of switches. RGB, HSYNC, and VSYNC signals are controlled by SEL1; and both SDA_ and SCL_ signals are controlled by SEL. Table 1. RGB/HV Truth Table SEL1 1 Table. DDC Truth Table SEL 1 R1 to R G1 to G B1 to B R to R G to G B to B SDA1 to SDA SCL1 to SCL SDA to SDA SCL to SCL FUNCTION H1 to H V1 to V H to H V to V FUNCTION RGB Switches The provides three SPDT high-bandwidth switches to route standard VGA R_, G_, and B_ signals (see Table 1). The R_, G_, and B_ analog switches are identical and any of the three switches can be used to route red, green, or blue video signals. The R, G, and B outputs are ESD protected to Q15kV (HBM). Horizontal/Vertical Sync Level Shifter H1, H, V1, and V inputs are buffered to provide levelshifting and drive capability for horizontal/vertical sync signals that meet the VESA specification. The H_ and V_ level-shifters are identical, and each level-shifter can be used for either horizontal or vertical signals. The H and V outputs are ESD protected to Q15kV (HBM). Display-Data Channel Multiplexer The provides two logic-level translating switches to route DDC signals (see Table ). VL is normally set to +.V to provide logic-shifting for VESA IC-compatible signals. The protects the low-voltage graphics controller from +5V that could be present in VESA-compatible monitors. In some applications, such as KVM, where logic-level shifting is not required, then VL can be connected to VCC. The SDA_ and SCL_ switches are identical, and each switch can be used to route either SDA_ or SCL_ signals. The SDA and SCL outputs are ESD protected to Q15kV (HBM). ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. Additionally, the R, G, B, H, V, SDA, and SCL terminals of the are designed for protection to the following limit: ±15kV using the HBM. For optimum ESD performance, bypass VCC and VL pins to ground with 1FF or larger ceramic capacitors as close as possible to these supply pins. 9

10 High-Bandwidth, VGA :1 Switch HIGH- VOLTAGE DC SOURCE R C 1MΩ CHARGE-CURRENT- LIMIT RESISTOR C S 1pF R D 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST AMPERES I P 1% 9% 6.8% 1% t RL I r TIME t DL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Figure 4. Human Body ESD Test Model Figure 5. Human Body Model Current Waveform Human Body Model Figure 4 shows the HBM, and Figure 5 shows the current waveform it generates when discharged into a lowimpedance state. This model consists of a 1pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5kI resistor. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report, test setup, methodology, and results. Applications Information The provides the switching and levelshifting necessary to drive a standard VGA port from either an internal graphics controller or an add-in module (MXM or GPU see Typical Applications Circuit). The R_, G_, and B_ signals are switched through the three low-capacitance SPDT switches. Internal buffers drive the HSYNC and VSYNC signals to VGA standard 5V-TTL levels. The DDC multiplexer provides level-shifting. Connect VL to +.V for normal operation, or to VCC to disable level-shifting for DDC signals as for KVM application. Power-Supply Decoupling Bypass each VCC pin and VL pin to ground with a 1FF or larger ceramic capacitor as close as possible to the device. PCB Layout High-speed switches such as the requires proper PCB layout for optimum performance. Ensure that impedance-controlled PCB traces for high-speed signals are matched in length and as short as possible. Connect the exposed pad to ground or leave unconnected. PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 TQFN-EP T Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 1 Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

11 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: ETI+ ETI+T