Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide

Transcription

1 Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML

2 Contents Contents...3 Device Family Support... 3 Features... 4 Overview... 4 Top Level Interfaces... 6 Clocks... 8 Output Path...10 Input Path...12 I/O Standards...15 Input Buffer Reference Voltage (VREF) On-Chip Termination (OCT) Placement Restrictions Guidelines: Group Pin Placement Reference Clock Reset...24 Constraining Multiple Intel FPGA PHYLite for Parallel Interfaces to One I/O Bank Dynamic Reconfiguration...24 Timing Timing Components...25 Timing Constraints and Files Timing Analysis...27 Timing Closure Guidelines Dynamic Reconfiguration...28 RTL Connectivity Addressing Example Design Avalon Controller Calibration Guidelines Intel FPGA PHYLite for Parallel Interfaces IP Core Reference Parameter Settings...41 Signals Design Example Generate the Design Example Application Specific Design Example...64 Implementation using the Intel FPGA PHYLite for Parallel Interfaces IP Core Document Archives Document Revision History for Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide

3 Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide The Intel FPGA PHYLite for Parallel Interfaces IP core is primarily used for building custom memory interface PHY blocks in Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX FPGAs. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (Synchronous Mode), and Mobile DDR. The IP core has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance. In addition, the Intel FPGA PHYLite for Parallel Interfaces IP core supports Dynamic Reconfiguration feature which enables reconfiguration of the data and strobe delays. You can align the data and strobe via calibration to achieve timing closure at high frequencies. The Intel FPGA PHYLite for Parallel Interfaces IP core controls the strobe-based capture I/O elements. Each instance of the IP core can support an interface up to 18 individual data/strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic. Related Links Document Archives on page 67 Provides a list of user guides for previous versions of the Altera PHYLite for Parallel Interfaces IP core. Device Family Support The Intel FPGA PHYLite for Parallel Interfaces IP core supports Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices only. For Arria V, Cyclone V, and Stratix V devices, use the ALTDQ_DQS2 IP core instead. Related Links ALTDQ_DQS2 IP Core User Guide For more information about the ALTDQ_DQS2 IP core Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

4 Features The Intel FPGA PHYLite for Parallel Interfaces IP core: Supports input, output, and bidirectional data channels Supports DQS-group based data capture, with up to 48 I/Os (including strobes) per group and DQS gating/ungating circuitry for strobe-based interfaces Supports output delays via interpolator Supports dynamic on-chip termination (OCT) control Supports quarter-rate to half-rate and half-rate to full-rate conversions. Supports input, output, and read/dqs/oct enable paths Supports single data rate (SDR) and double data rate (DDR) at the I/Os Supports PHY clock tree Supports dynamically reconfigurable delay chains using Avalon-MM interface Supports process, voltage, and temperature (PVT) or non-pvt compensated input and DQS delay chains Note: The non-pvt compensated component of the input delay is set through the.qsf assignment in the Intel Quartus Prime software. Overview The Intel FPGA PHYLite for Parallel Interfaces IP core utilizes the I/O subsystem in the Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel Stratix 10 devices, each column consists of I/O banks and IOSSM. For Intel Arria 10 and Intel Cyclone 10 GX devices, each column consists of I/O banks and I/O aux. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank. Important: Intel Stratix 10 devices has separate LVDS I/O bank and 3 V I/O banks. The Intel FPGA PHYLite for Parallel Interfaces IP core utilizes only the LVDS I/O banks. 4

5 Figure 1. Intel Stratix 10 I/O Bank Structure 6C 2N 2M 2L 2K 2J 2I 2H 3N 3M 3L 3K 3J 3I 3H 5N 5M 5L 5K 5J 5I 5H I/O VR I/O Lane I/O DLL I/O Lane I/O DLL I/O Center OCT 6B 6A 2G 2F 2E 2D 2C 2B 2A SDM 3G 3F 3E 3D 3C 3B 3A Secure Device Manager (SDM) 3 V I/O LVDS I/O Shared LVDS I/O 5G 5F 5E 5D 5C 5B 5A Hard Memory Controller and PHY Sequencer Clock Network I/O Lane I/O DLL I/O Lane I/O DLL I/O PLL Figure 2. Intel Arria 10 I/O Bank Structure 2L 2K 2J Individual I/O Banks 3H 3G 3F I/O Center I/O Lane I/O Lane I/O DLL I/O CLK Transceiver Block 2I 2H 3E 3D Transceiver Block I/O PLL OCT VR Hard Memory Controller and PHY Sequencer Bank Control 2G 2F 3C 3B I/O Lane Transceiver Block 2A I/O Column 3A I/O Column I/O Lane 5

6 Figure 3. Intel Cyclone 10 GX I/O Bank Structure I/O Lane I/O Lane 2L I/O Center I/O DLL OCT I/O CLK VR Transceiver Block 2K 2J 2A 3B 3A 3 V I/O LVDS I/O I/O PLL Hard Memory Controller and PHY Sequencer I/O Lane I/O Lane Intel Arria 10 and Intel Cyclone 10 GX devices do not have separate LVDS I/O and 3 V I/O banks. Related Links Top Level Interfaces Placement Restrictions on page 23 For more information about placement restrictions Intel Arria 10 External Memory Interfaces IP User Guide For more information about the architecture Intel Stratix 10 External Memory Interfaces IP User Guide For more information about the architecture Intel Cyclone 10 External Memory Interfaces IP User Guide For more information about the architecture Constraining Multiple Intel FPGA PHYLite for Parallel Interfaces to One I/O Bank on page 24 The Intel FPGA PHYLite for Parallel Interfaces IP core consists of the following ports: Clocks and reset Core data and control (broken down into input and output paths) I/O (broken down into input and output paths) Avalon-MM configuration bus 6

7 Figure 4. Top-Level Interface This figure shows the top-level diagram of the Intel FPGA PHYLite for Parallel Interfaces IP core interface. Intel FPGA Device ref_clk (From external oscillator) PLL Intel FPGA PHYLite for Parallel Interfaces IP Core phy_clk_phs phy_clk Group I/O Lane I/O Lane core_clk_out Tile Control Intel FPGA Core Logic Data to/from Core I/O Lane VCO/Interpolator I/O Lane data_in/out/io strobe_in/out/io } (From /to external devices) Legend Reference Clock Core Clock PHY Clock Interface Clock Related Links Output Path on page 10 For more information about the output path Input Path on page 12 For more information about the input path Signals on page 48 For more information about core data, control, and I/O interfaces signals 7

8 Clocks The Intel FPGA PHYLite for Parallel Interfaces IP core uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP core. This PLL provides four clock domains for the output and input paths. Table 1. Intel FPGA PHYLite IP Core Clock Domains Clock Domain Core clock PHY clock VCO clock Description This clock is generated internally by the IP core and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers. This clock is used internally by the IP core for PHY circuitry running at the same frequency as the core clock. This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator. Interface clock This is the clock frequency of the external device connected to the FPGA I/Os. Table 2. Intel Stratix 10 PHYLite for Parallel Interfaces IP Core Supported Interface Frequency Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Core Clock Rate Speed Grade 1 (MHz) Speed Grade 2 (MHz) Speed Grade 3 (MHz) Min Max Min Max Min Max Full Half Quarter Table 3. Intel Arria 10 PHYLite for Parallel Interfaces IP Core Supported Interface Frequency Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Core Clock Rate Speed Grade 1 (MHz) Speed Grade 2 (MHz) Speed Grade 3 (MHz) Min Max Min Max Min Max Full Half Quarter Table 4. Intel Cyclone 10 GX PHYLite for Parallel Interfaces IP Core Supported Interface Frequency Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Core Clock Rate Speed Grade 5 (MHz) Speed Grade 6 (MHz) Min Max Min Max Full Half Quarter

9 Clock Frequency Relationships The following equations describe the relationships between the clock domains available in the Intel FPGA PHYLite for Parallel Interface IP core. Core Clock Rate = Interface clock frequency / Core clock frequency VCO frequency Multiplier Factor = VCO clock frequency (1) / Interface clock frequency (1) You can obtain this value from the VCO clock frequency parameter under General Tab in the IP parameter editor. 9

10 Output Path The output path consists of a FIFO and an interpolator. Figure 5. Output Path This figure shows the output path for the Intel FPGA PHYLite for Parallel Interfaces IP core. output_strobe_in output_strobe_en strobe_out strobe_io data_from_core oe_from_core phy_clk Write FIFO data_io data_out oct_out oe_out interpolator_clk VCO clock Interpolator Table 5. Blocks in Output Path This table lists the blocks in the output path. Write FIFO Block Interpolator Description Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarterrate). Works with the FIFO block to generate the desired output delay. You can dynamically configure the delay through the Avalon-MM interface. For more information, refer to Dynamic Reconfiguration section. The following figures show the waveform diagrams for the output path. 10

11 Figure 6. Output Path Write Latency 0 Figure 7. Output Path Write Latency 3 Related Links Output Path Signals on page 49 For more information about output path signals Dynamic Reconfiguration on page 28 Output Path Data Alignment The data_from_core and oe_from_core signals are arranged in time slices, which are broken down into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP core. Example of time slices with individual pins correlation: {time(n),time(n-1),time(n-2),... time(0)} Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0} 11

12 Figure 8. Example Output for Quarter Rate DDR Related Links Dynamic Reconfiguration on page 28 External Memory Interface Handbook Volume 3: Reference Material (AFI 3.0 Specification) Input Path The input path of the IP core consists of a data path, a strobe path, and a read enable path. Table 6. Path Data Path Strobe Path Read Enable Path Blocks in Data, Strobe, and Read Enable Paths This table lists the information about these paths. Description Consists of a PVT compensated delay chain, a DDIO and a read FIFO. PVT compensated delay chain Allows per-bit deskew. You can only control the PVT compensated delay chain over Avalon-MM interface. For more information, refer to Dynamic Reconfiguration. DDIO and read FIFO Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zero-cycle transfer. The IP core supports SDR input by dropping every other bit of data going to the core. Consists of pstamble_reg (a gating component) and a PVT compensated delay chain. pstamble_reg This gating circuitry ensures that only clock edges associated with valid input data are used. PVT compensated delay chain Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs). Consists of VFIFO, DQS_EN FIFO, and an interpolator. VFIFO takes the rdata_en signal from the core and delays it separately for two outputs, one for the read enable on the read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. Individual control is not necessary, but if you are modifying these delays you can do so individually using dynamic reconfiguration. DQS_EN FIFO and interpolator used for the strobe enable delay, the DQS_EN FIFO and interpolator are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = 0). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be used for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read latency parameter for the group. 12

13 Figure 9. Input Path This figure shows the input path of the IP core. To Intel FPGA core Intel FPGA PHYLite for Parallel Interfaces To external interface 6 data_to_core Read FIFO DDIO Delay Chain 5 5 (PVT) data_in data_io read_enable phy_clk dqs strobe_in strobe_io strobe_in_n rdata_valid 6 pstamble_reg dqs_clean 3 dqs_enable Delay Chain (PVT) 4 phy_clk rdata_en 1 2 VFIFO dqs_enable DQS_EN FIFO interpolator_clk phy_clk_phs Interpolator n n = sequence number. This represent read operation sequence. Table 7. Read Operation Sequence A read operation is performed as listed in this table. Read Operation Sequence Number Operation 1 The core asserts the rdata_en signal (and the external device is issued a read command) 2 The strobe enable is delayed through VFIFO and DQS_EN FIFO by the programmed read latency (which should match the latency of the external device) 3 The strobe signal is gated by the strobe enable signal as valid data enters the read path 4 The strobe is optionally delayed to create a phase offset between the strobe and the input data (for example, 90 phase shift for DDR center-alignment) 5 The data is clocked into the DDIO and read FIFO by the strobe 6 The VFIFO asserts the read enable on the read FIFO and the rdata_valid signal to the core simultaneously. This outputs the captured data and the associated valid signal to the core. 13

14 Figure 10. Input Path Waveform This figure shows a waveform diagram of the input path. Related Links Input Path Signals on page 50 For more information about input path signals Input Path Data Alignment The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received. The rdata_valid delay is always set by the IP core to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle). Figure 11. Example Input (Quarter Rate DDR) - Aligned The waveform shows an example of aligned reads on the input path of the Intel FPGA PHYLite for Parallel Interfaces IP core. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus. Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs. This request causes the IP core to do two or more read operations. 14

15 Figure 12. Example Input (Quarter Rate DDR) - Unaligned The waveform shows an example of unaligned reads on the input path of the Intel FPGA PHYLite for Parallel Interfaces IP core. The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus. The valid data are transfer to the IP core through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid. I/O Standards The Intel FPGA PHYLite for Parallel Interfaces IP core allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups. When you select an I/O standard in the I/O standard parameter, the reference clock assigns the I/O standard as a single-ended input. For a differential reference clock, override the single-ended Intel Quartus Prime IP File (.qip) setting in the.qsf file with the command below. set_instance_assignment -name IO_STANDARDS LVDS -to ref_clk -entity top set_location_assignment <PIN_NUMBER> -to ref_clk set_location_assignment <PIN_NUMBER> -to "ref_clk(n)" Differential reference clock only supports LVDS input buffer. If you want to assign I/O standards manually at the system level (in the.qsf file), then set the I/O standard to none in the IP Parameter Editor, which do not output any I/O standard related.qip assignments from the IP generation. Table 8. I/O Standards and Termination Values for Intel Stratix 10 Devices I/O Standard Valid Input Terminations (Ω) Valid Output Terminations (Ω) RZQ (Ω) Differential/Complementary I/O Support Important: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. SSTL-12 60, , 60, Yes SSTL , 60, , Yes SSTL , 60, , Yes SSTL-15 40, 60, , Yes SSTL-15 Class I Yes SSTL-15 Class II Yes SSTL-18 Class I Yes continued... 15

16 I/O Standard Valid Input Terminations (Ω) Valid Output Terminations (Ω) RZQ (Ω) Differential/Complementary I/O Support Important: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. SSTL-18 Class II Yes 1.2-V HSTL Class I Yes 1.2-V HSTL Class II Yes 1.5-V HSTL Class I Yes 1.5-V HSTL Class II Yes 1.8-V HSTL Class I Yes 1.8-V HSTL Class II Yes 1.2-V POD 34, 40, 48, 60, 80, 120, , 40, 48, Yes 1.2-V No 1.5-V No 1.8-V No Table 9. I/O Standards and Termination Values for Intel Arria 10 Devices I/O Standard Valid Input Terminations (Ω) (2) Valid Output Calibrated/ Uncalibrated Terminations (Ω) (2) RZQ (Ω) (3) Differential/Complementary I/O Support SSTL-12 (4) 60, , Yes SSTL-125 (4) 60, , Yes SSTL-135 (4) 60, , Yes SSTL-15 (4) 60, , Yes SSTL-15 Class I (5) 0, 50 0, Yes SSTL-15 Class II (5) 0, 50 0, Yes SSTL-18 Class I (5) 0, 50 0, Yes SSTL-18 Class II (5) 0, 50 0, Yes 1.2-V HSTL Class I (5) 0, 50 0, Yes continued... (2) 0 is equivalent to no termination. (3) RZQ pin is not required for uncalibrated output terminations. (4) Use this I/O standard if input termination is required with interface frequency more than 533 MHz. (5) Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz. For more information, refer to KDB found in the Related Links section: The interface frequency is too high for this I/O standard. 16

17 I/O Standard Valid Input Terminations (Ω) (2) Valid Output Calibrated/ Uncalibrated Terminations (Ω) (2) RZQ (Ω) (3) Differential/Complementary I/O Support 1.2-V HSTL Class II (5) 0, 50 0, Yes 1.5-V HSTL Class I (5) 0, 50 0, Yes 1.5-V HSTL Class II (5) 0, 50 0, Yes 1.8-V HSTL Class I (5) 0, 50 0, Yes 1.8-V HSTL Class II (5) 0, 50 0, Yes 1.2-V POD 34, 40, 48, 60, 80, 120, , 40, 48, Yes 1.2-V No 1.5-V No 1.8-V No Table 10. I/O Standards and Termination Values for Intel Cyclone 10 GX Devices I/O Standard Valid Input Terminations (Ω) (2) Valid Output Calibrated/ Uncalibrated Terminations (Ω) (2) RZQ (Ω) (3) Differential/Complementary I/O Support SSTL-12 (6) 60, , Yes SSTL-125 (6) 60, , Yes SSTL-135 (6) 60, , Yes SSTL-15 (6) 60, , Yes SSTL-15 Class I (7) 0, 50 0, Yes SSTL-15 Class II (7) 0, 50 0, Yes SSTL-18 Class I (7) 0, 50 0, Yes SSTL-18 Class II (7) 0, 50 0, Yes 1.2-V HSTL Class I (7) 0, 50 0, Yes 1.2-V HSTL Class II (7) 0, 50 0, Yes 1.5-V HSTL Class I (7) 0, 50 0, Yes 1.5-V HSTL Class II (7) 0, 50 0, Yes continued... (2) 0 is equivalent to no termination. (3) RZQ pin is not required for uncalibrated output terminations. (6) Use this I/O standard if input termination is required with interface frequency more than 533 MHz. (7) Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz. For more information, refer to KDB link: The interface frequency is too high for this I/O standard. 17

18 I/O Standard Valid Input Terminations (Ω) (2) Valid Output Calibrated/ Uncalibrated Terminations (Ω) (2) RZQ (Ω) (3) Differential/Complementary I/O Support 1.8-V HSTL Class I (7) 0, 50 0, Yes 1.8-V HSTL Class II (7) 0, 50 0, Yes 1.2-V POD 34, 40, 48, 60, 80, 120, , 40, 48, Yes 1.2-V No 1.5-V No 1.8-V No Related Links On-Chip I/O Termination in Intel Arria 10 Devices On-Chip I/O Termination in Intel Cyclone 10 GX Devices On-Chip I/O Termination in Intel Stratix 10 Devices KDB link: Selected input mode termination value for data bus is not valid. Please select a value of 50 ohm or higher. Input termination limitation for Intel FPGA PHYLite for Parallel Interfaces IP Core. KDB link: The interface frequency is too high for this I/O standard I/O standards limitation for Intel FPGA PHYLite for Input Buffer Reference Voltage (VREF) The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following.qsf assignments: set_instance_assignment -name VREF_MODE <mode> -to <pin_name> Note: Table 11. The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs). VREF_MODE Description VREF Mode Description EXTERNAL CALIBRATED VCCIO_45 VCCIO_50 VCCIO_55 VCCIO_65 VCCIO_70 VCCIO_75 Use the external VREF. This is the default. Use internal VREF generated using VREF codes from the Avalon-MM reconfiguration bus. Use internal VREF generated using static VREF code. VREF is 45% of VCCN Use internal VREF generated using static VREF code. VREF is 50% of VCCN Use internal VREF generated using static VREF code. VREF is 55% of VCCN Use internal VREF generated using static VREF code. VREF is 65% of VCCN Use internal VREF generated using static VREF code. VREF is 70% of VCCN Use internal VREF generated using static VREF code. VREF is 75% of VCCN 18

19 Figure 13. VREF Input Buffer VCCN Rt Vref + - VREF Calibration Block External VREF VCCN Resistor Ladder Internal VREF R + 6 bits Static VREF Code - R 6 bits calibrated VREF code from Avalon-MM bus 6 bits binary weighted resistors dividor Calibrated VREF Settings Table 12. Calibrated VREF Settings This table lists the calibrated VREF settings that you can set over the Avalon-MM calibration bus. This table is applicable to all Intel FPGA devices. avl_writedata[5:0] % of VCCN % % % % % % % % % % % continued... 19

20 avl_writedata[5:0] % of VCCN % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % continued... 20

21 avl_writedata[5:0] % of VCCN % % % % > Reserved Related Links Dynamic Reconfiguration on page 28 On-Chip Termination (OCT) Intel FPGA PHYLite for Parallel Interfaces IP core provides valid OCT settings for each group (refer to I/O Standards on page 15). These settings are written to the.qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. You can instantiate the OCT block in one of two ways: Fitter insertion of OCT block Manual insertion of OCT block Fitter Insertion of OCT Block The RZQ_GROUP assignment creates the Intel FPGA OCT IP core without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the Intel FPGA OCT IP core and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the Intel FPGA PHYLite IP core instance with an RZQ pin at the system level manually. Example: set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_or_strobe_pin> Note: Repeat for each data and strobe pin with calibrated termination. If you know the location of the RZQ pin, then use the following.qsf assignments to set the RZQ pin to the desired location. Example: set_location_assignment <rzq_capable_pin_location> to < rzq_pin_name> Note: Repeat for each RZQ pin. The RZQ pin can be shared by groups in the same column with I/O standards that require the same RZQ value (refer to I/O Standards on page 15). 21

22 Manual Insertion of OCT Block Alternately, you can expose the termination ports of Intel FPGA PHYLite IP core instance by de-selecting the Use Default OCT Values under Group <x> OCT Settings, select the available OCT values for Input OCT Value and Output OCT Value, and select the Expose termination ports. For the input and output OCT values, refer to I/O Standards on page 15. You can then connect the termination ports to an Intel FPGA OCT IP core either in power-up or user mode. Figure 14. RTL View of Intel FPGA PHYLite for Parallel Interfaces IP Interfacing with Intel FPGA OCT IP Core in User Mode group_0_data_in[3:0] cal_request refclk rstn octrzqin0 group_0_strobe_in calibration_request clock reset rzqin oct_test_ip u1 oct_0_parallel_termination_control[15:0] oct_0_series_termination_control[15:0] group_0_data_in[3:0] phylite_test_ip group_0_parallelterminationcontrol[15:0] 4 h0group_0_rdata_en[3:0] group_0_seriesterminationcontrol[15:0] group_0_strobe_in 32 h0group_1_data_from_core[31:0] 16 h0group_1_oe_from_core[15:0] group_1_parallelterminationcontrol[15:0] group_1_seriesterminationcontrol[15:0] 4 h0group_1_strobe_out_en[3:0] 8 h0group_1_strobe_out_en[7:0] ref_clk group_1_data_out[3:0] group_1_strobe_out interface_locked reset_n u0 22

23 Placement Restrictions Guidelines: Group Pin Placement Follow these guidelines to place the Intel FPGA PHYLite for Parallel Interface IP core group pins. 1. All groups in an Intel FPGA PHYLite for Parallel Interface IP core must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group. 2. Two groups, from either the same or different Intel FPGA PHYLite for Parallel Interface IP core, cannot share an I/O lane. 3. For Intel FPGA PHYLite for Parallel Interface IP core instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width. 4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins. 5. To constrain groups from separate Intel FPGA PHYLite for Parallel Interface IP core instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings. The number of I/O banks must be at least as many as the number of PHYLite interfaces. 6. A reference clock network can only span across maximum of 6 I/O banks. 7. You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the Intel FPGA PHYLite for Parallel Interface IP core instance with an RZQ pin through RZQ_GROUP assignment. Table 13. Group Pin Placement Intel FPGA PHYLite for Parallel Interface IP core does not support DQS for X4. Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank 1-12 DQS for X8/X9 {0-11}/{12-23}/{24-35}/{36-47} DQS for X16/X18 {0-23}/{24-47} DQS for X32/X36 {0-47} Related Links Reference Clock Pin-Out Files for Intel FPGA Devices For specific DQS group numbers refer to the specific device pin-out file You are recommended to source the reference clock to the Intel FPGA PHYLite for Parallel Interface IP core from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the Intel FPGA PHYLite for Parallel Interface IP core. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of EMIF and Intel FPGA PHYLite for Parallel Interface IP cores). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks. 23

24 Important: In previous versions of the Intel Arria 10 PHYLite for Parallel Interfaces IP core, the IOPLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Intel Quartus Prime version Related Links Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin Clock Networks and PLLs in Intel Arria 10 Devices - PLL Cascading For more information about PLL cascading in Intel Arria 10 devices. How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? Reset You can source the reset to the Intel FPGA PHYLite for Parallel Interface IP core from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the.qsf file with the following command: set_location_asignment <PIN_NUMBER> -to <signal_name> Constraining Multiple Intel FPGA PHYLite for Parallel Interfaces to One I/O Bank To constrain groups from separate Intel FPGA PHYLite for Parallel Interface IP core instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings. Related Links Overview on page 4 Dynamic Reconfiguration Timing If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and Intel FPGA PHYLite for Parallel Interface IP cores in the same I/O column must share the reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity. Related Links Daisy Chain on page 29 Describes the daisy chain connectivity The Intel Quartus Prime software generates the required timing constraints to analyze the timing of the Intel FPGA PHYLite for Parallel Interface IP core on the all Intel FPGA devices. 24

25 Timing Components Table 14. Timing Components Circuit Category Timing Paths Source Destination Description Source synchronous and optionally calibrated (8) Source synchronous and optionally calibrated (8) Read Path Write Path Memory Device FPGA DQ/DQS DQ Capture Register Memory Device Source synchronous timing paths paths where clock and data signals are passed from the transmitting devices to the receiving devices. Optionally calibrated paths paths with delay elements that are dynamically reconfigurable to achieve timing closure, especially at higher frequency, and to maximize the timing margins. You can calibrate these paths by implementing an algorithm and turning on the optional dynamic reconfiguration feature. An example of the calibrated path is the FPGA to memory device write path, in which you can dynamically reconfigure the delay elements to, for instance, compensate the skew due to process voltage temperature variation. Internal FPGA Internal FPGA Core to PHYLite Path PHYLite to Core Core Registers Read FIFO Write FIFO Core Registers The internal FPGA paths are paths in the FPGA fabric. The Timing Analyzer reports the corresponding timing margins. Timing Constraints and Files To successfully constrain the timing for Intel FPGA PHYLite for Parallel Interface IP core, the IP core generates a set of timing files. You can locate these timing files in the <variation_name> directory: <variation_name>.sdc <variation_name>.sdc <variation_name> _ip_parameters.tcl <variation_name> _pin_map.tcl <variation_name>_parameters.tcl <variation_name>_report_timing.tcl <variation_name>_report_timing_core.tcl You can find the location of the <variation_name>.sdc file in the.qip or.qsys, which is generated during the IP generation. The <variation_name>.sdc allows the Fitter to optimize timing margins with timing driven compilation and allows the Timing Analyzer to analyze the timing of your design. (8) Can be optionally calibrated by using dynamic reconfiguration. 25

26 The IP core uses <variation_name>.sdc for the following operations: Creating clocks on PLL inputs Creating generated clocks Calling derive_clock_uncertainty Creating set_output_delay and set_input_delay constraints to analyze the timing of the read and write paths <variation_name>_parameter.tcl The <variation_name>_parameters.tcl file is a script that lists the following Intel FPGA PHYLite for Parallel Interface IP core parameters used in the.sdc file and report timing scripts: Jitter Simultaneous switching noise Calibration uncertainties <variation_name>_ip_parameters.tcl The <variation_name>_ip_parameters.tcl file lists the Intel FPGA PHYLite for Parallel Interfaces IP core parameters and is read by the <variation_name>.sdc. <variation_name>_pin_map.tcl The <variation_name>_pin_map.tcl is a TCL library of functions and procedures that <variation_name>.sdc uses. <variation_name>_report_timing.tcl The <variation_name>_report_timing.tcl file is a script that contains timing analysis flow and reports the timing slack for your variation. This script runs automatically during calibration (during static timing analysis) by sourcing the following files: <variation_name>_ip_parameters.tcl <variation_name>_parameters.tcl <variation_name>_pin_map.tcl <variation_name>_report_timing_core.tcl You can also run <variation_name>_report_timing.tcl with the Report DDR function in the Timing Analyzer. This script runs for every instance of the same variation. Note: You can only use the Report DDR function if you enable the dynamic reconfiguration feature. 26

27 <variation_name>_report_timing_core.tcl The <variation_name>_report_timing_core.tcl file is a script that <variation_name>_report_timing.tcl uses to calculate the timing slack for your variation. <variation_name>_report_timing_core.tcl runs automatically during compilation. Timing Analysis Table 15. Timing Analysis This table lists the timing analysis performed in the I/O and FPGA for the Intel FPGA PHYLite for Parallel Interfaces IP core. Location I/O FPGA Description The Intel FPGA PHYLite for Parallel Interfaces IP core generation creates the appropriate generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format: Clock name for read strobe <pin_name>_in. Clock name for the write path <pin_name> for positive strobe. Clock name for the write path <pin_name>_neg for negative strobe. The set_false_path, set_input_delay and set_output_delay constraints are also generated to ensure proper timing analysis of the Intel FPGA PHYLite for Parallel Interfaces IP core. The Intel FPGA PHYLite for Parallel Interfaces IP core generation creates the clock settings for the user core clock and the periphery clock in the following formats: user core clock <variation_name>_usr_clk periphery clock <variation_name>_phy_clk* The user core clock is for user core logic and the periphery clock is the clock for the Intel FPGA PHYLite for Parallel Interfaces IP core periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of the Intel FPGA PHYLite for Parallel Interfaces IP core interface transfer and within core transfer correctly. Timing Closure Guidelines Timing Closure: Dynamic Reconfiguration You can dynamically reconfigure the delay elements in the I/O to optimize process, voltage, temperature variations by implementing a calibration algorithm that modifies the input and output delays. Related Links Dynamic Reconfiguration on page 28 Timing Closure: Non Edge-Aligned Input Data If the input data is not edge-aligned, use the following equation to calculate the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values: New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input Strobe Phase Shift (nanosecond) New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input Strobe Phase Shift (nanosecond) 27

28 For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1 with input data phase shift of 90 : New Input Strobe Setup Delay Constraint value = *(90/360) = ns. New Input Strobe Hold Delay Constraint value = *(90/360) = ns Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters. I/O Timing Violation It can be difficult to achieve timing closure for I/O paths at high frequency. Use the dynamic reconfiguration feature to calibrate the I/O path. Related Links Dynamic Reconfiguration on page 28 For more information about using the dynamic reconfiguration feature to calibrate the I/O path Internal FPGA Path Timing Violation If timing violations are reported at the internal FPGA paths (such as <instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the following guidelines: If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer. If hold time violation is observed, you may increase hold uncertainty value to equal or higher than the violation amount in the.sdc file. This will provide a more stringent constraint during design fitting. Following is an example to increase the hold uncertainty. If {$::quartus(nameofexecutable)!= quartus_sta }{ set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add } However, increasing the hold uncertainty value may cause setup timing violation at slow corner. Dynamic Reconfiguration Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. You can modify these delays using an Avalon-MM interface by enabling dynamic reconfiguration in the Intel FPGA PHYLite for Parallel Interfaces IP core. 28

29 Important: When the dynamic reconfiguration feature is enabled in Intel Stratix 10 devices, the maximum Avalon-MM interface speed is 167 MHz. Related Links RTL Connectivity Daisy Chain Calibrated VREF Settings on page 19 Timing Closure: Dynamic Reconfiguration on page 27 The Intel FPGA PHYLite for Parallel Interfaces IP core exposes the Avalon-MM master and Avalon-MM slave interfaces when you enable the dynamic reconfiguration feature. If the generated IP core is the only Intel FPGA PHYLite for Parallel Interfaces IP core (with dynamic reconfiguration) or External Memory Interfaces IP core in the I/O column, connect only the Avalon-MM slave interface with a master in the core. Otherwise, connect Avalon-MM master and slave interfaces as described in the following section. The I/O column provides a single physical Avalon-MM interface. All IP cores in the I/O column that require Avalon-MM interface access the same physical Avalon-MM interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IP cores in an I/O column. The Intel Stratix 10 PHYLite for Parallel Interfaces IP core exposes a 32-bit Avalon-MM address, where the MSB is always 0, followed by a 4-bit interface ID. For Intel Arria 10 PHYLite for Parallel Interfaces and Intel Cyclone 10 GX IP cores, the Avalon-MM address is 28 bits where the top 4-bits are the ID of the interface to be addressed in the daisy chain. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP core, it is sufficient to connect these bits as the interface s ID. Figure 15. Logical RTL View to Physical Column Placement This figure shows an example of a daisy chain consisting of the External Memory Interfaces and Intel FPGA PHYLite for Parallel Interfaces IP cores before and after placement. Notice that all core controllers must go through the arbitration logic that you created in the FPGA core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0. 29

30 Note: The Fitter rearranges the Avalon address pins during compilation, therefore simulation of the design using prefit netlist will be incorrectly. Use the postfit netlist for proper simulation of the merged I/O column. Addressing Each reconfigurable feature of the interface has an associated memory address; however, this address is placement dependent. If Intel FPGA PHYLite for Parallel Interfaces IP cores and the External Memory Interfaces IP cores share the same I/O column, you must track the addresses of the interface lanes and the pins. Addressing is done at the 32-bit word boundary, where avl_address[1:0] are always 00. Table 16. Address Map In this table: id[3:0] refers to the Interface ID parameter. lane_addr[7:0] refers to the address of a given lane in an interface. The Fitter sets this address value. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup on page 33. pin[4:0] refers to the physical location of the pin in a lane. You can use the Fitter to automatically determine a pin location or you can manually set the pin location through.qsf assignment. Refer to the Parameter Table Lookup Operation Sequence as described in the Address Lookup on page 33 for more information. Feature Avalon Address R/W Address CSR R Control Value Field Range Pin Output Phase {id[3:0], 3'h4,lane_addr[7: 0],pin{4:0],8'D0} {id[3:0], 3'h4,lane_addr[7 :0],pin{4:0], 8'E8} Phase Value Minimum Setting: Refer to Table 17 on page 33 Maximum Setting: Refer to Table 17 on page 33 Incremental Delay: 1/128th VCO clock period Note: The pin output phase switches from the CSR value to the Avalon value after the first Avalon write. It is only reset to the CSR value on a reset of the interface. Reserved (9) Pin PVT Compensated Input Delay {id[3:0], 3'h4,lane_addr[7: 0], 4'hC,lgc_sel[1:0],pin_off[2:0], 4'h0} Not supported Delay Value Reserved ( 9) 8..0 Minimum Setting: Maximum Setting: 511 VCO clock periods Incremental Delay: 1/256th VCO clock period continued... (9) Reserved bit ranges must be zero 30

31 Feature Avalon Address R/W Address CSR R Control Value Field Range lgc_sel[1:0] is: 2'b01 for DQ [5:0] 2'b10 for DQ [11:6] pin_off[2:0] : 3'h0: DQ [0], DQ [6] 3 h1: DQ [1], DQ [7] 3 h2: DQ [2], DQ [8] 3 h3: DQ [3], DQ [9] 3 h4: DQ [4], DQ [10] 3 h5: DQ [5], DQ [11] Enable 12 0 = Delay value is 0. Reserved ( 9) = Select delay value from Avalon register Strobe PVT compensated input delay (10) {id[3:0], 3'h4,lane_addr[7: 0], 4'hC,lgc_sel[1:0],3'h6,4'h0} lgc_sel[1:0] = 2'b01 Not supported Delay Value Reserved ( 9) 9..0 Minimum Setting: Maximum Setting: 1023 VCO clock periods Incremental Delay: 1/256th VCO clock period Enable 12 0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP core instantiation. 1 = Select delay value from Avalon register Reserved ( 9) Strobe enable phase (10) {id[3:0], 3'h4,lane_addr[7: 0], 4'hC,lgc_sel[1:0],3'h7,4'h0} lgc_sel[1:0] = 2'b01 {id[3:0], 3'h4,lane_addr[7 :0],4'hC,9'h198} Phase Value Reserved ( 9) Minimum Setting: Refer to Table 17 on page Maximum Setting: Refer to Table 17 on page 33 Incremental Delay: 1/128th VCO clock period Enable 15 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Reserved ( 9) continued... (10) Modifying these values must be done on all lanes in a group. 31

32 Feature Avalon Address R/W Address CSR R Control Value Field Range Strobe enable delay (10) {id[3:0], 3'h4,lane_addr[7: 0],4'hC,9'h008} {id[3:0], 3'h4,lane_addr[7 :0],4'hC,9'h1A8} Delay Value 5..0 Minimum Setting: 0 external clock cycles Maximum Setting: 63 external memory clock cycles Incremental Delay: 1 external memory clock cycle Reserved ( 9) Enable 15 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Reserved ( 9) Read valid delay (10) {id[3:0], 3'h4,lane_addr[7: 0],4'hC,9'h00C} {id[3:0], 3'h4,lane_addr[7 :0],4'hC,9'h1A4} Delay Value 6..0 Minimum Setting: 0 external clock cycles Maximum Setting: 127 external memory clock cycles Incremental Delay: 1 external memory clock cycle Reserved ( 9) Enable 15 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Reserved ( 9) Internal VREF Code {id[3:0], 3'h4,lane_addr[7: 0],4'hC,9'h014} Not supported VREF Code Reserved ( 9) 5..0 Refer to Table 12 on page (9) Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx. 32

33 Output and Strobe Enable Minimum and Maximum Phase Settings When dynamically reconfiguring the interpolator phase settings, the values must be kept within the ranges below to ensure proper operation of the circuitry. Table 17. Output and Strobe Enable Minimum and Maximum Phase Settings for Intel Stratix 10, Intel Arria 10 and Intel Cyclone 10 GX Devices. VCO Multiplication Factor Core Rate Minimum Interpolator Phase Maximum Interpolator Phase Output Bidirectional Bidirectional with OCT Enabled 1 Full 0x080 0x100 0x100 0xA80 Half 0x080 0x100 0x100 0xBC0 Quarter 0x080 0x100 0x100 0xA00 2 Full 0x080 0x100 0x180 0x1400 Half 0x080 0x100 0x180 0x1400 Quarter 0x080 0x100 0x180 0x Full 0x080 0x100 0x280 0x1FFF Half 0x080 0x100 0x280 0x1FFF Quarter 0x080 0x100 0x280 0x1FFF 8 Full 0x080 0x100 0x480 0x1FFF Half 0x080 0x100 0x480 0x1FFF Quarter 0x080 0x100 0x480 0x1FFF Address Lookup For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx. The lane addresses and pin placement to an interface changes every time you compile your design in Intel Quartus Prime software. Therefore, you must know the lane addresses and the pin placement to address an interface correctly. The Intel FPGA PHYLite for Parallel Interfaces IP core is generated as if the IP core is the only IP core in a column, with lane addresses starting from 0. You must modify the addressing of the I/O lanes if the Intel FPGA PHYLite for Parallel Interface IP core (with dynamic reconfiguration) and the External Memory Interfaces IP core are placed in the same column to avoid conflicts. 33

34 Figure 16. Lane and Pin Placement Dependent Addresses This figure shows an example of a placed group with two lanes, 16 data pins and a differential strobe. To provide a unified way to look up reconfigurable feature addresses for a specific interface both before and after placement, the address information is stored in memory in the I/O column. This memory is addressable over the same Avalon-MM bus used for feature reconfiguration. Table 18. Memory Lookup Components This table lists the two main components of the memory lookup. Component Global parameter table Set of individual interface parameter tables Description Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and Intel FPGA PHYLite for Parallel Interfaces IP cores). Contain interface specific information. This is where pin-level and lane-level address lookups are performed. 34

35 Figure 17. Memory Overview in Intel Stratix 10 Devices 32-bits (4 Byte Addresses) {1 b0,id[3:0],27 h } Global Parameter Table (One per column, same as EMIF) {1 b0,id[3:0],27 h h24} {4 b1000,id[3:0], Address Offset pt_ptr[23:0] 1 A {4'h8,id[3:0],8'h00,interface_table_ptr[15:0]} {1 b0,id[3:0],27 h } + pt_ptr {1 b0,id[3:0],27 h } + pt_ptr 28 d4 {1 b0,id[3:0],27 h } + pt_ptr 28 d8 Number of Groups Parameter Table (PHYLite Specific) {1 b0,id[3:0],27 h } + pt_ptr + Number of Groups {18 h0,group_offset[5:2],2 b00} + {21 d0,num_grps,2 b00} + 28h C PT_VER[15:0],IP_VER[15:0] Number of Groups lane_ptr[15:0],pin_ptr[15:0] B group_offset = grp_num -1 num_lanes[1:0],num_pins[5:0] lane_offset[31:16],pin_offset[15:0] One per Interface {1 b0,id[3:0],27 h } + lane_ptr + lane_num Lane Address Table (PHYLite Specific) C Group 0 Lane 0 5 Needed for simplifying strobe feature logic address lookups {1 b0,id[3:0],27 h } + pin_ptr + {17 h0,pin_num[5:0],1 b0} Pin Address Table (PHYLite Specific) Group 0 Pin 1 Group 0 Pin 0 D 6 Needed for pin address lookups A B C D The MSB of the interface pointer entry in the global parameter table is 1 for PHYLite interfaces. num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes Lane address table information: Group X Lane Y = lane_addr[7:0] Pin address table information: Group X Pin Y = {lane_addr[7:0],0xf,pin[3:0]} for data and {lane_addr[7:0],0xe,pin[3:0]} for strobe The Parameter table look-ups are used as follows (the sequence corresponds to the sequence in Memory Overview in Intel Stratix 10 Devices): Table 19. Parameter Table Lookup Operation Sequence Legend in Memory Overview in Intel Stratix 10 Devices Description 1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface) {1'b0,id{3:0],27'h } + 28'h24 to {1'b0,id{3:0],27'h } + 28'h3C 1 to 11 look-ups 2 Retrieve number of groups in the interface (cache once per interface) {1'b0,id[3:0],27'h } + {12'h0,pt_ptr[15:0]} + 28'h4 You can skip this sequence if the number of groups is saved in the core during compilation (for example, hard coded in RTL logic) 3 Retrieve group information (cache once per group) {1'b0,id[3:0],27'h } + {12'h0,pt_ptr[15:0]} + 28'h8 + grp_num Not always necessary 4 Retrieve Lane/Pin Address Offsets for group (cache once per group) {1'b0,id[3:0],27'h } + {12'h0,pt_ptr[15:0]} + {18'h0,group_offset[5:2],2'b00} + {21'd0, grp_num, 2'b00} + 28'hC 5 Perform lane/pin address translation (cache once per pin) continued... 35

36 Legend in Memory Overview in Intel Stratix 10 Devices Description {1'b0,id[3:0],27'h } + {12'h000,lane_ptr[15:0]} + lane_num {1'b0,id[3:0],27'h } + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0} 6 Read/Write Avalon Calibration Bus {1'b0,id[3:0],27'h } + read_from_step_4 + intra_lane_addr Figure 18. Memory Overview in Intel Arria 10 and Intel Cyclone 10 GX Devices {id[3:0],24 h00e000} Global Parameter Table (One per column, same as EMIF) {id[3:0],24'00e018} A 32-bits (4 Byte Addresses) {4 b1000,id[3:0], pt_ptr[23:0] {4'h8,id[3:0],8'h00,interface_table_ptr[15:0]} 1 Parameter Table (PHYLite Specific) {id[3:0],24 h00e000} + pt_ptr + {22 d0,num_grps[7:2],2 b00} + 28 d8 {id[3:0],24 h00e000} + pt_ptr {id[3:0],24 h00e000} + pt_ptr 28 d4 Number of Groups Number of Groups PT_VER[15:0],IP_VER[15:0] Number of Groups lane_ptr[15:0],pin_ptr[15:0] B num_lanes[1:0],num_pins[5:0] One per Interface {id[3:0],24 h00e000} + lane_ptr Lane Address Table (PHYLite Specific) C Group 0 Lane 0 5 Needed for simplifying strobe feature logic address lookups {id[3:0],24 h00e000} + pin_ptr Pin Address Table (PHYLite Specific) Group 0 Pin 1 Group 0 Pin 0 D 6 Needed for pin address lookups A B C D The MSB of the interface pointer entry in the global parameter table is 1 for PHYLite interfaces. num_lanes[1:0] starts counting at 0. For example, 0 = 1 lane, 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes Lane address table information: Group X Lane Y = lane_addr[7:0] Pin address table information: Group X Pin Y = {lane_addr[7:0],0xf,pin[3:0]} for data and {lane_addr[7:0],0xe,pin[3:0]} for strobe The Parameter table look-ups are used as follows (the sequence corresponds to the sequence in Figure 18 on page 36): Table 20. Parameter Table Lookup Operation Sequence Legend in Figure 18 on page 36 Description 1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface) {id{3:0],24'h00e000} + 28'h18 to {id{3:0],24'h00e0000} + 28'h2C 1 to 11 look-ups 2 Retrieve number of groups in the interface (cache once per interface) continued... 36

37 Legend in Figure 18 on page 36 Description {id[3:0],24'h00e000} + {4'h0,pt_ptr[23:0]} + 4'h4 You can skip this sequence if the number of groups is saved in the core during compilation (for example, hard coded in RTL logic) 3 Retrieve group information (cache once per group) {id[3:0],24'h00e000} + {4'h0,pt_ptr[23:0]} + 24'h4 + grp_num Not always necessary 4 Retrieve Lane/Pin Address Offsets for group (cache once per group) {id[3:0],24'h00e000} + pt_ptr + {22'd0,num_grps[7:2],2'b00} + 28'd8 5 Perform lane/pin address translation (cache once per pin) {id[3:0],24'h00e000} + {12'h000,lane_ptr[15:0]} + lane_num {id[3:0],24'h00e000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0} 6 Read/Write Avalon Calibration Bus {id[3:0],24'h800000} + read_from_step_4 + intra_lane_addr Caching lookups 1 to 4 (8-bytes of information) allows for pin and lane translations in one look-up. Strobes The first pins listed in the pin address lookup table are the strobes. They are also identified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placement always take precedence. For differential and complementary strobes, the positive pin is the lower index. Note: You can modify the output phase of differential strobes by writing to either the positive or negative pin. Only one write is necessary. This is also the case for output-only complementary strobes. Parameter Table Example These figures show examples of designs containing two Intel FPGA PHYLite interfaces from different Intel FPGA devices, each with one bidirectional group composed of 4 data bits and one strobe. Both interfaces are in the same I/O column and therefore their tables must be merged. 37

38 Figure 19. Parameter Table Example for Intel Stratix 10 Devices Figure 20. Parameter Table Example for Intel Arria 10 and Intel Cyclone 10 GX Devices 1 group with 5 pins and 1 lane in the interface Lane Pointer Pin Pointer strobe_io = lane 0x00, pin 0 data_io[0] = lane 0x00,pin 1 data_io[1] = lane 0x00, pin 2 data_io[2] = lane 0x00, pin 3 data_io[3] = lane 0x00, pin 4 strobe_io = lane 0x39, pin 4 data_io[0] = lane 0x39,pin 3 data_io[1] = lane 0x39, pin 11 data_io[2] = lane 0x39, pin 7 data_io[3] = lane 0x39, pin 10 strobe_io = lane 0x00, pin 0 data_io[0] = lane 0x00, pin 1 data_io[1] = lane 0x00, pin 2 data_io[2] = lane 0x00, pin 3 data_io[3] = lane 0x00, pin 4 3AF13AE4 3AFA3AF9 strobe_io = lane 0x3A, pin 4 data_io[0] = lane 0x3A, pin 1 data_io[1] = lane 0x3A, pin 9 data_io[2] = lane 0x3A, pin 10 data_io[3] = lane 0x3A, pin 8 Important: There is no guarantee of the ordering of the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter. For more information about the contents of the parameter table, refer to Figure 18 on page

39 Example Design Avalon Controller An addressing operation can be complicated and error prone. Accidentally addressing the wrong interface of the IP cores may result in difficulties when debugging runtime errors. Therefore, the example design provides an Avalon controller to simplify the dynamic control of an interface. Intel recommends to integrate the provided example controller into a dynamic reconfiguration design. Figure 21. Avalon Controller Avalon Interface Input (from user logic) Avalon Controller Avalon Interface Output (to Intel FPGA PHYLite instance daisy chain) The input interface is as follows: avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]} Note: Note: Table 21. There is no look-up stage here. The Avalon controller automatically looks up and caches all the necessary data. A single controller can support multiple interfaces in an I/O column. Avalon Controller Registers This table lists the available registers in the Avalon controller. For more information, refer to Table 16 on page 30. Register[7:0] Pin[5:0] Csr[0] Avalon Register Access Type CSR Register Access Type R/W Data on avl_readdata/ avl_writedata AVL_CTRL_REG_NUM_GROUPS 0 0: Access to Avalon register. AVL_CTRL_REG_GROUP_INFO 0 0: Access to Avalon register. AVL_CTRL_REG_IDELAY : Access to Avalon register. AVL_CTRL_REG_ODELAY : Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. R N/A {24'h000000,num_grps[7: 0]} R N/A {16'h0000,num_lanes[7:0],num_pins[7:0]} R/W N/A {23'h000000,dq_delay[8:0 ]} R/W R {19'h00000,output_phase[ 12:0]} continued... 39

40 Register[7:0] Pin[5:0] Csr[0] Avalon Register Access Type CSR Register Access Type R/W Data on avl_readdata/ avl_writedata AVL_CTRL_REG_DQS_DELAY 0: DQS A 1: DQS B (11) 0: Access to Avalon register. R/W N/A {22'h000000,dqs_delay[9: 0]} AVL_CTRL_REG_DQS_EN_DELAY 0 0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. R/W R {26'h ,dqs_en_dela y[5:0]} AVL_CTRL_REG_DQS_EN_PHASE_SHI FT 0: DQS A 1: DQS B (11) 0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. R/W R {19'h00000,phase[12:0]} AVL_CTRL_REG_RD_VALID_DELAY 0 0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. R/W R {25'h ,rd_vld_dela y[6:0]} The interface_id[3:0] and grp[4:0] components of the input address are always used. Note: The example Avalon controller does not currently support VREF reconfiguration. Related Links Dynamic Reconfiguration with Debug Kit on page 55 Functional Description on page 60 Calibration Guidelines The Intel FPGA PHYLite for Parallel Interfaces IP core allows you to dynamically reconfigure the features of the interface. However, performing calibration is an application specific process. This section provides some general guidelines for calibrating the Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX I/O architecture. (11) Strobe logic B is only used by the negative pin of complementary strobes 40

41 Strobe Enable Windowing The read pointer in the read FIFO buffer gets reset when reads are far apart (80 core clock cycles). However, the data inside the FIFO is not cleared. Therefore, an alternating pattern should be used to find the end to the strobe enable window to avoid reading stale data in the FIFO. The strobe enable signal turns itself off on the last negative edge of the strobe. Therefore, while finding the enable window, use extra dummy pulses (either extended strobe or reads from memory without asserting the rdata_en signal) to clear the strobe enable. Intel FPGA PHYLite for Parallel Interfaces IP Core Reference You can instantiate the Intel FPGA PHYLite for Parallel Interfaces IP core from IP Catalog in Intel Quartus Prime software. Intel provides an integrated parameter editor that allows you to customize the Intel FPGA PHYLite for Parallel Interfaces IP core to support a wide variety of applications. The Intel FPGA PHYLite for Parallel Interfaces IP core is located in Libraries Basic Functions I/O of the IP catalog. Related Links Parameter Settings Introduction to Intel FPGA IP Cores Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores. Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades. Project Management Best Practices Guidelines for efficient management and portability of your project and IP files. Table 22. Intel FPGA PHYLite for Parallel Interfaces IP Core Parameter Settings This table lists the parameter settings for the Intel FPGA PHYLite for Parallel Interfaces IP core for Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. GUI Name Values Default Values Description Parameter Number of groups 1 to 18 1 Number of data and strobe groups in the interface. The value is set to 1 by default. General Tab- these parameters are set on a per interface basis Clocks Interface clock frequency 100 MHz MHz MHz External memory clock frequency. Note: To achieve timing closure at 800 MHz and above, use dynamic reconfiguration to calibrate the interface. Use recommended PLL reference clock frequency On, Off On If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option. continued... 41

42 GUI Name Values Default Values Description If you want to specify your own PLL reference clock frequency, turn off this option. PLL reference clock frequency VCO clock frequency Dependent on desired memory clock frequency Calculated internally by PLL MHz PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface. Note: There is no minimum range, but the maximum output frequency is 1600 MHz, limited by the clock network. The minimum range for the ref_clk signal is 10 MHz but the maximum is dependent on the speed grade MHz The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate. Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz. Specify additional output clocks based on existing PLL On, Off Off Exposes additional output clocks from the existing PLL. Output Clocks Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter is turned on Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to be exposed. outclk[4:0] (Reserved) PLL output clocks with the flag (Reserved) in the QSYS GUI are reserved for Intel FPGA PHYLite for Parallel Interfaces IP core internal functionality. Desired Frequency MHz Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places. Actual Frequency MHz Allows you to select the actual output clock frequency from a list of achievable frequencies. Phase shift units ps or degrees ps Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees. Phase shift ps Specifies the requested value for the phase shift. The default value is 0 ps. Actual phase shift ps Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift. Desired duty cycle % Specifies the requested value for the duty cycle. Actual duty cycle 50.0 % Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle. Dynamic Reconfiguration continued... 42

43 GUI Name Values Default Values Description Use dynamic reconfiguration On, Off Off Exposes an Avalon-MM interface, allowing you to control the configuration of the Intel FPGA PHYLite for Parallel Interfaces IP core settings. Interface ID 0 The ID used to identify this interface in the I/O column over the Avalon-MM bus. I/O Settings I/O standard SSTL-12 SSTL-125 SSTL-135 SSTL-15 SSTL-15 Class I SSTL-15 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V-HSTL Class I 1.2-V-HSTL Class II 1.5-V-HSTL Class I 1.5-V-HSTL Class II 1.8-V-HSTL Class I 1.8-V-HSTL Class II 1.2-V POD SSTL-15 Class I Specifies the I/O standard of the interface's strobe and data pins written to the.qip file of the IP instance. When you choose None, the I/O standard is unspecified in the generated IP. 1.2-V 1.5-V 1.8-V None Group <x> - these parameters are set on a per group basis Group <x> Parameter Settings Copy parameters from another group On, Off Off Select this option when you want to copy the parameter settings from another group. Set Number of groups to more than 1 to enable this option. Group Choose the group index that you want as the parameter settings source. The changes made to the source is updated automatically to all the target groups. Group <x> Pin Settings Note: These parameters are disabled when Copy parameters from another group is enabled. You can only choose the group index which the parameter settings are not copied from another group. Set Number of groups to more than 1 to enable this option. Pin type Input, Output, Bidirectional Bidirectional Direction of data pins. This value is set to Bidirectional by default. continued... 43

44 GUI Name Values Default Values Description Pin width 1 to 48 9 Number of pins in this data/strobe group. A data width up to 48 is achievable if no strobe is used in the group. The number of strobes is controlled by the Use output strobe, Strobe configuration and Use separate capture strobe parameters. DDR/SDR DDR, SDR DDR Double/single data rate. Group <x> Input Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Read latency 1 to 63 external interface clock cycles 7 Expected read latency of the external device in memory clock cycles. For example, a design with an external clock frequency of 533 MHz in half-rate has a valid read latency range of 5 to 63 external interface clock cycles. Refer to Table 23 on page 47 for read latency settings based on FPGA core clock rate. Swap capture strobe polarity On, Off Off Internally swap the negative and positive capture strobe input pins. This feature is only available for complementary strobe configurations. Capture strobe phase shift 0, 45, 90, 135, Internally phase shift the input strobe relative to input data. Group <x> Output Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Write latency 0 to 3 (maximum value is dependent on the rate) 0 Additional delay added to the output data in memory clock cycles. Refer to Table 24 on page 48 for write latency settings based on FPGA core clock rate. Use output strobe On, Off On Use an output strobe. Output strobe phase 0, 45, 90, 135, Phase shift of the output strobe relative to the output data. Group <x> General Data Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Data configuration Single ended, Differential (available only for Intel Arria 10 and Intel Cyclone 10 GX devices) Single ended Selects the type of data. Single ended data type uses one pin. Differential data type uses 2 pins. Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. Refer to I/O Standards on page 15 for a list of supported I/O standards. Group <x> General Strobe Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Strobe configuration Single ended, Differential, Complementar y Single ended Select the type of strobe. A single ended strobe uses one pin, which reduces the maximum possible number of data pins in the group to 47. Differential/complementary strobe types use 2 pins, which reduces the maximum possible number of data pins in the group to 46. continued... 44

45 GUI Name Values Default Values Description Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The complementary strobe configuration uses two single-ended input buffers and clocks the data into the capture DDIO and read FIFO using both clocks (as required by protocols such as QDRII). The output path functionality is the same. Refer to I/O Standards on page 15 for a list of supported I/O standards. Use separate strobes On, Off Off Separate the bidirectional strobe into input and output strobe pins. Use separate strobes is only available for a bidirectional data group with the output strobe enabled. Group <x> OCT Settings Note: These parameters are disabled when Copy parameters from another group is enabled. OCT enable size 0-15 (Intel Stratix 10 devices) 0-4 (Intel Arria 10 and Intel Cyclone 10 GX devices) 1 Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data. Note: For Intel Quartus Prime software version prior to 17.0, refer to related information for known issue. Expose termination ports On, Off Off Turn on to expose the series and parallel termination ports to connect separate OCT block. To enable this option, turn off Use Default OCT Values parameter and select a value for Input OCT Value or Output OCT Value parameters. Use Default OCT Values Use default OCT values based on the I/O standard parameter setting. Input OCT Value No termination, <n> ohm with calibration No termination Specifies the group's data and strobe input termination values to be written to the.qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to I/O Standards on page 15. This option is available when the Use Default OCT Values option is disabled. Output OCT Value No termination, <n> ohm with calibration, <n> with no calibration No termination Specifies the group's data and strobe input termination values to be written to the.qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to I/O Standards on page 15 supported termination values. This option is available when the Use Default OCT Values option is disabled. Group <x> Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Generate Input Delay Constraints for this group On, Off On Instructs SDC to generate set_input_delay constraints for this group. Input Strobe Setup Delay Constraint Input Strobe Hold Delay Constraint Constraint in ns Constraint in ns 0.03 ns Specifies the group's input setup delay constraint against the input strobe ns Specifies the group's input hold delay constraint against the input strobe. continued... 45

46 GUI Name Values Default Values Description Inter Symbol Interference of the Read Channel Constraint in ns 0.09 ns Specifies the Inter Symbol Interference value for DQS signal of read channel. Specify a positive value to decrease the setup and hold slack by half of the entered value. Generate Output Delay Constraints for this group On, Off On Instructs SDC to generate set_output_delay constraints for this group. Output Strobe Setup Delay Constraint Output Strobe Hold Delay Constraint Inter Symbol Interference of the Write Channel Constraint in ns Constraint in ns Constraint in ns 0.03 ns Specifies the group's output setup delay constraint against the input strobe ns Specifies the group's output hold delay constraint against the input strobe ns Specifies the Inter Symbol Interference value for DQS signal of write channel. Specify a positive value to decrease the setup and hold slack by half of the entered value. Group <x> Dynamic Reconfiguration Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled. Dynamic Reconfiguration Read Deskew Algorithm DQ Per-Bit Deskew, DQ Group Deskew, Custom Dekew DQ Per-Bit Deskew Specifies the Read Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: DQ Per-Bit Deskew: Each DQ pin is adjusted independently to minimize the skew within the DQ bits. DQS signal is adjusted to center-align to the de-skewed DQ bus. Each DQ bit may have different delay chain settings. DQ Group Deskew: DQS signal is adjusted center-align to the DQ bus without de-skewing individual DQ bits. All DQ bits within the same group has same delay chain settings. Custom Dekew: DQS is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter. Setup Slack Recoverable of Custom Read Deskew Algorithm Hold Slack Recoverable of Custom Read Deskew Algorithm Constraint in ns Constraint in ns 0.0 ns Specifies the amount of positive setup slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew 0.0 ns Specifies the amount of positive hold slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew Dynamic Reconfiguration Write Deskew Algorithm DQ Per-Bit Deskew, DQ Group Deskew, Custom Dekew DQ Per-Bit Deskew Specifies the Write Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: continued... 46

47 GUI Name Values Default Values Description DQ Per-Bit Deskew: DQS signal is centered to each individual DQ bits. Each DQ bit may have different delay chain settings. DQ Group Deskew: DQS signal is centered to the DQ bus group. All DQ bits within the same group has same delay chain settings. Custom Dekew: DQS is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter. Setup Slack Recoverable of Custom Write Deskew Algorithm Hold Slack Recoverable of Custom Write Deskew Algorithm Constraint in ns Constraint in ns 0.0 ns Specifies the amount of positive setup slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew 0.0 ns Specifies the amount of positive hold slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew Related Links Read Latency KDB link to Unsupported OCT enable size values for Arria 10 Altera PHYLite. Applicable to Quartus Prime software version prior to Table 23. Minimum Read Latency This table is applicable to Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle) Full rate Half rate Quarter rate 1 7 continued... 47

48 Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle) Write Latency Table 24. Maximum Write Latency This table is applicable to Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. Core Clock Rate VCO Multiplier Factor Write Latency (External Memory Clock Cycle) Full rate Half rate Quarter rate Signals Clock and Reset Interface Signals Table 25. Clock and Reset Interface Signals Signal Name Direction Width Description ref_clk Input 1 Reference clock for the PLL. The reference clock must be synchronous with strobe_in to ensure the dqs_enable signal is in-sync with strobe_in. reset_n Input 1 Resets the interface. This signal is asynchronous. interface_locked Output 1 Interface locked signal from Intel FPGA PHYLite for Parallel Interfaces IP core to Intel FPGA core. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal. core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter. 48

49 Output Path Signals Table 26. Output Path Signals Output path signals are signals that are available when you set the Pin Type parameter to either Output or Bidirectional. Signal Name Direction Width Description oe_from_core Input Quarter-rate: 4 x PIN_WIDTH Half-rate: 2 x PIN_WIDTH Full-rate: 1 x PIN_WIDTH Output enable signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. data_from_core Input Quarter rate-ddr: 8 x PIN_WIDTH Half-rate DDR: 4 x PIN_WIDTH Full-rate DDR: 2 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH Half-rate SDR: 2 x PIN_WIDTH Full-rate SDR: 1 x PIN_WIDTH Data signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. strobe_out_in Input Quarter-rate: 8 Half-rate: 4 Full-rate: 2 strobe_out_en Input Quarter-rate: 4 Half-rate: 2 Full-rate: 1 Strobe signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. Note: This path is always DDR. Strobe output enable from Intel FPGA core. Synchronous to the core_clk output from the IP core. data_out/data_io Output/ Bidirectional 1 to 48 if data configuration is Single Ended 1 to 24 if data configuration is Differential (Intel Arria 10 and Intel Cyclone 10 GX devices) Data output from Intel FPGA PHYLIte for Parallel Interface IP core. Synchronous to the strobe_out or strobe_io output from the IP core. If the Pin Type parameter is set to Output, the data_out signals are used. If the Pin Type parameter is set to Bidirectional, the data_io signals are used. Note: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. data_out_n/ data_io_n strobe_out/ strobe_io Output/ Bidirectional Output/ Bidirectional 1 to 24 Negative data output from Intel FPGA PHYLIte for Parallel Interface IP core is enabled when data configuration is set to Differential. Data is synchronous to the strobe_out or strobe_io output from the IP core. If the Pin Type is set to Output, the data_out_n ports are used. If the pin type is set to Bidirectional, the data_io_n ports are used. Note: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. 1 Positive output strobe from Intel FPGA PHYLIte for Parallel Interface IP core. If the Pin Type is set to Output, the strobe_out signal is used. If the Pin Type is set to Bidirectional the strobe_io signal is used. The Use Separate Strobes continued... 49

50 Signal Name Direction Width Description parameter forces the use of the strobe_out signal with a Bidirectional Pin Type. strobe_out_n/ strobe_io_n Output/ Bidirectional 1 Negative output strobe from Intel FPGA PHYLIte for Parallel Interface IP core. This is used if the Strobe Configuration is set to Differential or Complementary. If the Pin Type is set to Output, the strobe_out_n signal is used. If the Pin Type is set to Bidirectional, the strobe_io_n signal is used. The Use Separate Strobes parameter forces the use of the strobe_out_n signal with a Bidirectional Pin Type. Input Path Signals Table 27. Input Path Signals Input path signals are signals that are available when you set the Pin Type parameter to Input or Bidirectional. Signal Name Direction Width Description data_to_core Output Quarter-rate DDR: 8 x PIN_WIDTH Half-rate DDR: 4 x PIN_WIDTH Full-rate DDR: 2 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH Half-rate SDR: 2 x PIN_WIDTH Full-rate SDR: 1 x PIN_WIDTH rdata_en Input Quarter-rate: 4 Half-rate: 2 Full-rate: 1 rdata_valid Output Quarter-rate: 4 Half-rate: 2 Full-rate: 1 Valid on rdata_valid. Synchronous to the core_clk output from the Intel FPGA PHYLite for Parallel Interfaces IP core. This signal is set to high for the number of expected read words after a read command is issued. Synchronous to the core_clk output from the Intel FPGA PHYLite for Parallel Interfaces IP core. Delayed by READ_LATENCY with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles. Synchronous to the core_clk output from the Intel FPGA PHYLite for Parallel Interfaces IP core. data_in/ data_io Input/ Bidirectional 1 to 48 if data configuration is Single Ended 1 to 24 if data configuration is Differential (Intel Arria 10 and Intel Cyclone 10 GX devices) Data input from pin. Synchronous to the strobe_in or strobe_io input. The first data_in must be associated with positive edge of strobe_in/ strobe_io. If the pin type is set to Input, the data_in ports are used. If the pin type is set to bidirectional, the data_io ports are used. continued... 50

51 Signal Name Direction Width Description Note: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. data_in_n/ data_io_n strobe_in/ strobe_io strobe_in_n/ strobe_io_n Input/ Bidirectional Input/ Bidirectional Input/ Bidirectional 1 to 24 Negative data input from pin enabled when data configuration is set to Differential. Data is synchronous to the strobe_in or strobe_io input. If the pin type is set to Input, the data_in_n ports are used. If the pin type is set to bidirectional, the data_io_n ports are used. Note: Intel Stratix 10 PHYLite for Parallel Interfaces IP core does not support differential data pins. 1 Positive strobe from pin. If the pin type is set to Input, the strobe_in signal is used. If the pin type is set to Bidirectional, the strobe_io signal is used. 1 Negative strobe from pin. This is used if the Strobe Configuration parameter is set to Differential or Complementary. If the pin type is set to Input, the strobe_in_n signal is used. If the pin type is set to Bidirectional, the strobe_io_n signal is used. 51

52 Avalon Configuration Bus Interface Signals The Intel FPGA PHYLite for Parallel Interfaces IP core exposes the Avalon-MM slave and Avalon-MM master interfaces when you perform dynamic reconfiguration. Connect the Avalon-MM slave to either a master in the core or the master interface of either an Intel FPGA PHYLite for Parallel Interfaces IP core or the Intel FPGA External Memory Interfaces IP core to be placed in the same column. You can only connect the master interface to the slave interface of an Intel FPGA PHYLite for Parallel Interfaces IP core or Intel FPGA External Memory Interfaces IP core to be placed in the same column. Table 28. Avalon-MM Master Interface Signals Signal Name Direction Width Description avl_clk Input 1 Avalon interface clock. avl_reset_n Input 1 Reset input synchronous to avl_clk. avl_read Input 1 Read request from io_aux. This signal is synchronous to the avl_clk input. avl_write Input 1 Write request from io_aux. This signal is synchronous to the avl_clk input. avl_byteenable Input 4 Controls which bytes should be written on avl_writedata. avl_writedata Input 32 Write data from io_aux. This signal is synchronous to the avl_clk input. avl_address Input 32 (Intel Stratix 10 devices) 28 (Intel Arria 10 and Intel Cyclone 10 GX devices) Address from io_aux. This signal is synchronous to the avl_clk input. avl_readdata Output 32 Read data to io_aux. This signal is synchronous to the avl_clk input. avl_writedata Input 32 Write data from io_aux. This signal is synchronous to the avl_clk input. avl_readdata_valid Output 1 Indicates that read data has returned. avl_waitrequest Output 1 Stalls upstream logic when it is asserted. Table 29. Avalon-MM Slave Interface Signals Signal Name Direction Width Description avl_out_clk Output 1 Connect this signal to the input Avalon interface of another Intel FPGA PHYLite for Parallel Interfaces IP core or the Arria 10 External Memory Interfaces IP. avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of another Intel FPGA PHYLite for Parallel Interfaces IP core or the Arria 10 External Memory Interfaces IP. avl_out_read Output 1 Indicates read transaction. avl_out_write Output 1 Indicates write transaction. avl_out_byteenable Output 4 Controls which bytes should be written on avl_out_writedata. continued... 52

53 Signal Name Direction Width Description avl_out_writedata Output 32 The data packet associated with the write transaction. avl_out_address Output 32 (Intel Stratix 10 devices) 28 (Intel Arria 10 and Intel Cyclone 10 GX devices) Avalon address (in byte granularity). Value is identical to avl_address but with zeroes padded on the LSBs. avl_out_readdata Input 32 The data packet associated with avl_out_readdata_valid. avl_out_readdata_val id Input 1 Indicates that read data has returned. avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted. Related Links Dynamic Reconfiguration on page 28 For more information about connecting these signals Design Example The Intel FPGA PHYLite for Parallel Interfaces IP core is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP core and what behavior to expect in a simulation. Note: The.qsys files are for internal use during design example generation only. You should not edit the files. Generate the Design Example You can generate a design example by clicking Generating Example Design in the IP Parameter Editor. The software generates a user defined directory in which the design example files reside. There are two variants of design example available for Intel FPGA PHYLite for Parallel Interfaces IP core: Variant without dynamic reconfiguration design example Variant with dynamic reconfiguration design example 53

54 Table 30. Intel FPGA PHYLite for Parallel Interfaces IP Core Design Example Variants Design Example Variant Design Files Description Dynamic Reconfiguration OFF ed_synth.qsys (synthesis only) ed_sim.qsys (simulation only) Consists of configurable Intel FPGA PHYLite for Parallel Interfaces IP core instance. Consists of sim_ctrl, agent, addr/cmd and Intel FPGA Phylite for Parallel Interfaces IP core instances. Perform read and write transaction verification. ON ed_synth.qsys (synthesis only) phylite_debug_kit.qsys (synthesis only) ed_sim.qsys (simulation only) Consists of IOAUX and Intel FPGA PHYlite for Parallel Interfaces IP core instances. You need to instantiate NIOS and AVL_Controller manually or create user logic to perform address translation. Consists of NIOS, AVL_Controller, API functions, IOAUX and Intel FPGA PHYLite for Parallel Interfaces IP core instances. A recommended example design to perform dynamic reconfiguration. This design example does not support simulation. Consists of sim_ctrl, agent, addr/ cmd, cfg_ctrl, avl_ctrl and Intel FPGA PHYLite for Parallel Interfaces IP core instances. This design example demonstrates dynamic reconfiguration and uses FSM to perform calibration. Design Example without Dynamic Reconfiguration When the Enable dynamic reconfiguration option is not selected, Intel Quartus Prime software generates a design example of Intel FPGA PHYLite for Parallel Interface IP core without a dynamic reconfiguration module. This design example consists of simulation and synthesis design files. Generate the Hardware Design Example The make_qii_design.tcl generates a synthesizable hardware design example along with a Quartus project, ready for compilation. To generate synthesizable design example, run the following script at the end of IP generation: quartus_sh -t make_qii_design.tcl To specify an exact device to use, run the following script: quartus_sh -t make_qii_design.tcl [device_name] This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project with the Intel Quartus Prime software. 54

55 Generate the Simulation Design Example The make_sim_design.tcl generates a simulation design example along with toolspecific scripts to compile and elaborate the necessary files. To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation: quartus_sh -t make_sim_design.tcl VERILOG To generate the design example for a VHDL-only simulator, run the following script: quartus_sh -t make_sim_design.tcl VHDL This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation with the corresponding tool. The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation iterates over each group in your configured IP and performs basic reads/writes to an associated agent (one per group) in the testbench. A simple one group Intel FPGA PHYLite instantiation in the testbench is used for basic address and command outputs to the agent. A side bus between the sim_ctrl and the agents is used to check that the reads and writes are valid. Figure 22. High-Level View of the Simulation Design Example with One Group sim_ctrl Side read/write command Side read/write data Agent (one per group in DUT) DRAM clock Core clock Read/Write command PHYLite ADDR/CMD Core clock DRAM clock DRAM clock Write command Read command Agent select Latency Delays Core clock Read/Write enable PHYLite DUT data data Core clock DRAM clock strobe DRAM clock Dynamic Reconfiguration Design Examples When you select the Use dynamic reconfiguration option and click on Generate Example Design, Intel Quartus Prime software generates two design examples: Dynamic reconfiguration with debug kit design example Dynamic reconfiguration with configuration control module Dynamic Reconfiguration with Debug Kit This design example provides you a synthesizable system capable to perform dynamic calibration for Intel FPGA PHYLite for Parallel Interface IP core in Intel Arria 10 and Intel Cyclone 10 GX devices. 55

56 The design example includes: A fully configurable Intel FPGA PHYLite for Parallel Interface IP An Avalon controller to perform address translation A NIOS II processor to perform dynamic calibration for Intel FPGA PHYLite for Parallel Interface IP core A set of application program interface (API) to configure delay chains for Intel FPGA PHYLite for Parallel Interface IP core Figure 23. Dynamic Reconfiguration with Debug Kit Design Example NIOS II Avalon Controller Bus AVL_CTRL Avalon Controller Bus Intel FPGA PHYLite for Parallel Interface DUT Intel FPGA PHYLite for Parallel Interface IP Table 31. Dynamic Reconfiguration with Debug Kit Design Example Generated Files Example Design Files debug_kit_readme.txt hello_world.c phylite_debug_kit.qsys phylite_dynamic_reconfigurations.c phylite_dynamic_reconfiguration.h phylite_niosii_bridge.v phylite_niosii_bridge_hw.tcl issp.tcl and Description This file provide simple instructions to generate and use the example design. This is the main test program. This is the system design file. This file contains the set of APIs use in the test program. This is the header file for the APIs. This is an interconnect module between Altera PHYLite for Parallel Interface IP core and NIOS II processor. This is the In-System Source and Probes module. Use this file to reset the system and to probe the status of the interface_locked signal and dynamic calibration done status from NIOS II processor. Table 32. API Functions in Dynamic Reconfiguration Debug Kit Design Example API Function Argument Return Value Description hw_get_num_groups ID Integer Read from AVL_CTRL_REG_NUM_GROUPS register for the specified ID. hw_get_group_info ID, GROUP_NUM {16'h0000, num_lanes[7:0], num_pins[7:0]} Read from AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number. The return values are the number of lanes and number of pins available for the specified ID and group number. hw_get_num_lanes ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number. The return values are the number of lanes available for the specified ID and group number. continued... 56

57 API Function Argument Return Value Description hw_get_num_pins ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number. The return values are the number of pins available for the specified ID and group number. hw_get_input_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_IDELAY register for the specified ID, group number, and pin ID. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_get_output_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_ODELAY register for the specified ID, group number and pin number. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_get_strobe_input_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_DELAY delay register for the specified ID, group number and pin number. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_get_strobe_enable_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_EN_DELAY register for the specified ID, group number and pin number. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_get_strobe_enable_phase ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the specified ID, group number and pin number. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_get_read_valid_enable_de lay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_RD_VALID_DELAY register for the specified ID, group number and pin number. Specified CSR to: 0 to read from Avalon Controller register 1 to read from CSR register hw_set_input_delay ID, GROUP_NUM, PIN_NUM, input delay value (integer) Write to AVL_CTRL_REG_IDELAY register for the specified ID, group number and pin number. continued... 57

58 API Function Argument Return Value Description Refer to Table 16 on page 30 for valid value range. hw_set_output_delay hw_set_strobe_input_delay hw_set_strobe_enable_delay hw_set_strobe_enable_phase hw_set_read_valid_enable_de lay ID, GROUP_NUM, PIN_NUM, output delay value (integer) ID, GROUP_NUM, PIN_NUM, strobe input delay value (integer) ID, GROUP_NUM, PIN_NUM, strobe enable delay value (integer) ID, GROUP_NUM, PIN_NUM, strobe enable phase value (integer) ID, GROUP_NUM, PIN_NUM, read valid enable delay value (integer) Write to AVL_CTRL_REG_ODELAY register for the specified ID, group number and pin number. Refer to Table 16 on page 30 for valid value range. Write to AVL_CTRL_REG_DQS_DELAY register for the specified ID, group number and pin number. Refer to Table 16 on page 30 for valid value range. Write to AVL_CTRL_REG_DQS_EN_DELAY register for the specified ID, group number and pin number. Refer to Table 16 on page 30 for valid value range. Write to AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the specified ID, group number and pin number. Refer to Table 16 on page 30 for valid value range. Write to AVL_CTRL_REG_RD_VALID_DELAY register for the specified ID, group number and pin number. Refer to Table 16 on page 30 for valid value range. Related Links Example Design Avalon Controller on page 39 Generate the Dynamic Reconfiguration with Debug Kit Design Example 1. In Intel Quartus Prime software, instantiate Intel FPGA PHYLite for Parallel Interface IP core and turn on the Use dynamic reconfiguration option. 2. Click Generate Example Design. Specify a directory name to generate the example design. 3. In your example design directory, open the phylite_debug_kit.qsys file. 4. Select your device in the Device Family tab and click Generate HDL to generate the design example files. 5. In the Quartus, select File New Project Wizard to create a new project directory and specify phylite_debug_kit as the project name. Add the phylite_debug_kit.qip file in the newly created project directory when prompted. 6. In Intel Quartus Prime software, select Tools Nios II Software Build Tool for Eclipse. Create a new workspace when prompted. 7. In Nios II - Eclipse software, select File New Nios II Application and BSP from Template. 58

59 8. In the Nios II Application and BSP from Template window, select phylite_debug_kit_sopcinfo file in SOPC Information File name parameter to load the CPU settings. 9. Specify a project name in the Project name parameter. 10. Select Hello World for the Project Template. 11. Click Finish to generate the project. 12. Copy hello_world.c, phylite_dynamic_reconfiguration.c, and phylite_dynamic_reconfiguration.h files from the generated example design folder into your Eclipse project folder. You can refresh the Nios II Eclipse window by pressing F5 to make sure these files are added into your Eclipse project. 13. In the Nios II Eclipse window, click Project Build Project to generate.elf file. 14. Run the following command in Nios II Command Shell to convert the.elf file into.hex. elf2hex --input=<elf_filename.elf --base=0x end=0x7ffff --width=32 --output=phylite_debug_kit_inst_mem.hex 15. Copy and add the phylite_debug_kit_inst_mem.hex file into the ed_synth project folder. 16. Add the following command in the ed_synth.qsf to include the phylite_debug_kit_inst_mem.hex in your project compilation. set_global_assignment -name MISC_FILE phylite_debug_kit_inst_mem.hex 17. Compile the ed_synth project file to generate.sof file to run the example design on your hardware. Run the Dynamic Reconfiguration with Debug Kit Design Example 1. Download the phylite_debug_kit.sof file into the FPGA. 2. From the Quartus installation directory, double click on the Nios II Command Shell.bat to launch the Intel Nios II command shell (command shell A). Repeat the same step to launch a second command shell (command shell B). 3. In command shell B, use the following command to run Nios II terminal application for result printouts. nios2-terminal --cable=<jtag_cable_num> 4. Use the following command in command shell A to reset the system and start the dynamic reconfiguration application. quartus_stp -t issp.tcl phylite_debug_kit.qpf Dynamic Reconfiguration Using Finite State Machine Features Perform dynamic reconfiguration using Avalon controller Read and write transactions monitoring Delay values monitoring 59

60 Software Requirements Functional Description Intel Quartus Prime software Active-HDL, ModelSim* - Intel FPGA Edition, NCsim or VCS Simulator This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with the sim_ctrl module to demonstrate the basic functionality of the Intel FPGA PHYLite IPs Avalon-MM based reconfiguration. The agent is also modified to insert delays on the data and clocks, which the new modules will compensate for. NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops at the first working delay values. The design example only support simulation. A robust calibration algorithm should sweep over the entire valid range of delays to choose the correct value for the application. Figure 24. Dynamic Reconfiguration Using Finite State Machine Design Example This figure shows a high-level view of the simulation design example with one group. sim_ctrl Side read/write command Side read/write data Agent (one per group in DUT) ref_clk_gen ref_clk reset_gen DRAM clock Core clock Reconfiguration Flow Control Core clock Lock Data Dynamic Reconfiguration Only Read/Write command Driver ref_clk PHYLite DUT Core clock Read/Write enable Data Strobe Lock PHYLite ADDR/CMD ref_clk Core clock Core clock DRAM clock DRAM clock Avalon Bus reset_n reset_n DRAM clock Write command Read command Agent select Data strobe Latency Delays DRAM clock cfg_ctrl Avalon Bus avl_ctrl Table 33. Design Components Description Component Description ref_clk_gen reset_gen Generates clock to reset_gen, PHYLite ADDR/CMD (ref_clk), and PHYLite DUT (ref_clk) blocks. Generates reset to PHYLite ADDR/CMD and PHYLite DUT blocks. sim_ctrl Generates read/write commands to PHYLite ADDR/CMD block. Generates side read/write commands and data to Agent block. Generates strobe and data to Driver block. Driver PHYLite ADDR/CMD Generates strobe and data for each group and to PHYLite_DUT block. Passing read/write commands and command clock from sim_ctrl to Agent. continued... 60

61 Component Description Agent cfg_ctrl avl_ctrl FIFO to store data from PHYLite DUT and side read/write data from sim_ctrl block. This is configuration control block which performs read and write delay calibration before test begin. The calibration results is passed to the PHYLite DUT through Avalon Controller. Contains 4 FSMs: 1. Main FSM cfg_ctrl state 2. Write Strobe FSM Calibration state for Output Strobe 3. Read Strobe FSM Calibration state for Input Strobe 4. Read Enable FSM Calibration state for Strobe Enable and Input Data The Avalon controller is used to perform address translation to store delay settings from the calibration done by cfg_ctrl block. 61

62 Figure 25. Design Example Functional Flow Start Reset cfg_ctrl module Dynamically reconfigure data group's settings Function name: reconfigure_grp Output Dynamically reconfigure write strobe setting Function name: reconfigure_grp_write a) Read from Pin Output Phase CSR register b) Write to DUT and read back c) If fail, update Pin Output Phase Avalon register d) Repeat step b) and c) until pass e) Done Write data to DUT and read back to verify data is correct Pin Type? Bidirectional Dynamically reconfigure write strobe setting Function name: reconfigure_grp_write a) Read from Pin Output Phase CSR register b) Write to DUT and read back c) If fail, update Pin Output Phase Avalon register d) Repeat step b) and c) until pass e) Done Write data to DUT and read back to verify data is correct Input Simulation ends Dynamically reconfigure read strobe setting Function name: reconfigure_grp_read a) Read from Strobe PVT Compensated Input Delay CSR register b) Write to Agent and read back c) If fail, update Strobe PVT Compensated Input Delay Avalon register d) Repeat step b) and c) until pass e) Done Dynamically reconfigure read enable and input data settings Function name: reconfigure_grp_read_en_and_data a) Read from Strobe Enable Phase CSR register b) Write to Agent and read back c) If data[0] is mismatched, update Strobe Enable Phase Avalon register d) Repeat step b) and c) until data[0] is matched e) Get number of data pin f) Write to Agent and read back g) If fail, update Pin PVT Compensated Input Delay Avalon register h) Repeat f) and g) until pass i) Done Write data to Agent and read back to verify data is correct Simulation ends Related Links Example Design Avalon Controller on page 39 62

63 Generate the Dynamic Reconfiguration with Configuration Control Module Design Example 1. In Intel Quartus Prime software, instantiate Intel FPGA PHYLite for Parallel Interface IP core. 2. Customize parameter settings per your requirement and turn on the Use dynamic reconfiguration option. 3. Click Generate Example Design. Specify a directory name to generate the design example. 4. To generate Verilog or mixed-language simulation files, go to the design example directory and run the following script in Nios II Command Shell. quartus_sh -t make_sim_design.tcl VERILOG 5. To generate VHDL simulation files, go to the design example directory and run the following script in Nios II Command Shell. quartus_sh -t make_sim_design.tcl VHDL Run the Dynamic Reconfiguration with Configuration Control Design Example Follow these steps to compile and simulate the design: 1. Change the working directory to <Example Design>\sim\ed_sim\sim \<Simulator>. 2. Run the simulation script for the simulator of your choice. Refer to the table below. Simulator Working Directory Steps Modelsim VCS VCSMX NCSim Aldec <Example Design>\sim\ed_sim \sim\mentor <Example Design>\sim\ed_sim \sim\synopsys\vcs <Example Design>\sim\ed_sim \sim\synopsys\vcsmx <Example Design>\sim\ed_sim \sim\cadence Example Design\sim\ed_sim\sim \aldec a. do msim_setup.tcl b. ld_debug c. Add desired signals into the waveform window. d. run -all a. sh vcs_setup.sh a. sh vcsmx_setup.sh a. sh ncsim_setup.sh a. do rivierapro_setup.tcl b. ld_debug c. Add desired signals into the waveform window. d. run -all 63

64 Figure 26. Sample of Simulation Output Application Specific Design Example This design example demonstrates the Intel FPGA PHYLite implementation for a NAND Flash design. The following figure shows the RTL view of the design example. 64

65 Figure 27. RTL Viewer for a NAND Flash Simple Design Based on the Intel FPGA PHYLite for Parallel Interfaces IP Core Related Links Altera PHYLite NAND FLASH Design Example Implementation using the Intel FPGA PHYLite for Parallel Interfaces IP Core You can configure the the Intel FPGA PHYLite for Parallel Interfaces IP core to support multiple groups (maximum 48 I/O pins each). The following lists the possible implementations: Instantiates one Intel FPGA PHYLite for Parallel Interfaces IP core with two groups Bidirectional type for DQ and DQS signals Output type for Addr/Cmd signals Note: Figure 28. Each group in the Intel FPGA PHYLite for Parallel Interfaces IP core can have 48 I/Os, and the IP supports up to 18 groups. General Tab Settings 65

66 Figure 29. Group 0 settings (Bidirectional type for DQ and DQS) 66

67 Figure 30. Group 1 settings (Output type for Addr/Cmd) Related Links Altera PHYLite NAND FLASH Design Example Document Archives If an IP core version is not listed, the user guide for the previous IP core version applies. IP Core Version User Guide 17.0 Altera PHYLite for Parallel Interfaces IP Core User Guide 16.0 Altera PHYLite for Parallel Interfaces IP Core User Guide 15.1 Altera PHYLite for Parallel Interfaces IP Core User Guide 14.1 Altera PHYLite for Parallel Interfaces IP Core User Guide 67