Chapter 15 PCI Implementation Example
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1 Chapter 15 PCI Implementation Example PC Architecture for Technicians: Level-1 Systems Manufacturing Training and Employee Development Copyright 1996 Intel Corp. Ch 15 - Page 1
2 OBJECTIVES: At the end of this section, the student will be able to do the following: l Discuss an example PCI ChipSet Implementation. nthe 82430FX PCIset 3[TSC] FX T System Controller 3[TDP] FX T Data Path (2-required) 3[PIIX] FB PCI-ISA-IDE Xcellerator nan overview of the PC87306 Ultra I/O Ch 15 - Page 2
3 Low, Mid- Range Desktop Platform Processor TSC/TDP Bridge/ Memory Controller Cache DRAM Graphics PCI Local Bus PIIX Exp Bus Xface Fax Modem LAN ISA/EISA - MicroChannel R Auto Configuration Ready Low System Cost Ch 15 - Page 3
4 The 82430FX ChipSet Ch 15 - Page 4
5 The 82430FX ChipSet lthe 82430FX ChipSet consists of (3) device types: n[tsc] FX T System Controller n[tdp] FX T Data Path (2-required) n[piix] FB PCI-ISA-IDE Xcellerator lthe PCIset forms a Host-to-PCI bridge and provides the second level cache control and a full function 64- bit data path to main memory. lthe TSC integrates the cache and main memory DRAM control functions and provides bus control for transfers between the CPU, cache, main memory, and the PCI Bus. Ch 15 - Page 5
6 Typical System Board w/ T-FX ChipSet Host Addr P54C CPU Host Ctrl Host Data TDP CTRL TAG 32K X 8 SRAM TSC DRAM DRAM MD MD TDP TDP PCI Conn PCI A/D PCI Ctrl Plink Bus ISA Conn PIIX BIOS ISA BUS SA 19:0 VIDEO SD 15:0 ISA Ctrl UIO Ch 15 - Page 6
7 82437FX TSC Ch 15 - Page 7
8 82437FX TSC Simplified Block Diagram CPU Address CPU Control Host Interface PCI Interface PCI Address / Data PCI Control Cache Control TAG ADDRESS HCLKIN PCLKIN Cache Interface Clocks DRAM Interface TDP Interface RAS(4:0)# CAS(7:0)# Memory Address PLINK(15:0) TPD Control Ch 15 - Page 8
9 T System Controller The core logic lthe T-FX System Controller is the heart and programmable intelligence of the Host-to-PCI bridge. ncpu clock 66/60/50Mhz npci clock 1/2 CPU clock speed lthe TSC provides; nfully synchronous CPU-to-PCI interface nsecond Level Cache Interface nhost and PCI Address Decode npci Bus Arbitration ncpu-to-pci (memory) write posting Ch 15 - Page 9
10 82430FX PCIset 82437FX TSC Integrated Second Level Cache Controller ldirect Mapped Organization lwrite-back Cache Policy lcacheless, 256K-KByte, or 512-KByte configurations. Integrated DRAM Controller l64-bit Data Path to Memory na dedicated memory DATA bus is used to connect the TDPs to DRAM. (MD 63:0) l4 MBytes to 128 MBytes Main Memory ledo/hyper Page Mode DRAM or Standard Page Mode DRAMs. Ch 15 - Page 10
11 The 82430FX ChipSet lthe TSC and TDPs interface with the Pentium Processor Host Bus, and the PCI bus. ntwo TDP s are required for the 82430FX PCIset system configuration. 3The T-FX Data Paths are sophisticated data buffers. 3The TSC controls the data flow through the TDP s with the TDP Control Signals. lthe TDP s provide the data path for host-to-main memory, PCI-to-main memory, and host-to-pci cycles. nconnects to the (64-bit) Host Data Bus nconnects to the (64-bit) Memory Data Bus nconnects to the (16-bit) PLINK Bus Ch 15 - Page 11
12 PLINK BUS (15-0) The 82430FX ChipSet lthe PLINK bus is used to connect the PCI bus with the TDP, through the TSC. lbi-directional (16-bit) DATA bus between the T-FX Data Paths and the T-FX System Controller. nactive in CPU-PCI data transfers; nactive in PCI-Memory data transfers; nactive in CPU-TSC register accesses; Host Bus Clock rate for faster transfers. 3e.g. Host Bus 66 MHz, PCI 33 MHz Ch 15 - Page 12
13 TDP 64- Bit Data Path Partitioning Odd Order TDP Byte Lanes 1,3,5 & 7 Even Order TDP Byte Lanes 0,2,4 & 6 MD (63:56, 47:40, 31:23, 15:8) HD(31:0) HD (63:56, 47:40, 31:23, 15:8) MD (56:48, 39:32, 23:16, 7:0) HD(31:0) HD (56:48, 39:32, 23:16, 7:0) MD(31:0) MD(31:0) PLINK (15:8) PLINK(7:0) PLINK (7:0) PLINK(7:0) HOE# MOE# POE# PCMD(1:0) MSTB # MADV# HOE# MOE# POE# PCMD(1:0) MSTB # MADV# HOE# MOE# POE# PCMD(1:0) MSTB # MADV# HOE# MOE# POE# PCMD(1:0) MSTB # MADV# HCLK HCLK Ch 15 - Page 13
14 PIIX (PCI ISA/ SA/IDE Xcellerator) Ch 15 - Page 14
15 PIIX Introduction lthe PIIX (PCI ISA/IDE Xcellerator) component provides the bridge between the PCI and ISA busses. nisa Master/Slave Interface npci clock support range 25-33Mhz nisa clock support range Mhz lthe PIIX integrates many common I/O functions found in ISA based PC systems along with a fast IDE interface. Ch 15 - Page 15
16 PIIX Simplified Block Diagram PCI Addr / Data PCI Control PWROK CPURST PCIRST# RSTDRV INIT PCI Bus Interface System Reset ISA Bus Interface ISA, Address ISA DATA ISA Control IRQ8# IRQ12/M INTR NMI IRQ(15,14, 11:9,7:3,1) PIRQ(A:D)# Interrupt IDE Interface DDRQ(1:0) IDE DATA IDE Control DD(14:13) SPKR OSC DREQ(7:5,3:0) DACK (7:5,3:0)# TC REFRESH# Timers / Counters DMA X-Bus Support Logic XDIR# XOE# RTCALE FERR# IGNNE# BIOSCS# RTCCS# KBCS# Ch 15 - Page 16
17 82371FB PCI ISA IDE XCELLERATOR (PIIX) lbridge & Interface between the PCI Bus and ISA Bus nfunctionality of one 82C54 Timer 3System Timer; Refresh Request; Speaker Tone Output nfunctionality of two 82C59 Interrupt Controllers nnon-maskable Interrupts (NMI) 3IOCHK# or PCI System Error Reporting (SERR#) nfunctionality of two 8237 DMA Controllers 3Compatible DMA Transfers nx-bus Peripheral Support 3Chip Select Decode (BIOSCS#, KBCS#, RTCCS#) nfast IDE Interface (Function 1) Ch 15 - Page 17
18 87306 Super I/O Ch 15 - Page 18
19 87306 Super I/O loften referred to as Ultra I/O, the PC87306VUL incorporates; nkeyboard Controller 3Commands are software compatible with the 8042uC. nreal Time Clock (RTC) 3DS1287 and MC compatible. nfloppy Disk Controller 3Supports 360kb 5.25 through 3.5 4Mb disk media formats. n(2) Fifo d UARTs (serial channels) 3NS16450 or PC16550 equivalent 3Infra-Red Serial Interface Ch 15 - Page 19
20 87306 Super I/O l Ultra I/O, the PC87306VUL incorporates; (Cont.) nenhanced Parallel Port (EPP) 3Extended Capability Port ECP compliant. nide Interface 3The IDE control logic provides a complete IDE interface (except for signal buffers) 3DMA support, including Type-F FAST DMA. lconfiguration registers consist of (18) byte-wide registers. npoint and Shoot addressing configurable within ISA I/O space. (e.g Port 2EH & 2FH) Ch 15 - Page 20
21 Typical System Board w/ T-FX ChipSet Host Addr P54C CPU Host Ctrl Host Data TDP CTRL TAG 32K X 8 SRAM TSC DRAM DRAM MD MD TDP TDP PCI Conn PCI A/D PCI Ctrl Plink Bus ISA Conn PIIX BIOS ISA BUS SA 19:0 VIDEO SD 15:0 ISA Ctrl UIO Ch 15 - Page 21
22 SUMMARY WE HAVE DISCUSSED THE FOLLOWING: l An example PCI ChipSet Implementation. nthe 82430FX PCIset 3[TSC] FX T System Controller 3[TDP] FX T Data Path (2-required) 3[PIIX] FB PCI-ISA-IDE Xcellerator nan overview of the PC87306 Ultra I/O Ch 15 - Page 22
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