ower Management IC for Portable Devices 1-Channel DC/DC Converter + 1-Channel Low-Noise LDO

Transcription

1 P ower Management IC for Portable Devices 1-Channel DC/DC Converter + 1-Channel Low-Noise LDO MB39C22G/MB39C22J MB39C22L/MB39C22N An optimal IC for power management systems in portable devices with one built-in channel of DC/DC step-down converter for digital circuits and one built-in channel of lownoise LDO for analog circuits. It can also be used in products adopting one cell of Li-ion battery as the power supply. Two power management systems in a 3.mm 3.mm, 1-pin package and the built-in switching FET enable the construction of a power management system at a low BOM cost. There are four versions of the fixed output voltage in the LDO block. Introduction Photo 1 External View The MB39C22 Series are optimal power management ICs for the construction of systems for ARM architecture-based system ICs, GPSs, and portable TVs. Low-noise LDO is demanded for power supplies for RF, PLL, and analog functions. This product is a 2-channel power management IC combining a DC/DC converter and a low-noise LDO. It is useful in electronic devices with mixed analog and digital components.

2 Product Features Input voltage range: 2.5V to 5.5V Output voltage/current DC/DC block (CH1): Voltage setting range:.8v to 4.5V Current: 6mA (Max.) LDO block (CH2): Output voltage (fixed): 3.3V, 2.85V, and 1.2V Current: 3mA (Max.) The DC/DC circuit adopts the PFM/PWM mode to improve efficiency under light load. The current mode architecture is also adopted to achieve high-speed load response. The LDO circuit is optimal for power supplies of analog circuits such as RF as it satisfies the low-noise requirement. The built-in Power on Reset () function enables the construction of the power startup sequence without signals from an MCU. Rich protective functions Short-circuit protection (SCP), over-current protection (OCP), over-temperature protection (OTP), and under-voltage lockout (UVLO) are provided. Package: SON-1 (Photo 1) Adoption of the SON package contributes to the reduction in the board area of power management circuit. 3.mm 3.mm.75mm (lead pitch.5mm) Figure 1 presents the conversion efficiency of the DC/DC block of this product, Figure 2 its load stability, Figure 3 its input stability, Figure 4 its switching waveforms, and Figure 5 its load transient response. Figure 6 presents the load stability of the LDO block of MB39C22G, Figure 7 its input stability, and Figure 8 its power supply rejection ratio (PSRR). Functions PFM/PWM control circuit (CH1) The frequency (2.MHz) set up by the built-in oscillator (square wave oscillating circuit) is used to enable synchronous rectification operation of the built-in P channel MOS FET and N channel MOS FET. PFM operation is executed under light loads. Figure 1 Conversion Efficiency of MB39C22 DC/DC Block Efficiency (%) VIN = 5.5 V IO1 Load Current (A) Figure 2 Load Regulation of MB39C22 DC/DC Block VO1 Output Voltage (V) IO1 Load Current (A) VIN = 5.5 V Figure 3 Line Regulation of MB39C22 DC/DC Block Figure 4 Switching Waveform of MB39C22 DC/DC Block VO1 Output Voltage (V) VIN Input Voltage (V) IO1 = ma IO1 = 3 ma IO1 = 6 ma VLx 5 V/div ILx 1mA/div VO1 VO2 EN1=EN2=VIN=3.7V; VO1=;IO1=25mA;C1=1μF;C2=4.7μF VO2=3.3V;IO2=15mA;C4=C5=4.7μF 5 ns/div

3 Iout comparator circuit This circuit detects the current flowing from the built-in P channel MOS FET to the external inductor (ILX). It compares VIDET obtained by I-V conversion of the ILX peak current and the Error Amp. output to turn OFF the built-in P channel MOS FET through the PFM/PWM logic Control circuit. Error Amp.(CH1) phase compensation circuit This circuit compares the VREF reference voltage and the output voltage. The phase compensation circuit of this product is realized by externally attaching a feedback resistor and a capacitor for phase compensation to the FB terminal. LDO circuit (CH2) The built-in low-noise LDO can output currents up to 3mA. A capacitor is required on the VOUT2 pin for stability. Table 1 presents the output settings and power supply rejection ratio (PSRR) of the LDO block of this product. Power on Reset () circuit This circuit monitors the VO1 terminal voltage (CH1 output voltage) via the FB terminal. The pin has open drain output. It is normally used in pull-up with an external resistor. While the pin reaches H level when VO1 reaches the set output voltage, it is set to L level when the output voltage drops due to over current and so forth. VREF circuit It generates a highly precise reference voltage using a BGR (band-gap reference) circuit. Table 1 Output Settings and Power Supply Rejection Ratio (PSRR) of the LDO block Product name Output voltage setting in LDO block PSRR (typical) MB39C22G 3.3V 7dB MB39C22J 2.85V 65dB MB39C22L 6dB MB39C22N 1.2V 55dB Figure 5 Load Transient Response of MB39C22 DC/DC Block Figure 6 Load Regulation of MB39C22G LDO Block IO1 5mA/div VO1 1mV/div VO2 VIN=EN1=EN2=3.7V; T IO1 = 1mA to 4mA IO2 = 15mA VO2 Output Voltage (V) EN2=VIN;EN1=V VIN = 3.7V VIN = 4.3V VIN = 5.5V IO2 Load Regulation (A) 1μs/div Figure 7 Line Regulation of MB39C22G LDO Block Figure 8 Power Supply Rejection Ratio (PSRR) of MB39C22G LDO Block VO2 Output Voltage (V) EN2=VIN;EN1=V IO2 = ma IO2 = 12 ma IO2 = 3 ma VIN Input Voltage (V) PSRR (db) EN2=VIN=3.7V;EN1=V VO2=3.3V;IO2=1mA;C1=C4=μF Freq (khz)

4 Protection circuit The over-temperature protection circuit (OTP) stops the entire output operation at CH1 and CH2 when the junction temperature reaches It restores CH1 and CH2 to normal operation when the junction temperature drops to +11. Since the PFM/ PWM control circuit adopts the current mode architecture for its control method, the current peak value is constantly monitored and controlled. Control circuit Table 2 presents the function control by EN1 and EN2 pins. Figure 9 presents the block diagram for this product. Applications Figures 1 and 11 present application examples. This product is optimal for the following applications: Portable applications GPS, PND Table 2 Function Control by EN1 and EN2 Pins EN1 EN2 CH1 and CH2 VREF,UVLO,OTP L L OFF OFF OFF H L ON OFF ON L H OFF ON ON H H ON ON ON Figure 9 Block Diagram <<CH1 Buck DC/DC>> FB 6 Error Amplifier VIN1 8 ICOMP PFM PWM Logic Control Current Limit DRV LEVEL CONV. LX 9 IO1 (6 ma Max) VO1 (.8 V to 4.5 V) OSC 1 GND1 VIN or VO1 VIN (2.5 V to 5.5 V) 4 OCP <<CH2: LDO>> Error Amplifier VIN2 2 VOUT2 3 GND2 5 IO2 (3 ma Max) VO2 3.3 V: MB39C22G 2.85 V: MB39C22J 1.8 V: MB39C22L 1.2 V: MB39C22N VREF OTP UVLO EN1 7 enb1 (H: CH1 ON) EN2 1 enb2 (H: CH2 ON) <<1 PIN>>

5 MP3, PMP Portable TV, USB dongle (CMMB, DVB-T, DMB-T) SMART-PHONE, etc. Figure 1 Application Example (Portable TV System) Li-ion battery or AC/DC 5V MB39C22G 3.3V 1.2V 1.2V Evaluation Board We offer an evaluation board (Photo 2) to simplify the single unit evaluation of this product. Tuner De-modulator TS MPEG decoder Future Development We plan to successively introduce product versions that offer fixed output voltage of the LDO block in the future. We will continue development to meet our customer needs, aiming to address further miniaturization and cost reduction. Li-ion battery or AC/DC 5V MB39C22L Figure 11 Application Example (USB-SATA Bridge) DDR memory Flash memory Photo 2 Evaluation Board Function button LED TR Quartz oscillator Flash ROM USB2. GPIO USB2.(3.) bridge IC I 2 C I/O port 2.5-inch SATA HDD USB connector USB3. Analog VDD 3.3V Digital VDD MB39C22G I/O port 5V