USER GUIDE FOR IR3899 EVALUATION BOARD

Transcription

1 IRDC3899-PV8 SupIRBuck TM DESCRIPTION USER GUIDE FOR IR3899 EVALUATION BOARD.8Vout The IR3899 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm X 5 mm Power QFN package. Key features offered by the IR3899 include internal Digital Soft Start/Soft Stop, precision 0.5Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias startup. Output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance and the current limit is thermally compensated. This user guide contains the schematic and bill of materials for the IR3899 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3899 is available in the IR3899 data sheet. BOARD FEATURES V in = +2V (+ 3.2V Max) V out = 0-8.5A F s =200kHz L= 0.4uH (Coilcraft XAL , 0.4uH, SMD 4mm x 4mm x 2.mm) C in = x22uf/25v (ceramic 206) + X330uF (electrolytic, optional) C out =2x47uF/6.3V (ceramic 0805) 2//203

2 IRDC3899-PV8 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +2V input supply should be connected to VIN+ and VIN-. A maximum of 8.5A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I. IR3899 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc is required, then R5 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDOout pins should be shorted together for external Vcc operation. The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero ohm resistor for R2). The value of R4 and R28 can be selected to provide the desired tracking ratio between output voltage and the tracking input. Connection VIN+ VIN- Vout+ Vout- Vcc+ Vcc- Enable P_Good AGnd Table I. Connections Signal Name Vin (+2V) Ground of Vin Vout(+.8V) Ground for Vout Vcc/ LDO_out Pin Ground for Vcc input Enable Power Good Signal Analog ground LAYOUT The PCB is a 4-layer board (2.23 x2 ) using FR4 material. All layers use 2 Oz. copper. The PCB thickness is The IR3899 and other major power components are mounted on the top side of the board. Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3899. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 2//203 2

3 IRDC3899-PV8 Connection Diagram * Photos are from standard IR3899/98/97 evaluation boards. Vin Gnd Gnd Vout Enable VDDQ Vref Top View Sync S-Ctrl AGnd PGood Vsns Vcc+ Vcc- Bottom View Fig. : Connection Diagram of IR3899/98/97 Evaluation Boards 2//203 MC 3

4 IRDC3899-PV8 Fig. 2: Board Layout-Top Layer Single point connection between AGnd and PGnd Fig. 3: Board Layout-Bottom Layer 2//203 MC 4

5 IRDC3899-PV8 Fig. 4: Board Layout-Mid Layer Fig. 5: Board Layout-Mid Layer 2 2//203 MC 5

6 IRDC3899-PV8 VDDQ VREF Fig. 6: Schematic of the IR3899 evaluation board PGND L 0.4uH + C35 + C36 C4 0.uF R28 R9 7.5K VCC R29 C24 0.uF C26 5.6nF Vsns R4 0 ohm Vcc+ R.78k SYNC R9 9.K C2 00pF R8 49.9K R0 0 ohm S_Ctrl R50 0 ohm R3 0 ohm C23 2.2uF R7 N/A C25 R2.54k R4 5 ohm R2 R6 4.02k 20 ohm R3.54k C5 22uF C20 C9 C4 C8 C3 C7 C2 Vout C6 47uF C5 47uF VCC R5 C32.0uF 0 ohm U IR3899 VCC C8 2200pF A B C27 C 330uF/25V + 8 Vsns Enable Boot FB COMP Gnd PVin Vp 6 PGnd S_Ctrl 3 SW Vcc/LDO_OUT 5 Rt_Sync 7 PGood GND VREF Vin 2 9 Vcc- PGood C0 N/A R7 49.9K R2 C 20pF Enable C37 C7 0.uF N38703 C30 C29 C28 R 4.02k C6 N/A Vout+ (.8V) Vout- Agnd Vin+ (2V) Vin- 2//203 6

7 IRDC3899-PV8 Bill of Materials Item Qty Part Reference Value Description Manufacturer Part Number C* 330uF SMD Electrolytic F size 25V 20% Panasonic EEV-FKE33P 2 4 C5 22uF 206, 25V, X5R, 0% Murata GRM3CR6E226KE5L 3 4 C7 C2 C4 C24 0.uF 0603, 25V, X7R, 0% Murata GRM88R7E04KA0B 4 C8 2200pF 0603,50V,X7R Murata GRM88R7H222KA0B 5 C 20pF 0603, 50V, NP0, 5% TDK C608C0GH2J080AA 6 2 C5 C6 47uF 0805, 6.3V, X5R, 20% TDK C202X5R0J476M25AC 7 C23 2.2uF 0603, 6V, X5R, 20% TDK C608X5RC225M 8 C26 5.6nF 0603, 25V, NP0, 5% TDK C608C0GE562J080AA 9 C32.0uF 0603, 25V, X5R, 0% Murata GRM88R6E05KA2D 0 L 0.4uH SMD 4mm x 4mm x 2.mm, 7.55mΩ Coilcraft XAL ME R.78K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF78V 2 2 R2 R 4.02K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF402V 3 2 R3 R2.54K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF54V 4 R4 5 Thick Film, 0603,/0W,% Panasonic ERJ-3GEYJ50V 5 R6 20 Thick Film, 0603,/0W,% Panasonic ERJ-3EKF20R0V 6 R9 9.K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF9RV 7 5 R0 R3 R4 R5 R50 0 Thick Film, 0603,/0W Panasonic ERJ-3GEY0R00V 8 2 R7 R8 49.9K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF4992V 9 R9 7.5K Thick Film, 0603,/0W,% Panasonic ERJ-3EKF750V 20 U IR3899 PQFN 4x5mm IR IR3899MPBF * The electrolytic input capacitor is used to eliminate the impact of the parasitic inductance of the power supply cable. It may not be needed in real applications. 2//203 7

8 IRDC3899-PV8 TYPICAL OPERATING WAVEFORMS Vin=2.0V, Vo=.8V, Io=0-8.5A, Room Temperature, no airflow Fig. 7: Start up at 8.5A Load Ch :PV in, Ch 2 :En, Ch 3 :Vo, Ch 4 :PGood Fig. 8: Start up at 8.5A Load, Ch :PV in, Ch 2 :En, Ch 3 :Vo, Ch 4 :Vcc Fig. 9: Start up with.62v Pre Bias, 0A Load, Ch :SW, Ch 2 :En, Ch 3 :Vo, Ch 4 :PGood (PGood is tied to the internal smart LDO.) Fig. 0: Output Voltage Ripple, 8.5A load Ch 3 : V out, Fig. : Inductor node at 8.5A load Ch 3 :LX (with persistent on) Fig. 2: Short circuit (Hiccup) Recovery Ch 3 :V out, Ch 4 :Iout 2//203 8

9 IRDC3899-PV8 TYPICAL OPERATING WAVEFORMS Vin=2.0V, Vo=.8V, Io=0-8.5A, Room Temperature, no air flow Fig. 3: Transient Response, 4A to 8.5A step Ch 3 :V out Ch 4 -Iout Fig. 4: Bode Plot at 8.5A load shows a bandwidth of 94KHz, phase margin of 53 degree, and gain margin of -8dB. 2//203 9

10 IRDC3899-PV8 TYPICAL OPERATING WAVEFORMS Vin=2.0V, Vo=.8V, Io=0-8.5A, Room Temperature, no air flow Fig.7: Efficiency versus load current Fig.8: Power loss versus load current 2//203 0

11 IRDC3899-PV8 THERMAL IMAGES Vin=2.0V, Vo=0.8V, Io=0-8A, Room Temperature, No Air flow Fig. 9: Thermal Image of the board at 8.5A load Test point is IR3899 Test point 2 is inductor 2//203

12 IRDC3899-PV8 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to SupIRBuck Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note. (AN32) Figure 20: PCB Metal Pad Spacing (all dimensions in mm) 2//203 MC 2

13 IRDC3899-PV8 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.5mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 2: Solder resist 2//203 MC 3

14 IRDC3899-PV8 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of mm ( "). Stencils thinner than 0.00mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.25mm-0.200mm ( "), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.27mm (0.005").The reduction should be adjusted for stencils of other thicknesses. Figure 22: Stencil Pad Spacing (all dimensions in mm) 2//203 MC 4

15 IRDC3899-PV8 PACKAGE INFORMATION Figure 23: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) This product has been designed and qualified for the Industrial market Visit us at for sales contact information Data and specifications subject to change without notice. 06/ 2//203 MC 5