PRELIMINARY. CONTROL and Write LOGIC

Transcription

1 Features Zero Bus Latency, no dead cycles between Write and Read cycles Fast clock speed: 25, 2, and 67 MHz Fast access time: 2.4, 3. and 3.4 ns Internally synchronized registered outputs eliminate the need to control OE Single 3.3V 5% and +5% power supply V DD Separate for 3.3V or 2.5V Single WE (Read/Write) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear four-word burst capability Individual byte write (BWS a BWS h ) control (may be tied LOW) CEN pin to enable clock and suspend operations Three chip enables for simple depth expansion JTG boundary scan for BG packaging version vailable in 9-ball bump BG and -pin TQFP packages ( and ). 65-ball FBG and 29-ball BG () package are offered by opportunity basis. (Please contact Cypress sales or marketing) Functional Description The,, and SRMs are designed to eliminate dead cycles when making transitions from Read to Write or vice versa. These SRMs are optimized for % bus utilization and achieve Zero Bus Latency. They integrate 2,97,52 36/4,94,34 8/,48, SRM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. The Cypress Synchronous Burst SRM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, three-layer metal technology. Each memory cell consists of six transistors. ll synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion PRELIMINRY 2M x 36/4M x 8/M x 72 Pipelined SRM with NoBL rchitecture Chip Enables (CE, CE 2, and CE 3 ), cycle start input (DV/LD), Clock Enable (CEN), Byte Write Selects (BWS a, BWS b, BWS c, BWS d, BWS e, BWS f, BWS g, BWS h ), and Read/Write control (WE). BWS c and BWS d apply to and only. BWS e, BWS f, BWS g, and BWS h apply to only. ddress and control signals are applied to the SRM during one clock cycle, and two cycles later its associated data occurs, either Read or Write. Clock Enable (CEN) pin allows operation of the,, and to be suspended as long as necessary. ll synchronous inputs are ignored when (CEN) is HIGH; the internal device registers will hold their previous values. There are three Chip Enable (CE, CE 2, CE 3 ) pins that allow the user to deselect the device when desired. If any one of these three is not active when DV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in a high-impedance state two cycles after chip is deselected or a Write cycle is initiated. The,, and have an on-chip two-bit burst counter. In burst mode,,, and provide four cycles of data for a single address presented to the SRM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The DV/LD signal is used to load a new external address (DV/LD = LOW) or increment the internal burst counter (DV/LD = HIGH) Output Enable (OE) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTG test capabilities. The JTG circuitry is used to serially shift data to and from the device. JTG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. Logic Block Diagram CLK DV/LD CE D Data-In REG. Q x X DQ X DPX BWS X CEN X = 2: X=a,b,c,d X=a,b,c,d X=a,b,c,d 2M 36 CE CE 2 CE 3 4M 8 X = 2: X = a, b X = a, b X = a, b WE BWS x M 72 X = 9: X = a, b, X = a, b, X = a, b c,d,e,f,g,h c,d,e,f,g,h c,d,e,f,g,h Mode CONTROL and Write LOGIC 2M 36/ 4M 8/ M 72 MEMORY RRY OUTOUT REGISTERS and LOGIC DQ x DP x OE Cypress Semiconductor Corporation 39 North First Street San Jose, C Document #: Rev. * Revised January 24, 23

2 PRELIMINRY Selection Guide Unit Maximum ccess Time ns Maximum Operating Current TBD TBD TBD m Maximum CMOS Standby Current TBD TBD TBD m Pin Configurations CE CE 2 BWSd BWSc BWSb BWSa CE 3 V DD CLK WE CEN OE DV/LD -pin TQFP Packages CE CE 2 BWSb BWSa CE 3 V DD CLK WE CEN OE DPc V DD DPd DPb V DD ZZ DPa V DD DV/LD V DD 6 (2M 36) (4M 8) DPb DPa V DD ZZ V DD MODE MODE Document #: Rev. * Page 2 of 26

3 PRELIMINRY Pin Configurations (continued) B C D E F G H J K L M N P R T U B C D E F G H J K L M N P R T U 9-ball Bump BG (2M 36) 7 7 BG CE 2 DV/LD CE 3 V DD DQ c DP c DP b DQ b DQ c DQ c CE DQ b DQ b DQ c OE DQ b DQ c DQ c BWS c BWS b DQ b DQ b DQ c DQ c WE DQ b DQ b V DD V DD V DD DQ d DQ d CLK DQ a DQ a DQ d DQ d BWS d BWS a DQ a DQ a DQ d CEN DQ a DQ d DQ d DQ a DQ a DQ d DP d DP a DQ a MODE V DD ZZ TMS TDI TCK TDO (4M 8) 7 7 BG DQ b DQ b DQ b DQ b CE 2 DV/LD CE 3 V DD DP a DQ b CE DQ a OE DQ a DQ b BWS b DQ a WE DQ a V DD V DD V DD DQ b CLK DQ a BWS a DQ a DQ b CEN DQ a DP b DQ a MODE V DD ZZ TMS TDI TCK TDO Document #: Rev. * Page 3 of 26

4 PRELIMINRY Pin Configurations (continued) 65-ball Bump FBG (This package is offered by opportunity basis) (2M 36) 5 FBG B C D E F G H J K L M N P R DPc DPd MODE CE BWS c BWS b CE 3 CEN CE 2 BWS d BWS a CLK WE V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD TDI TDO TMS TCK 8 9 DV/LD OE 44M DPb V DD V DD V DD V DD V DD ZZ V DD V DD V DD V DD DPa (4M 8) 5 FBG B C D E F G H J K L M N P R DPb MODE CE BWS b CE 3 CEN CE 2 BWS a CLK WE V DD V DD V DD V DD V DD V DD V DD V DD V DD V DD TDI TDO TMS TCK 8 9 DV/LD OE 44M DPa V DD V DD V DD V DD V DD ZZ V DD V DD V DD V DD Document #: Rev. * Page 4 of 26

5 PRELIMINRY Pin Configurations (continued) 29-ball BG (This package is offered by opportunity basis) (M 72) B DQg DQg DQg DQg CE 2 DV/LD CE 3 BWS c BWS g WE BWS b BWS f C D E F G H J K L M N P R T U V W DQg DQg DPg DQh DQh DQh DQh DPd DQg DQg DPc DQh DQh DQh DQh DPh BWS h BWS d CLK CEN TMS TDI TDO TCK MODE BWS e BWS a V DD V DD V DD V DD V DD Q V DD V DD V DD V DD V DD CE OE V DD ZZ V DD V DD V DD DPf DQf DQf DQf DQf DPa DQe DQe DQe DQe DPb DQf DQf DQf DQf DPe DQe DQe DQe DQe Pin Definitions Pin Name I/O Type Pin Description BWS a BWS b BWS c BWS d BWS e BWS f BWS g BWS h WE DV/LD Input- Synchronous Input- Synchronous Input- Synchronous Input- Synchronous ddress Inputs used to select one of the 29752/49434/48576 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRM. Sampled on the rising edge of CLK. BWS a controls DQ a and DP a, BWS b controls DQ b and DP b, BWS c controls DQ c and DP c, BWS d controls DQ d and DP d. BWS e controls DQ e and DP e, BWS f controls DQ f and DP f, BWS g controls DQ g and DP g, and BWS h controls DQ h and DP h. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a Write sequence. dvance/load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW), the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. fter being deselected, DV/LD should be driven LOW in order to load a new address. Document #: Rev. * Page 5 of 26

6 PRELIMINRY Pin Definitions (continued) Pin Name I/O Type Pin Description CLK CE CE 2 CE 3 OE CEN DQ a DQ b DQ c DQ d DQ e DQ f DQ g DQ h DP a DP b DP c DP d DP e DP f DP g DP h ZZ Input- Clock Input- Synchronous Input- Synchronous Input- Synchronous Input- synchronous Input- Synchronous I/O- Synchronous I/O- Synchronous Input- synchronous Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 2 and CE 3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE and CE 3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE and CE 2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O Lines. s inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. s outputs, they deliver the data contained in the memory location specified by [x:] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a DQ d are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQ a, b, c, d, e, f, g, and h are eight bits wide Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ [x:]. DP a, b, c, d, e, f, g, and h are one bit wide. ZZ sleep Input. This active HIGH input places the device in a non-time critical sleep condition with data integrity preserved. MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. V DD Power Supply Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. Ground Ground for the device. Should be connected to ground of the system. TDO JTG serial output Serial data-out to the JTG circuit. Delivers data on the negative edge of TCK (BG only). Synchronous TDI JTG serial input Synchronous Serial data-in to the JTG circuit. Sampled on the rising edge of TCK (BG only). TMS TCK Test Mode Select Synchronous This pin controls the Test ccess Port state machine. Sampled on the rising edge of TCK (BG only). JTG serial clock Serial clock to the JTG circuit (BG only). 44M. This pin is reserved for expansion to 44 Mb. No connects. Document #: Rev. * Page 6 of 26

7 PRELIMINRY Introduction Functional Overview The // are synchronous-pipelined Burst NoBL SRMs designed specifically to eliminate wait states during Write/Read transitions. ll synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. ll synchronous operations are qualified with CEN. ll data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 2.6 ns (25-MHz device). ccesses can be initiated by asserting Chip Enable (CE, CE 2, CE 3 on the TQFP, CE on the BG) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and DV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BWS [h:a] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). ll writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Enable (CE, CE 2, CE 3 on TQFP, CE on BG) and an asynchronous Output Enable (OE) simplify depth expansion. ll operations (Reads, Writes, and Deselects) are pipelined. DV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read ccesses read access is initiated when the following conditions are satisfied at clock rise: () CEN is asserted LOW, (2) chip enable asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) DV/LD is asserted LOW. The address presented to the address inputs is latched into the ddress Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. t the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (25-MHz device) provided OE is active LOW. fter the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. Burst Read ccesses The // have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. DV/LD must be driven LOW in order to load a new address into the SRM, as described in the Single Read ccess section above. The sequence of the burst counter is determined by the MODE input signal. LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use and in the burst sequence, and will wraparound when incremented sufficiently. HIGH input on DV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write ccesses Write access are initiated when the following conditions are satisfied at clock rise: () CEN is asserted LOW, (2) CE, CE 2, and CE 3 are LL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to x is loaded into the ddress Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d,e,f,g,h /DP a,b,c,d,e,f,g,h for, DQ a,b,c,d / DP a,b,c,d for, and DQ a,b /DP a,b for ). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the ddress Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DP (DQ a,b,c,d,e,f,g,h /DP a,b,c,d,e,f,g,h for, DQ a,b,c,d / DP a,b,c,d for, and DQ a,b /DP a,b for ) (or a subset for byte write operations; see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BWS (BWS a,b,c,d,e,f,g,h for, BWS a,b,c,d for, and BWS a,b for ) signals. The // provides byte write capability that is described in the Write Cycle Description table. sserting the Write Enable input (WE) with the selected Byte Write Select (BWS) input will selectively write only to the desired bytes. Bytes not selected during a byte write operation will remain unaltered. Synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the // is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DP (DQ a,b,c,d,e,f,g,h /DP a,b,c,d,e,f,g,h for, DQ a,b,c,d /DP a,b,c,d for, and DQ a,b /DP a,b for ) inputs. Doing so will three-state the output drivers. s a safety precaution, DQ and DP (DQ a,b,c,d,e,f,g,h / DP a,b,c,d,e,f,g,h for, DQ a,b,c,d /DP a,b,c,d for, and DQ a,b /DP a,b for ) are automatically three-stated during the data portion of a Write cycle, regardless of the state of OE. Burst Write ccesses The // has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. DV/LD must be driven LOW in order to load the initial address, as described in the Single Write ccess section above. When DV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE, CE 2, and CE 3 ) and WE inputs are ignored and the burst counter is incremented. The correct BWS (BWS a,b,c,d,e,f,g,h for, BWS a,b,c,d for, and BWS a,b for ) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Document #: Rev. * Page 7 of 26

8 PRELIMINRY Cycle Description Truth Table [, 2, 3, 4, 5, 6] Operation ddress Used CE CEN DV/LD/ WE BWS x CLK Comments Deselected External X X L-H I/Os three-state following next recognized clock. Suspend X X X X L-H Clock ignored, all operations suspended. Begin Read External X L-H ddress latched. Begin Write External Valid L-H ddress latched, data presented two valid clocks later. Burst Read Operation Burst Write Operation Internal X X X L-H Burst Read operation. Previous access was a Read operation. ddresses incremented internally in conjunction with the state of Mode. Internal X X Valid L-H Burst Write operation. Previous access was a Write operation. ddresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS [h:a]. Interleaved Burst Sequence First ddress Second ddress Third ddress Fourth ddress [:] [:] [:] [:] Linear Burst Sequence First ddress Second ddress Third ddress Fourth ddress [:] [:] [:] [:] ZZ Mode Electrical Characteristics Sleep Mode The ZZ input pin is an asynchronous input. sserting ZZ places the SRM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. ccesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CEs must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. Parameter Description Test Conditions Min. Max. Unit I DDZZ Snooze mode standby current ZZ > V DD.2V 5 m t ZZS Device operation to ZZ ZZ > V DD.2V 2t CYC ns t ZZREC ZZ recovery time ZZ <.2V 2t CYC ns Write Cycle Descriptions [, 2] Function () WE BWS d BWS c BWS b BWS a Read X X X X Write No Bytes Written Write Byte (DQ a and DP a) Notes:. X = Don't Care, = Logic HIGH, = Logic LOW, CE stands for LL Chip Enables active. BWS x = signifies at least one Byte Write Select is active, BWS x = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details. 2. Write is defined by WE and BWS x. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN = inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: Rev. * Page 8 of 26

9 PRELIMINRY Write Cycle Descriptions (continued)[, 2] Function () WE BWS d BWS c BWS b BWS a Write Byte (DQ b and DP b) Write Bytes, Write Byte 2 (DQ c and DP c) Write Bytes 2, Write Bytes 2, Write Bytes 2,, Write Byte 3 (DQ d and DP d) Write Bytes 3, Write Bytes 3, Write Bytes 3,, Write Bytes 3, 2 Write Bytes 3, 2, Write Bytes 3, 2, Write ll Bytes Function () WE BWS b BWS a Read x x Write No Bytes Written Write Byte (DQ a and DP a) Write Byte (DQ b and DP b) Write Both Bytes Function () [7] WE BWS x Read x Write Byte X Write ll Bytes ll BWS = IEEE 49. Serial Boundary Scan (JTG) The // incorporates a serial boundary scan Test ccess Port (TP) in the BG package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 49.-9, but does not have the set of functions required for full 49. compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRM. Note that the TP controller functions in a manner that does not conflict with the operation of other devices using fully compliant 49. TPs. The TP operates using JEDEC standard 3.3V I/O logic levels. Disabling the JTG Feature It is possible to operate the SRM without using the JTG feature. To disable the TP controller, TCK must be tied LOW ( ) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test ccess Port Test Clock The test clock is used only with the TP controller. ll inputs are captured on the rising edge of TCK. ll outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Note: 7. BWSx represents any byte write signal BW[..7]. To enable any byte write BWSx, a low logic signal should be applied at clock rise. ny number of byte writes can be enabled at the same time for any given write. Document #: Rev. * Page 9 of 26

10 PRELIMINRY Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TP instruction register. For information on loading the instruction register, see the TP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TP state machine (see TP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TP Reset Reset is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This RESET does not affect the operation of the SRM and may be performed while the SRM is operating. t power-up, the TP is reset internally to ensure that TDO comes up in a High-Z state. TP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TP controller is in the CaptureIR state, the two least significant bits are loaded with a binary pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRM with minimal delay. The bypass register is set LOW ( ) when the BYPSS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRM. Several no connect () pins are also included in the scan register to reserve pins for higher density devices. The 36 configuration has a 7-bit-long register, and the 8 configuration has a 5-bit-long register. The boundary scan register is loaded with the contents of the RM Input and Output ring when the TP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SMPLE/PRELOD and SMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRM and can be shifted out when the TP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TP Instruction Set Eight different instructions are possible with the three-bit instruction register. ll combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TP controller used in this SRM is not fully compliant with the 49. convention because some of the mandatory 49. instructions are not fully implemented. The TP controller cannot be used to load address, data, or control signals into the SRM and cannot preload the Input or Output buffers. The SRM does not implement the 49. commands EXTEST or INTEST or the PRELOD portion of SMPLE/PRELOD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 49. instruction that is to be executed whenever the instruction register is loaded with all s. EXTEST is not implemented in the TP controller, and therefore this device is not compliant with the 49. standard. The TP controller does recognize an all- instruction. When an EXTEST instruction is loaded into the instruction register, the SRM responds as if a SMPLE/PRELOD instruction has been loaded. There is one difference between the two instructions. Unlike the SMPLE/PRELOD instruction, EXTEST places the SRM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TP controller is given a test logic reset state. Document #: Rev. * Page of 26

11 PRELIMINRY SMPLE Z The SMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TP controller is in a Shift-DR state. It also places all SRM outputs into a High-Z state. SMPLE/PRELOD SMPLE/PRELOD is a 49. mandatory instruction. The PRELOD portion of this instruction is not implemented, so the TP controller is not fully 49.-compliant. When the SMPLE/PRELOD instructions are loaded into the instruction register and the TP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TP controller clock can only operate at a frequency up to MHz, while the SRM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRM signal must be stabilized long enough to meet the TP controller s capture set-up plus hold times (t CS and t CH ). The SRM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SMPLE/PRELOD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOD part of the command is not implemented, putting the TP into the Update to the Update-DR state while performing a SMPLE/PRELOD instruction will have the same effect as the Pause-DR command. Bypass When the BYPSS instruction is loaded in the instruction register and the TP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPSS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: Rev. * Page of 26

12 PRELIMINRY TP Controller State Diagram [8] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCN SELECT IR-SCN CPTURE-DR CPTURE-DR SHIFT-DR SHIFT-IR EXIT-DR EXIT-IR PUSE-DR PUSE-IR EXIT2-DR EXIT2-IR UPDTE-DR UPDTE-IR Note: 8. The / next to each state represents the value at TMS at the rising edge of TCK. Document #: Rev. * Page 2 of 26

13 PRELIMINRY TP Controller Block Diagram Bypass Register TDI Selection Circuitry 2 Instruction Register Selection Circuitry TDO Identification Register Boundary Scan Register TCK TMS TP Controller TP Electrical Characteristics Over the Operating Range [9, ] Parameter Description Test Conditions Min. Max. Unit V OH Output HIGH Voltage I OH = 4. m 2.4 V V OH2 Output HIGH Voltage I OH = µ 3. V V OL Output LOW Voltage I OL = 8. m.4 V V OL2 Output LOW Voltage I OL = µ.2 V V IH Input HIGH Voltage.8 V DD +.3 V V IL Input LOW Voltage.5.8 V I X Input Load Current GND < V I < 5 5 µ [, 2] TP C Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit t TCYC TCK Clock Cycle Time ns t TF TCK Clock Frequency MHz t TH TCK Clock HIGH 4 ns t TL TCK Clock LOW 4 ns Set-up Times t TMSS TMS Set-up to TCK Clock Rise ns t TDIS TDI Set-up to TCK Clock Rise ns t CS Capture Set-up to TCK Rise ns Notes: 9. ll voltage referenced to Ground.. Overshoot: V IH (C) < V DD +.5V for t < t TCYC /2; undershoot: V IL (C) <.5V for t < t TCYC /2; power-up: V IH < 2.6V and V DD < 2.4V and <.4V for t < 2 ms.. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TP C test conditions. t R /t F = ns. Document #: Rev. * Page 3 of 26

14 PRELIMINRY TP C Switching Characteristics Over the Operating Range (continued)[, 2] Parameter Description Min. Max. Unit Hold Times t TMSH TMS Hold after TCK Clock Rise ns t TDIH TDI Hold after Clock Rise ns t CH Capture Hold after Clock Rise ns Output Times t TDOV TCK Clock LOW to TDO Valid 2 ns t TDOX TCK Clock LOW to TDO Invalid ns TP Timing and Test Conditions.25V TDO Z = 5Ω 5Ω C L = 2 pf V Vih LL INPUT PULSES (a) GND t TH t TL Test Clock TCK t TCYC t TMSS t TMSH Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO t TDOV ttdox Document #: Rev. * Page 4 of 26

15 PRELIMINRY Identification Register Definitions Instruction Field 8 36 X72 Description Revision Number (3:29) Reserved for version number Department Number (27:25) Department number Voltage (28&24) rchitecture (23:2) rchitecture type Memory type (2:8) Defines type of memory Device Width (7:5) Defines width of the SRM. 36 or 8 Device Density (4:2) Defines the density of the SRM Cypress JEDEC ID (:) llows unique identification of SRM vendor ID Register Presence () Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (x8) Bit Size (x36) Bit Size (x72) Instruction Bypass ID Boundary Scan TBD TBD TBD Identification Codes Instruction Code Description EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRM outputs to High-Z state. This instruction is not 49.-compliant. IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRM operation. SMPLE Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRM output drivers to a High-Z state. RESERVED Do Not Use. This instruction is reserved for future use. SMPLE/PRELOD Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRM operation. This instruction does not implement 49. preload function and is therefore not 49.-compliant. RESERVED Do Not Use. This instruction is reserved for future use. RESERVED Do Not Use. This instruction is reserved for future use. BYPSS Places the bypass register between TDI and TDO. This operation does not affect SRM operation. Document #: Rev. * Page 5 of 26

16 PRELIMINRY Boundary Scan Order (2M 36) Boundary Scan Order (4M 8) Document #: Rev. * Page 6 of 26

17 PRELIMINRY Maximum Ratings (bove which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +5 C mbient Temperature with Power pplied C to +25 C Supply Voltage on V DD Relative to GND....5V to +4.6V DC Voltage pplied to Outputs in High-Z State [4]....5V to +.5V DC Input Voltage [4]....5V to +.5V Current into Outputs (LOW)... 2 m Static Discharge Voltage... > 2V (per MIL-STD-883, Method 35) Latch-up Current... > 2 m Operating Range Range mbient Temperature [3] V DD Com l C to +7 C 3.3V ±5% 2.375V (min.) V DD (max) Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V DD Power Supply Voltage V I/O Supply Voltage V DD V V OH Output HIGH Voltage V DD = Min., I OH = 4. m 3.3V 2.4 V V DD = Min., I OH =. m 2.5V 2. V V OL Output LOW Voltage V DD = Min., I OL = 8. m 3.3V.4 V V DD = Min., I OL =. m 2.5V.4 V V IH Input HIGH Voltage 3.3 V 2. V 2.5V.7 V V IL Input LOW Voltage [4] 3.3V.3.8 V 2.5V.3.7 V I X Input Load Current GND < V I < 5 µ Input Current of MODE 3 µ Input Current of ZZ Input = 3 µ I OZ Output Leakage Current GND < V I <, Output Disabled 5 µ 25 MHz TBD m I DD V DD Operating Supply V DD = Max., I OUT = m, f = f MX = /t CYC 2 MHz TBD m 67 MHz TBD m I SB I SB2 I SB3 I SB4 utomatic CE Power-down Current TTL Inputs utomatic CE Power-down Current CMOS Inputs utomatic CE Power-down Current CMOS Inputs utomatic CE Power-down Current TTL Inputs Max. V DD, Device Deselected, V IN > V IH or V IN < V IL f = f MX = /t CYC Max. V DD, Device Deselected, V IN <.3V or V IN >.3V, f = Max. V DD, Device Deselected, or V IN <.3V or V IN >.3V f = f MX = /t CYC Max. V DD, Device Deselected, V IN > V IH or V IN < V IL, f = Shaded areas contain advance information. Notes: 3. T is the ambient temperature. 4. Minimum voltage equals 2.V for pulse durations of less than 2 ns. 25 MHz TBD m 2 MHz TBD m 67 MHz TBD m ll speed grades TBD m 25 MHz TBD m 2 MHz TBD m 67 MHz TBD m ll speed grades TBD m Document #: Rev. * Page 7 of 26

18 PRELIMINRY Capacitance [6] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T = 25 C, f = MHz, TBD pf C CLK Clock Input Capacitance V DD = = 3.3V TBD pf C I/O Input/Output Capacitance TBD pf C Test Loads and Waveforms OUTPUT Z = 5Ω (a) Thermal Resistance [6] R L = 5Ω R = 37Ω LL INPUT PULSES [5] OUTPUT V L =.5V for 3.3V =.25V for 2.5V 5pF ILUDING JIG ND SCOPE (b) % GND R = 35Ω Rise Time: 2 V/ns Parameter Description Test Conditions BG Typ. TQFP Typ. Units Q J Thermal Resistance Still ir, soldered on a inch, TBD TBD C/W (Junction to mbient) four-layer printed circuit board Q JC Thermal Resistance (Junction to Case) TBD TBD C/W Switching Characteristics (Over the Operating Range) Parameter Clock Description 3.3V 9% (c) Min. Max. Min. Max. Min. Max. 9% % Fall Time: 2 V/ns t CYC Clock Cycle Time ns F MX Maximum Operating Frequency MHz t CH Clock HIGH ns t CL Clock LOW ns Output Times t CO Data Output Valid fter CLK Rise ns t EOV OE LOW to Output Valid [6, 8, 2] ns t DOH Data Output Hold fter CLK Rise..3.5 ns t CHZ Clock to High-Z [6, 7, 8, 9, 2] ns t CLZ Clock to Low-Z [6, 7, 8, 9, 2]..3.5 ns t EOHZ OE HIGH to Output High-Z [7, 8, 2] ns t EOLZ OE LOW to Output Low-Z [7, 8, 2] ns Set-up Times t S ddress Set-up Before CLK Rise.5 ns t DS Data Input Set-up Before CLK Rise ns t CENS CEN Set-Up Before CLK Rise ns t WES WE, BWS x Set-up Before CLK Rise ns Notes: 5. Input waveform should have a slew rate of 2V/ns. 6. Tested initially and after any design or process change that may affect these parameters. 7. Unless otherwise noted, test conditions assume signal transition time of.5ns, timing reference levels of.5v, input pulse levels of to 3.3V, and output loading of the specified I OL /I OH and load capacitance. Shown in (a), (b) and (c) of C Test Loads. 8. t CHZ, t CLZ, t OEV, t EOLZ, and t EOHZ are specified with C test conditions shown in part (a) of C Test Loads. Transition is measured ± 2 mv from steady-state voltage. 9. t any given voltage and temperature, t EOHZ is less than t EOLZ and t CHZ is less than t CLZ to eliminate bus contention between SRMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 2. This parameter is sampled and not % tested. Unit Document #: Rev. * Page 8 of 26

19 PRELIMINRY Switching Characteristics (Over the Operating Range) (continued) Parameter Description Min. Max. Min. Max. Min. Max. Unit t LS DV/LD Set-up Before CLK Rise ns t CES Chip Select Set-up ns Hold Times t H ddress Hold fter CLK Rise ns t DH Data Input Hold fter CLK Rise ns t CENH CEN Hold fter CLK Rise ns t WEH WE, BW x Hold fter CLK Rise ns t LH DV/LD Hold after CLK Rise ns t CEH Chip Select Hold fter CLK Rise ns Shaded area contains advanced information. Switching Waveforms Read/Write/DESELECT Sequence Read Write Read DESELECT Read Write Read Read SUSPEND DESELECT DESELECT CLK CEN t CH t CL t CYC t CENS t CENH t S t H CEN HIGH blocks all synchronous inputs DDRESS R W2 R3 R4 W5 R6 R7 WE and BWS x t WS t WH t CES t CEH CE Data In/Out t DS t DH Q D2 Out In Q3 Out t CLZ t DOH t CHZ t DOH Q4 Out Device originally t CO deselected The combination of WE and BWS x (x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x8) defines a write cycle (see Write Cycle Description table). CE is the combination of CE, CE 2, and CE 3. ll chip enables need to be active in order to select the device. ny chip enable can deselect the device. Rx stands for Read ddress X, Wx stands for Write ddress X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. DV/LD held LOW. OE held LOW. = DON T CRE = UNDEFINED D5 In Q6 Out Q7 Out t CHZ Document #: Rev. * Page 9 of 26

20 PRELIMINRY Switching Waveforms (continued) Burst Sequences Begin Read Burst Read Burst Read Burst Read Begin Write Burst Write Burst Write Burst Write Begin Read Burst Read Burst Read CLK t LS t LH t CH t CL t CYC DV/LD t S t H DDRESS R W2 R3 WE t WS t WH t WS t WH BWS x t CES t CEH CE Data In/Out t CLZ Device originally deselected t CO t DOH Q Out t CO Q+ Out Q+2 Out The combination of WE and BWS x (x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x8) define a write cycle (see Write Cycle Description table). CE is the combination of CE, CE 2, and CE 3. ll chip enables need to be active in order to select the device. ny chip enable can deselect the device. Rx stands for Read ddress X, W stands for Write ddress X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS x input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. Q+3 Out t CHZ t DS D2 In = DON T CRE = UNDEFINED t DH D2+ In D2+2 In t CLZ D2+3 In Q3 Out Document #: Rev. * Page 2 of 26

21 PRELIMINRY Switching Waveforms (continued) OE Timing OE t EOHZ t EOV I/Os Three-state t EOLZ Ordering Information Speed (MHz) Ordering Code 25-25C -25C -25BGC -25BGC -25BZC -25BZC Package Operating Name Package Type Range -lead mm Thin Quad Flat Pack Commercial BG9 BB65C 9-ball BG ( mm) 65-ball FBG (5 7 mm) -25BGC BG29 29-ball BG ( mm) 2-2C -2C -2BGC -2BGC -2BZC -2BZC BG9 BB65C -lead mm Thin Quad Flat Pack 9-ball BG ( mm) 65-ball FBG (5 7 mm) -2BGC BG29 29-ball BG ( mm) 67-67C -67C -67BGC -67BGC -67BZC -67BZC BG9 BB65C -lead mm Thin Quad Flat Pack 9-ball BG ( mm) 65-ball FBG (5 7 mm) -67BGC BG29 29-ball BG ( mm) Shaded area contains advanced information. Document #: Rev. * Page 2 of 26

22 PRELIMINRY Package Diagrams -pin Thin Plastic Quad Flatpack (4 x 2 x.4 mm) Document #: Rev. * Page 22 of 26

23 PRELIMINRY Package Diagrams (continued) 65-ball FBG (5 7.2 mm) BB65C ** Document #: Rev. * Page 23 of 26

24 PRELIMINRY Package Diagrams (continued) 9-Lead PBG (4 x 22 x 2.4 mm) BG *B Document #: Rev. * Page 24 of 26

25 PRELIMINRY Package Diagrams (continued) 29-Lead PBG (4 x 22 x 2.2 mm) BG *B Zero Bus Latency, No Bus Latency, and NoBL are trademarks of Cypress Semiconductor Corporation. ll product and company names mentioned in this document are the trademarks of their respective holders. Document #: Rev. * Page 25 of 26 Cypress Semiconductor Corporation, 23. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

26 PRELIMINRY Document History Page Document Title: // 2M x 36/4M x 8/M x 72 Pipelined SRM with NoBL rchitecture Document Number: REV. ECN NO. ISSUE DTE ORIG. OF CHNGE DESCRIPTION OF CHNGE ** /6/2 PKS New Data Sheet * 252 /27/3 CJM Updated features for package offering Removed 3MHz offering Changed tco, teov, tchz, teohz from 2.4 ns to 2.6 ns (25 MHz), tdoh, tclz from.8 ns to. ns (25 MHz), tdoh, tclz from. ns to.3 ns (2 MHz) Updated ordering information Changed dvanced Information to Preliminary Document #: Rev. * Page 26 of 26