12-Mbit (512 K 24) Static RAM

Transcription

1 12-Mbit (512 K 24) Static RAM Features High speed t AA = 10 ns Low active power I CC = 175 ma at 10 ns Low CMOS standby power I SB2 = 25 ma Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Available in Pb-free standard 119-ball PBGA Functional Description The is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE 1, CE 2, and CE 3 ). CE 1 controls the data on the I/O 0 I/O 7, while CE 2 controls the data on I/O 8 I/O 15, and CE 3 controls the data on the data pins I/O 16 I/O 23. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input and output (I/O) pins is then written into the location specified on the address pins (A 0 A 18 ). Asserting all of the chip selects LOW and write enable LOW writes all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes are also individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH, while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins appear on the specified data input and output (I/O) pins. Asserting all the chip selects LOW reads all 24 bits of data from the SRAM. The 24 I/O pins (I/O 0 I/O 23 ) are placed in a high impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For more information, see the Truth Table on page 8. Logic Block Diagram INPUT BUFFER A (9:0) ROW DECODER 512K x 24 ARRAY SENSE AMPS I/O 0 I/O 7 I/O 8 I/O 15 I/O 16 I/O 23 COLUMN DECODER CONTROL LOGIC CE 1, CE 2, CE 3 WE OE A (18:10) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *E Revised December 8, 2010

2 Selection Guide Description 10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 ma Maximum CMOS Standby Current 25 ma Pin Configuration Figure Ball PBGA (Top View) [1] A NC A A A A A NC B NC A A CE 1 A A NC C I/O 12 NC CE 2 NC CE 3 NC I/O 0 D I/O 13 V DD V SS V SS V SS V DD I/O 1 E I/O 14 V SS V DD V SS V DD V SS I/O 2 F I/O 15 V DD V SS V SS V SS V DD I/O 3 G I/O 16 V SS V DD V SS V DD V SS I/O 4 H I/O 17 V DD V SS V SS V SS V DD I/O 5 J NC V SS V DD V SS V DD V SS NC K I/O 18 V DD V SS V SS V SS V DD I/O 6 L I/O 19 V SS V DD V SS V DD V SS I/O 7 M I/O 20 V DD V SS V SS V SS V DD I/O 8 N I/O 21 V SS V DD V SS V DD V SS I/O 9 P I/O 22 V DD V SS V SS V SS V DD I/O 10 R I/O 23 A NC NC NC A I/O 11 T NC A A WE A A NC U NC A A OE A A NC Note 1. NC pins are not connected on the die. Document Number: Rev. *E Page 2 of 12

3 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage on V CC Relative to GND [2] V to +4.6V DC Voltage Applied to Outputs in High-Z State [2] V to V CC + 0.5V DC Input Voltage [2] V to V CC + 0.5V Current into Outputs (LOW) ma Static Discharge Voltage......>2001V (MIL-STD-883, Method 3015) Latch Up Current... >200 ma Operating Range Range Ambient Temperature V CC Industrial 40 C to +85 C 3.3V 0.3V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [3] 10 Min Max Unit V OH Output HIGH Voltage V CC = Min, I OH = 4.0 ma 2.4 V V OL Output LOW Voltage V CC = Min, I OL = 8.0 ma 0.4 V V IH Input HIGH Voltage 2.0 V CC V [2] V IL Input LOW Voltage V I IX Input Leakage Current GND < V I < V CC 1 +1 A I OZ Output Leakage Current GND < V OUT < V CC, output disabled 1 +1 A I CC V CC Operating Supply Current V CC = Max, f = f MAX = 1/t RC I OUT = 0 ma CMOS levels 175 ma I SB1 I SB2 Automatic CE Power Down Current TTL Inputs Automatic CE Power Down Current CMOS Inputs Max V CC, CE > V IH 30 ma V IN > V IH or V IN < V IL, f = f MAX Max V CC, CE > V CC 0.3V, V IN > V CC 0.3V, or V IN < 0.3V, f = 0 25 ma Notes 2. V IL (min) = 2.0V and V IH (max) = V CC + 2V for pulse durations of less than 20 ns. 3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE 1 or CE 2, or CE 3 is LOW. When HIGH, CE indicates the CE 1, CE 2, and CE 3 are HIGH. Document Number: Rev. *E Page 3 of 12

4 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, V CC = 3.3V 8 pf C OUT I/O Capacitance 10 pf Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions JA JC Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Still air, soldered on a inch, four layer printed circuit board 119-Ball PBGA Unit C/W 8.35 C/W Figure 2. AC Test Loads and Waveforms [4] OUTPUT Z0= 50 (a) *Capacitive Load consists of all components of the test environment pf* V TH = 1.5V 3.3V OUTPUT 5 pf* *Including jig and scope R1 317 (b) R V GND Rise Time > 1V/ns All input pulses 90% 10% (c) 90% 10% Fall Time:> 1V/ns Note 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V DD (3.0V). 100 s (t power ) after reaching the minimum operating V DD, normal SRAM operation begins including reduction in V DD to the data retention (V CCDR, 2.0V) voltage. Document Number: Rev. *E Page 4 of 12

5 AC Switching Characteristics Over the Operating Range [5] Parameter Description 10 Min Max Unit Read Cycle [6] t power V CC (Typical) to the First Access 100 s t RC Read Cycle Time 10 ns t AA Address to Data Valid 10 ns t OHA Data Hold from Address Change 3 ns t ACE CE Active LOW to Data Valid [3] 10 ns t DOE OE LOW to Data Valid 5 ns t LZOE OE LOW to Low Z [7] 1 ns t HZOE OE HIGH to High Z [7] 5 ns t LZCE CE Active LOW to Low Z [3, 7] 3 ns t HZCE CE Deselect HIGH to High Z [3, 7] 5 ns t PU CE Active LOW to Power Up [3, 8] 0 ns t PD CE Deselect HIGH to Power Down [3, 8] 10 ns [9, 10] Write Cycle t WC Write Cycle Time 10 ns t SCE CE Active LOW to Write End [3] 7 ns t AW Address Setup to Write End 7 ns t HA Address Hold from Write End 0 ns t SA Address Setup to Write Start 0 ns t PWE WE Pulse Width 7 ns t SD Data Setup to Write End 5.5 ns t HD Data Hold from Write End 0 ns t LZWE WE HIGH to Low Z [7] 3 ns t HZWE WE LOW to High Z [7] 5 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of Figure 2, unless specified otherwise. 6. t POWER gives the minimum amount of time that the power supply is at typical V CC values until the first memory access is performed. 7. t HZOE, t HZCE, t HZWE, t LZOE, t LZCE, and t LZWE are specified with a load capacitance of 5 pf as in part (b) of Figure 2. Transition is measured 200 mv from steady state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE 1 or CE 2 or CE 3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD. Document Number: Rev. *E Page 5 of 12

6 Data Retention Characteristics Over the Operating Range Parameter Description Conditions [3] Min Typ Max Unit V DR V CC for Data Retention 2 V I CCDR Data Retention Current V CC = 2V, CE > V CC 0.2V, 25 ma V IN > V CC 0.2V or V IN < 0.2V t [11] CDR Chip Deselect to Data Retention 0 ns Time [12] t R Operation Recovery Time t RC ns Data Retention Waveform V CC 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R CE Switching Waveforms [13, 14] Figure 3. Read Cycle No. 1 trc ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID [3, 14, 15] Figure 4. Read Cycle No. 2 (OE Controlled) DATA VALID ADDRESS CE t RC OE t ACE DATA OUT t DOE t LZOE HIGH IMPEDANCE DATA VALID t HZOE t HZCE HIGH IMPEDANCE V CC SUPPLY CURRENT t LZCE t PU 50% t PD 50% I CC I SB Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear V CC ramp from V DR to V CC(min) > 50 s or stable at V CC(min) > 50 s. 13. Device is continuously selected. OE, CE = V IL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. Document Number: Rev. *E Page 6 of 12

7 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17] ADDRESS t WC CE t SCE t SA t AW t SCE t HA WE t PWE t SD t HD DATA I/O DATA VALID [3, 16, 17] Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS CE t SCE t AW t HA WE t SA t PWE OE DATA I/O NOTE 18 t HZOE t SD DATAIN VALID t HD [3, 17] Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t AW t HA t SA t PWE WE t SD t HD DATA I/O NOTE 18 DATA VALID t HZWE t LZWE Notes 16. Data I/O is high impedance if OE = V IH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period, the I/Os are in output state. Do not apply input signals. Document Number: Rev. *E Page 7 of 12

8 Truth Table CE 1 CE 2 CE 3 OE WE I/O 0 I/O 7 I/O 8 I/O 15 I/O 16 I/O 23 Mode Power H H H X X High Z High Z High Z Power Down Standby (I SB ) L H H L H Data Out High Z High Z Read Active (I CC ) H L H L H High Z Data Out High Z Read Active (I CC ) H H L L H High Z High Z Data Out Read Active (I CC ) L L L L H Full Data Out Full Data Out Full Data Out Read Active (I CC ) L H H X L Data In High Z High Z Write Active (I CC ) H L H X L High Z Data In High Z Write Active (I CC ) H H L X L High Z High Z Data In Write Active (I CC ) L L L X L Full Data In Full Data In Full Data In Write Active (I CC ) L L L H H High Z High Z High Z Selected, Outputs Disabled Active (I CC ) Document Number: Rev. *E Page 8 of 12

9 Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 10-10BGXI ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Industrial Ordering Code Definitions CY 7 C D V33-10 BGX I Temperature Range: I = Industrial Package Type: BGX = 119-ball PBGA (Pb-free) Speed: 10 ns Voltage range: V33 = 3 V to 3.6 V D = C9, 90 nm Technology 012 = 12-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: Rev. *E Page 9 of 12

10 Package Diagram Figure ball PBGA ( mm) *C Document Number: Rev. *E Page 10 of 12

11 Document History Page Document Title: 12-Mbit (512 K 24) Static RAM Document Number: Rev. ECN No. Orig. of Change Submission Date Description of Change ** SYT See ECN New data sheet *A NXR See ECN Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed 10 and 12 speed bins from product offering Changed J7 Ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed I CC(Max) from 220 ma to 150 ma Changed I SB1(Max) from 70 ma to 30 ma Changed I SB2(Max) from 40 ma to 25 ma Specified the Overshoot specification in footnote 1 Updated the Truth Table Updated the Ordering Information table *B NXR See ECN Added note 1 for NC pins Changed I CC specification from 150 ma to 185 ma Updated Test Condition for I CC in DC Electrical Characteristics table Added note for t ACE, t LZCE, t HZCE, t PU, t PD, and t SCE in AC Switching Characteristics Table on page 4 *C VKN See ECN Converted from preliminary to final Updated block diagram Changed I CC specification from 185 ma to 225 ma Updated thermal specs *D VKN/PYRS 11/12/08 Removed Commercial operating range, Added Industrial operating range Removed 8 ns speed bin, Added 10 ns speed bin, Modified footnote# 3 *E AJU 12/08/2010 Added Ordering Code Definitions. Updated Package Diagram. Document Number: Rev. *E Page 11 of 12

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