ELEC 4601: Laboratory 1 Introduction to Microprocessors

Transcription

1 Department of Electronics ELEC 4601: Laboratory 1 Introduction to Microprocessors Record of Changes REV By Description Issue Date 4.1 MR Reformatting Aug 25, TP Changed trigger terms to table, added more detail for inserting trigger level, added note in part 2 procedure Sep 12, NM Update to Agilent 16702B Logic Analyzer Sep 10, DG Reformatting Sep 12, 2016 Carleton University, Ottawa, Ontario K1S 5B6, Canada

2 Introduction This lab will introduce various concepts related to microprocessors: How to test and debug simple code for a given microprocessor, in this case an AM386SX-40 (one of the early variations of the classic 80x86 processor) The idea of addressing and communicating with devices that are electrically connected to the address/data/control buses of the microprocessor using memory-mapped or I/O mapped operations How to operate a logic analyzer that lets you capture and evaluate these microprocessor bus signals The idea that the execution of code, even a single instruction, results in the generation of electrical signals that you can use as inputs to your own digital circuitry in order to cause something to happen Please note that there is additional support information and software available to you from the course website that you should carefully review before attempting this lab Hardware The following hardware is used in this lab: HP 16702B Logic Analyzer AM386SX-40 based single board computer (PC/104 SBC) The single board computer (SBC) uses a PC/104 industrial interface bus (a derivative of the classic ISA bus) as a peripheral device bus and the DOS operating system. Microsoft DOS has network functionality to allow you to network to a more sophisticated Windows based network for file transfer and, more importantly, it allows you to have direct access to all the hardware attached to the SBC without having to work with setting up access permission from the operating system. This is pretty much a standard embedded microprocessor development setup Logic analyzer Logic analyzers are used to capture and store the states of a large number of time related signals and then examine the relationship of these signals to each other. They are pretty much like digital cameras for digital signals with a variable flash rate (sampling rate) and a fixed memory card size (finite memory) that can be commanded to take a series of snapshots when certain conditions occur (trigger conditions); e.g. you can trigger a capture of all signals when two of the signals have a particular logical state, or when a particular hexadecimal value appears on the address or data bus. Note that if you take a lot of very fast snapshots you are limited by memory to a small time window that you can look at. If you take slow snapshots, you have a bigger time window for examination but you may miss fast changing signals PC/104 PC/104 is an industrial standard that defines how the bus signals from a microprocessor are brought out to particular pins of a particular connector having a very well defined size and shape. If you follow this standard, you can create boards and devices that will connect to any micro-computer that follows the standard. For the purposes of this lab, you need only consider it as a convenient way to bring the signals from the microprocessor out to place where the logic analyzer can connect to them Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 1

3 Part 1: Setting up the Logic Analyzer PRELAB In this lab you will have to label and assign pins to the logic analyzer. It is important to save time by already knowing which pins you will need to assign, and what pod they should be on (see Table 1 on Page 4). You should also be aware of what the TRIGGER is/does on the logic analyzer Figure 1: System Configuration Procedure 1) Click on the Select icon in the 167XXA: Analyzer<A> box. Note that the last A of this title may also be a D/E/something-else and just reflects the location of the interface board plugged into the back of the logic analyzer. Select the Setup and Trigger option, usually at the top of the dropdown list a) Under the Sampling tab: Ensure that the Type of the Analyzer is set to Timing b) Under Format: Select Pod Assignment, move all of the Pods 1-3 under Analyzer 1. If two analyzers are being used select the Pods as needed. If you look at the back of the PC104, you will see 3 pods which connect to the Logic Analyzer At this point, your Pod Assignment setup should appear as shown in Figure 2 Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 2

4 Figure 2: Analyzer Configuration 2) Select the Close to return to the Format option. This Format window is used to select the pods and pins to be used, and how they are labeled. Please refer to Table 1 for the appropriate pin assignments a) Setting up the Pods and Pins: i. Familiarize yourself with what s on the screen of the logic analyzer. You will notice labels running down the left of the screen (see Figure 3) ii. Click on the first label in the list (usually Label1 or something similar) and select Rename. Rename it to SDATA iii. Use your cursor to scroll through Pods 1 3, and the Clock Inputs (horizontal scroll located at the bottom right of your screen). The pods shown correspond to the ones selected in the Pod Assignment view. Note that, depending on the location of the logic analyzer module, the first letter of the Pod name might also be D or E or just something other than A b) Rename the labels for SDATA and SADDR lines that need to be used, as well as SYSCLK, MEMR, and MEMW, and the rest of the bus lines (as shown in Table 1) c) Assigning the pins to the labels i. In the Format view, under each Pod, is a listing of These correspond to the pins of each Pod ii. For example, looking at Table 1, you will see that for Pod 1, all pins (0 through 15) are assigned to SDATA. An asterisk * denotes that this pin is assigned to the label iii. Along SDATA, click on the corresponding Pod 1 segment, and you can set all of the pins to *. In the popup window, selecting **************** will set all the pins to be assigned iv. Do this for all of the other bus lines, and have a TA verify this Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 3

5 Table 1: Logic Analyzer POD connections to Processor Buses Channel Number [Pin # ] POD 3 POD 2 POD 1 Pin Name MISC Pin Name ADDR Pin Name DATA GND GND GND GND 0 SA16 SA0 SD0 1 SA17 SA1 SD1 2 SA18 SA2 SD2 3 SA19 SA3 SD3 4 IRQ4 SA4 SD4 5 IRQ5 SA5 SD5 6 IRQ3 SA6 SD6 7 IRQ7 SA7 SD7 8 MEMR SA8 SD8 9 MEMW SA9 SD9 10 BALE SA10 SD10 11 REFRESH SA11 SD11 12 AEN SA12 SD12 13 OSC SA13 SD13 14 SYSCLK SA14 SD SA15 SD15 CLK INPUT J IOR CLK INPUT K IOW Note : clock inputs are at the end of the scrollable list of PODS Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 4

6 Figure 3: Format Layout (example only) Note the following about Figure 3: In the Pod labels ( Pod A3, Pod A2, etc) the number is the important part. The actual alphabetic character may be different from that shown since the character code relates to the location of the logic analyzer module itself The signal group labels (which can refer to a single signal on a single pod or a cluster of signals across several pods) are shown in the leftmost column as labels The array of touchable buttons with the dots (. ) and asterisks ( * ) is used to assign one or more pins of the selected POD to a particular label At this point, you have defined the electrical connections. Signals of interest on the microprocessor bus are connected to actual inputs on the logic analyzer Since the logic analyzer doesn t have infinite memory, you have to very precisely define when exactly you want to take a snapshot of the signals that you are interested in. This process involves setting up the logical conditions that trigger the first snapshot. Snapshots will then be taken at a speed that you define until memory is full. The trick is to define the speed of the snapshots so that snapshots occur fast enough to see what you want over a fixed period of time too fast and you may not see how the signals are related, too slow and you may not see the fast signals that you are interested in Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 5

7 For the demonstration that follows we are going to generate and capture some memory mapped I/O cycles (the 80x86 is capable of both memory-mapped I/O and port-mapped I/O) i.e. reads and writes of the video memory used to produce the text display that you are seeing on the monitor attached to the PC/104 computer 3) Select the Trigger tab To debug embedded systems, it is necessary to monitor the real time behavior of the data signals passing through the bus. The logic analyzer captures the data both prior to and following the triggered trace point Figure 4: Trigger Layout (example only) The most commonly used trigger signals are the bus data WRITE and READ signals since conversations between the microprocessor and the peripheral device always involve these signals. So a simple trigger can be set up as shown in the following steps: a) Set the state(s) you are looking for in each signal. In this example, the MEMW and MEMR have states where they go to 1 and 0 (zero), respectively. That is, we have set both a (for the MEMW signal) and b (for the MEMR signal) to X indicating that we don t care about the state of these signals for the moment b) Insert a trigger level. There are a number of macros you can use, or you can make your own. For simplicity we can use 2 built-in trigger macros. Under General Timing we set a trigger to find "a" for > 6ns, and then trigger (capture a waveform) on b. You can add more trigger levels by clicking Insert Before/After c) After then, you have the options to finish the Trigger and fill the memory, or Goto the next trigger condition Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 6

8 Example: Triggering at Hello : Setting the TRIGGER: format of (signal column, pattern row) e.g. (SDATA column, a row) 1 Set (SDATA, a) to XX48, (SADDR) to B8XXX {H} 2 Set (SDATA, b) to XX65, (SADDR) to B8XXX {e} 3 Set (SDATA, c) to XX6C, (SADDR) to B8XXX {l} 4 Set (SDATA, d) to XX6C, (SADDR) to B8XXX {l} 5 (Optional) You can also set MEMW to 1 for states a-d Timing Sequence Levels: 1 Find a > 8ns 2 Find b > 8ns 3 Find c > 8ns 4 TRIGGER on d > 8ns Click the RUN icon, and then execute the LAB1A.EXE program from the DOS prompt To view the waveform, select Window followed by Analyzer<A>, Waveform<1> The waveform window should appear similar to the screen shown in the figure below Figure 5: Waveform Display You can save the screen shown on the logic analyzer to a JPEG file on your desktop. Launch the Chrome web browser. Enter the IP of the Agilent 16702B LA, located at the top of the unit, in the search bar. Select Get Image. Save the image to you H: drive (never save to your desktop! Ever!) Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 7

9 Figure 7: Screen Capture Questions 1. How long does one complete memory-mapped I/O cycle to video memory take? 2. What is the frequency of the reference SYSCLK? 3. Explain clearly the reason for the values shown on the captured display for the signals that you are looking at, specifically SMEMR, SMEMW, SDATA and SADDR Note: In order to answer these questions, you must include screenshots of your waveforms with timing markers indicating the beginning and ending of your measurements BONUS diversion a. Run your trigger on the logic analyzer b. Type in CLS in DOS, and run your executable c. Click on Acq. Control and set it to Manual. Set the Sample time to 256ns d. Find the time between each of the characters displayed e. Set Acq. Control back to 8ns. Hit enter repeatedly till you reach the last line of the screen, and trigger and run your executable again f. Find the time between the characters H, E, L, L, and O g. So what s up (it is related to the graphical display and how it synchronizes output to an old fashioned CRT monitor. A search for topics related to IBM-PC displays, CGA and snow will help) Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 8

10 Part 2: Investigating Port-mapped I/O The other technique used to talk with peripheral devices on the 80x86 buses is referred to as port-mapped I/O. This involves talking to a device using only IN and OUT opcode instructions (there are actually a few more such as INS and OUTS, but they operate in basically the same way). Memory-mapped I/O can use any instruction that involves memory operations (there are lots), port-mapped I/O is restricted to a smaller and less powerful instruction set Memory mapped I/O uses the full 20-bit address space of the processor and produces SMEMR and SMEMW strobe signals. Port mapped I/O uses a smaller 16-bit address space and produces IOR and IOW strobe signals For this demonstration, we are going to use the DOS Debug command to create a simple program to flash some LEDs that are attached to the output pins of what is referred to as the printer or parallel port (at input/output port at address 0x0378) Procedure 1) From the PC/104 computer, run the DEBUG utility. From the DEBUG prompt type: o to set the state of the LEDs to 0x55 o 378 AA i 378 to set the state of the LEDs to 0xAA to read back the state of the LEDs 2) For each of the examples above, capture the following so that their relationship is shown in time (note: you will have to alter the trigger levels/terms from what they were in Part 1, in order to capture these events): the data bus, address bus, and the IOR, IOW, SYSCLK signals 3) Use the logic analyzer to measure the time that it takes to produce one complete I/O cycle; hint, use the markers Capture the 3 timing diagrams for your report If you do o X and o X378 AA, where X is any hex digit between 0 and F, you should see exactly the same thing each time. This tells you something about how the parallel port on this PC is addressed, which would be what exactly? You can also do this in code, using the simple DEBUG assembler and instruction trace features: a 100 mov dx,378 in al,dx 4) Set the logic analyzer to trigger on an IO Read (an active low signal) to address X0378 Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 9

11 5) Trace the little program above and note exactly when the logic analyzer triggers 6) Compare this to the results of the i 378 instruction above a 100 mov dx,378 mov al,55 out dx,al 7) Set the logic analyzer to trigger on an IO Write (an active low signal) to address X0378 8) Trace the little program above and note exactly when the logic analyzer triggers 9) Compare this to the results of the o test above Capture the 2 timing diagrams for your report Questions 1. Discuss your observations on how the parallel port on the PC is addressed 2. Report your observations when the logic analyzer triggers and compare results from steps six and nine Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 10

12 Part 3 Investigating Video Memory The CGA text mode video memory starts at B800:0000 (20-bit address of 0xB80000). This memory holds all the text characters that you see on monitor attached to the PC/104 computer Address B800:0000 references the character (one byte) in the upper left corner of the screen. Each line on the display is 80 characters wide. There are 25 lines in the display. Each character is coded with one word one byte of the word is the actual ASCII character code and the other byte of the code is the attribute byte indicating the foreground and background colors of the character. This gives you a memory block which is 80*2*25 or 4,000 bytes in size Procedure 1) Using DEBUG and some simple assembly code, you now have a relatively easy way to access any character on the screen: a 100 mov ax,b800 mov es,ax mov di,0 mov ax,4235 es: mov [di+640],ax 2) Now run this little program: -r ip :100 3) Press t multiple times to step through the program until you get to the last instruction. To run the program again you will have to reset the instruction pointer (IP) back to 100 Questions 1. Describe the little change that you see on the screen. Explain it (this requires some thinking) 2. Explain and comment the above lines of code BONUS With this basic code you can now change any character on the screen and its attributes. Figure out how to change the color of every character on the screen so that it is WHITE on BLUE instead of LIGHTGREY on BLACK, regardless of what the character itself is Write-up and Deliverables Please follow the questions in the Marking Rubric given on culearn Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 11

13 Appendix A: Assembling and linking the part 1 executable Introduction From prior courses, you should already have acquired knowledge of how to use debug and how to assemble assembly language source. It would be very useful if you reviewed assembly level programming on the 80x86 as well as your common DOS commands. Below is a sample program that you can practice and run at home, as well as in the lab session Procedure 1. Download tools.zip from the culearn website 2. Extract all the files from tools.zip into a directory (i.e., H:\BUILD). The files are a subset of the freely available Microsoft MASM assembler that as a minimum you need to assemble and build code 3. Create a text file and save it as LAB1A.ASM. Note that, by default, the Notepad application will save your file with a.txt extension. Please make sure to change your save type 4. Copy the code below and paste it into your file 5. On the PC/104 computer, assemble the program by typing at the DOS prompt: ml LAB1A.asm 6. It produces LAB1A.EXE. 7. To test run it at the DOS prompt, type: LAB1A or LAB1A.EXE 8. You may need to type cls to clear the screen, as the message is written at the top of the screen s memory ; *********** lab1a.asm ************* ; Displays the string (including the spaces) ; at various locations about the screen ; Note: ; - Code uses MASM 6.11 syntax ; - To assemble: ml lab1a.asm ; ***********************************.MODEL small.stack 100h.386.data msg DB "Hello World, Welcome to ELEC4601!!!", 0 nsize DW ($ - msg).code _main PROC XOR SI, SI XOR DI, DI MOV MOV DS, DX MOV CX, nsize MOV SI, OFFSET msg MOV DX, 0B800h MOV ES, DX scanloop: MOV AL, byte ptr [SI] MOV byte ptr ES: [DI], AL INC DI INC SI INC DI LOOP scanloop terminate: MOV AX, 4C00h INT 21h _main ENDP END _main Carleton University, Ottawa, Ontario K1S 5B6, Canada Page 12