Laboratory 1 Introduction to Microprocessors

Transcription

1 Department of Electronics Laboratory 1 Introduction to Microprocessors Record of Changes REV By Description Issue Date 4.1 MR Reformatting Aug 25, TP Changed trigger terms to table, added more detail for inserting trigger level, added note in part 2 procedure 4.3 TP some references changed to Table 1, changed the labels needed, added info on using scroll wheel when assigning pins Sep 12, 2013 Sep 17, 2013

2 Introduction This lab will introduce various concepts related to microprocessors: How to test and debug simple code for a given microprocessor, in this case an AM386SX-40 (one of the early variations of the classic 80x86 processor. The idea of addressing and communicating with devices that are electrically connected to the address/data/control buses of the microprocessor using memory-mapped or I/O mapped operations How to operate a logic analyzer, that lets you capture and evaluate these microprocessor bus signals The idea that the execution of code, even a single instruction, results in the generation of electrical signals that you can use as inputs to your own digital circuitry in order to cause something to happen Please note that there is additional support information and software available to you from the course website that you should carefully review before attempting this lab. Hardware HP 16500B/C Logic Analyzer AM386SX-40 based single board computer (PC/104 SBC) The single board computer (SBC) uses a PC/104 industrial interface bus (a derivative of the classic ISA bus) as a peripheral device bus and the DOS operating system. Microsoft DOS has network functionality to allow you to network to a more sophisticated Windows based network for file transfer and, more importantly, it allows you to have direct access to all the hardware attached to the SBC without having to work with setting up access permission from the operating system. This is pretty much a standard embedded microprocessor development setup. Logic analyzer Logic analyzers are used to capture and store the states of a large number of time related signals and then examine the relationship of these signals to each other. They are pretty much like digital cameras for digital signals with a variable flash rate (sampling rate) and a fixed memory card size (finite memory) that can be commanded to take a series of snapshots when certain conditions occur (trigger conditions); e.g. you can trigger a capture of all signals when two of the signals have a particular logical state, or when a particular hexadecimal value appears on the address or data bus. Note that if you take a lot of very fast snapshots you are limited by memory to a small time window that you can look at. If you take slow snapshots, you have a bigger time window for examination but you may miss fast changing signals.

3 PC/104 PC/104 is an industrial standard that defines how the bus signals from a microprocessor are brought out to particular pins of a particular connector having a very well defined size and shape. If you follow this standard, you can create boards and devices that will connect to any micro-computer that follows the standard. For the purposes of this lab, you need only consider it as a convenient way to bring the signals from the microprocessor out to place where the logic analyzer can connect to them. Part 1: Setting up the Logic Analyzer PRELAB In this lab you will have to label and assign pins to the logic analyzer. It is important to save time by already knowing which pins you will need to assign, and what pod they should be on (refer to Table 1). You should also be aware of what the TRIGGER is/does on both the logic analyzer and oscilloscope. Procedure Figure 1 HP16500B System Configuration screen 1. Before we start, we are going to need an executable program that will write data to memory and to the screen to give the logic analyzer to trigger on. The executable program should be on CULearn. If it isn t, go to Appendix A; it gives instructions on how to create it. Once you have a working program, leave it on in a convenient place on your H: networked drive so that the PC/104 computer can see it. 2. Click on the top left System icon, and select the 100/500MHz LA A option from the dropdown list.

4 Note that the last A of this title may also be a D/E/something-else and just reflects the version number of the interface board plugged into the back of the logic analyzer. 3. Select the button to the right of the 100/500MHz LA A and 4. Choose the Configuration option, usually at the top of the dropdown list. 5. Move all of the Pods 1-3 under Analyzer 1 by pressing on the Pod icon, and selecting MACHINE 1 from the list (in Figure 2 below its ISA_TM; you can edit the name). If two analyzers are being used select the Pods as needed. If you look at the back of the PC/104 SBC, you will see 3 pods which connect to the Logic Analyzer. 6. Ensure that the Type of the Analyzer is set to Timing At this point, your setup should appear similar as shown in Figure 2 below: Figure 2 Analyzer POD Configuration 7. Select the Configuration button and, 8. From the dropdown list, select the Format option. This Format window is used to select the pods and pins to be used, and how they are labeled. Please refer to Table 1 for the appropriate pin assignments.

5 Figure 3 Formatting pod connections screen Setting up the PODs and Pins Familiarize yourself with what s on the screen of the logic analyzer. You will notice labels running down the left of the screen (see Figure 3 above). 1. Press the first label in the list (usually Lab1 or something similar) and 2. Select Modify Label. 3. Rename it to SDATA. Press Labels and you can scroll using the dial on the right of the screen to scroll through up to 126 labels (which can be renamed to individual/grouped bus lines) 4. Press on Pods, and 5. Use your cursor wheel to scroll through PODs 1-3, and the Clock Inputs. The pods shown correspond to the ones selected in the Configuration view. Note, depending on your version of the logic analyzer, the first letter of the POD name might also be D or E or just something other than A (i.e. E1, E2). 6. Rename the labels to accommodate the SDATA and SADDR lines that need to be used, as well as SYSCLK, MEMR, MEMW, IOR, and IOW (as shown in Table 1). The other bus lines will be used in another lab. Quick hint, we can group signal lines to labels. If you look at Table 1 below, you ll note that POD 1 has data lines SDO to SD15, we can assign the data line to one label and it will appear as a BUS. The same goes for the IRQ4 to 7 lines, the MEMR and MEMW lines, and the SA0 to SA19 line; we can create labels and group pins to them for convenience.

6 Assigning the pins to the labels In the Format view, under each Pod, in blue is a listing of These correspond to the pins of each Pod. For example, looking at Table 1, you will see that for Pod 1, all pins (0 through 15) are assigned to SDATA. An asterisk * denotes that this pin is assigned to the label. 1. Along the SDATA row, press on the corresponding Pod 1 segment; pop-up edit dialog appears in blue with a row of asterisks. You can set all of the pins to *. In the pop-up window, repeatedly selecting CLEAR will toggle all the pins between assigned and unassigned. You can use the scroll wheel on the front of the machine to move the cursor to a specific pin. 2. For all of your other labels, make the correct pin assignments (according to Table 1); have a TA verify this.

7 Table 1 : Logic Analyser POD connections to Processor Buses Channel Number [Pin #] POD 3 POD 2 POD 1 Clock Inputs Pin Name Pin Name Pin Name Pin Name MISC ADDR DATA GND GND GND GND 0 SA16 SA0 SD0 1 SA17 SA1 SD1 2 SA18 SA2 SD2 3 SA19 SA3 SD3 4 IRQ4 SA4 SD4 5 IRQ5 SA5 SD5 6 IRQ3 SA6 SD6 7 IRQ7 SA7 SD7 8 MEMR SA8 SD8 9 MEMW SA9 SD9 10 BALE SA10 SD10 11 REFRESH SA11 SD11 12 AEN SA12 SD12 13 OSC SA13 SD13 14 SYSCLK SA14 SD SA15 SD15 J IOR K IOW L - M - N - P - Note : Clock Inputs are at the end of the scrollable list of PODS

8 Figure 4 Format Layout (example only) Note the following about Figure 4: - If the control is coloured blue, you can likely touch it on the screen and change its properties - In the Pod labels ( Pod A3, Pod A2 etc.) the number is the important part. The actual alphabetic character may be different from that shown since the character code relates to the version of the logic analyzer itself - The signal group labels (which can refer to a single signal on a single pod or a cluster of signals across several pods) are shown in the leftmost column - The array of blue touchable buttons with the dots (. ) and asterisks ( * ) is used to assign one or more pins of the selected POD to a particular label At this point you have defined the electrical connections. Signals of interest on the microprocessor bus are connected to actual inputs on the logic analyzer. Setting up Triggers Since the logic analyzer doesn t have infinite memory, you have to very precisely define when exactly you want to take a snapshot of the signals that you are interested in. This process involves setting up the logical conditions that trigger the first snapshot. Snapshots will then be taken at a speed that you define until memory is full. The trick is to define the speed of the snapshots so that snapshots occur fast enough to see what you want over a fixed period of time too fast and you may not see how the signals are related, too slow and you may not see the fast signals that you are interested in. To debug embedded systems, it is necessary to monitor the real

9 time behavior of the data signals passing through the bus. The logic analyzer captures the data both prior to and following the triggered trace point. The most commonly used trigger signals are the bus data WRITE and READ signals since conversations between the microprocessor and the peripheral device always involve these signals. For this demonstration, we are going to generate and capture some memory mapped I/O cycles (the 80x86 is capable of both memory-mapped I/O and port-mapped I/O); i.e. reads and writes of the video memory used to produce the text display that you are seeing on the monitor attached to the PC/104 computer. To generate the reads and writes to video memory, we are going to run a program (see Appendix A: Assembling and linking the part 1 executable) LAB1A.EXE that will write Hello World, Welcome to ELEC4601!!! to the screen of the PC/104 computer. You will set up the logic analyzer trigger to start acquiring data when Hell (you re in fourth year right?) appears in order on the data bus. Setting up the trigger can be performed in the following steps: 1. Press the Format icon and move to the Trigger menu. Figure 5 Trigger Layout (EXAMPLE ONLY) 2. Set the state(s) you are looking for in each signal. Look at Figure 5 above and note the Terms; we are interested in: a, b, c, and d. The Label and Terms form a matrix of conditions that the trigger uses to take a snap shot; for example: a = SDATA AND SADDR AND IRQ3_7 AND IRQ9_C. If you want it to ignore the label for a specific condition, press on the value and select CLEAR. It will change the value to all X s.

10 What we have so far to do is set up the terms as shown in the following table: Triggering at Hello : Terms SDATA SADDR Note: a XX48 B8XXX triggering on H b XX65 B8XXX e c XX6C B8XXX l d XX6C B8XXX l 3. Insert trigger levels. There are a number of macros you can use, or you can make your own. For simplicity, we can use two built-in trigger macros. We set a trigger to find "a" for 8ns, and then trigger (capture a waveform) on b. You can add more trigger levels by pressing Modify Trigger, then choose Add sequence level, from the list choose Basic Macro 2. Find pattern present/absent for > duration. Make sure to use the present condition, not absent. In the end you should have 4 sequence levels as follows: Timing Sequence Levels: 1 Find a present for > 8ns 2 Find b present for > 8ns 3 Find c present for > 8ns 4 TRIGGER on d present for > 8ns 4. Click the RUN icon, and then execute the LAB1A.EXE program from the DOS prompt on the PC/104 computer. The waveform window should appear similar to the screen shown in the figure below: Figure 6 Waveform Display

11 5. You can save the screen shown on the logic analyzer using either of the following, however the floppy disk is the preferred method as X window crashes some times: the X Windows support available on the logic analyzer (see Appendix B: Setting up the X- Windows connection), and then using the Windows Snipping Tool program to capture the image. Writing your verified waveform to a floppy disk (Do this by selecting PRINT Print Disk. Set the Output Disk to Flexible disk. MAKE SURE TO CHANGE THE FILE NAME EACH TIME, OR YOU WILL OVERWRITE YOUR PREVIOUS IMAGE) 6. You need to save the configuration that you have entered for the next lab, look at the procedure detailed in Appendix C: Saving/Retrieving Configuration. Question How long does one complete memory-mapped I/O cycle to video memory take (ask the TA if you re not sure of the definition of a data cycle)? What is the frequency of the reference SYSCLK? Explain clearly the reason for the values shown on the captured display for the signals that you are looking at, specifically MEMR, MEMW, SDATA and SADDR. BONUS a. Run your trigger on the logic analyzer. b. Type in CLS in DOS, and run your executable. c. Click on Acq. Control and set it to Manual. Set the Sample time to 256ns. d. Find the time between each of the characters displayed e. Set Acq. Control back to 8ns. Hit enter repeatedly till you reach the last line of the screen, and trigger and run your executable again. f. Find the time between the characters H, E, L, L, and O. g. So what s up (it is related to the graphical display and how it synchronizes output to an old fashioned CRT monitor. A search for topics related to IBM-PC displays, CGA and snow will help ) Part 2: Investigating Port-mapped I/O The other technique used to talk with peripheral devices on the 80x86 buses is referred to as port-mapped I/O. This involves talking to a device using only IN and OUT opcode instructions (there are actually a few more such as INS and OUTS, but they operate in basically the same way). Memory-mapped I/O can use any instruction that involves memory operations (there are lots), port-mapped I/O is restricted to a smaller and less powerful instruction set. Memory mapped I/O uses the full 20-bit address space of the processor and produces MEMR and MEMW strobe signals. Port mapped I/O uses a smaller 16-bit address space and produces IOR and IOW strobe signals.

12 For this demonstration, we are going to use the DOS Debug command to create a simple program to flash some LEDs that are attached to the output pins of what is referred to as the printer or parallel port (at input/output port at address 0x0378). Procedure 1. From the PC/104 computer run the DEBUG utility, from the DEBUG prompt type: o to set the state of the LEDs to 0x55 o 378 AA to set the state of the LEDs to 0xAA i 378 to read back the state of the LEDs 2. For each of the examples above, set up the logic analyzer to trigger on these events (note: you will have to alter the trigger levels / terms from what they were in part 1) and capture the waveform screen so that the following are shown in time: the data bus, address bus, and the IOR, IOW, SYSCLK signals 3. Use the logic analyzer to measure the time that it takes to produce one complete I/O cycle; hint, use the markers. Question Capture the timing diagrams for your report. If you do o X and o X378 AA, where X is any hex digit between 0 and F, you should see exactly the same thing each time. What does this tell you about the addressing of the parallel port on this PC? You can also do this in code, using the simple DEBUG assembler and instruction trace features. Start entering assembly code at address 100 by typing in the following: a 100 mov dx,378 in al,dx After the last line, hit enter until you are back at the debug prompt (a dash, - ), then enter t=100 to start tracing the program at address 100, then enter a single t every time after that to trace the next line. 4. Set the logic analyzer to trigger on an IO Read (an active low signal) to address X Put the logic analyzer in run mode, trace the little program above, and note exactly when the logic analyzer triggers.

13 6. Compare this to the results of the i 378 instruction above. Now enter the following: a 100 mov dx,378 mov al,55 out dx,al 7. Set the logic analyzer to trigger on an IO Write (an active low signal) to address X Trace the little program above and note exactly when the logic analyzer triggers. 9. Compare this to the results of the o test above Question Discuss your observations on how the parallel port on the PC is addressed. Report your observations when the logic analyser triggers and compare results from steps six and nine. Part 3 Investigating Video Memory The CGA text mode video memory starts at B800:0000 (20-bit address of 0xB80000). This memory holds all the text characters that you see on monitor attached to the PC/104 computer. Address B800:0000 references the character (one byte) in the upper left corner of the screen. Each line on the display is 80 characters wide. There are 25 lines in the display. Each character is coded with one word one byte of the word is the actual ASCII character code and the other byte of the code is the attribute byte indicating the foreground and background colours of the character. This gives you a memory block which is 80*2*25 or 4,000 bytes in size. Procedure 1. Using DEBUG and some simple assembly code, you now have a relatively easy way to access any character on the screen: a 100 mov ax,b800 mov es,ax mov di,0 mov ax,4235 es: mov [di+640],ax 2. Now start tracing this little program from the beginning: -t=100

14 3. Press t multiple times to step through the program until you get to the last instruction. To run the program again you will have to reset the instruction pointer (IP) back to 100. Question Describe the little change that you see on the screen. Explain it (this requires some thinking). Explain and comment the above lines of code. BONUS With this basic code you can now change any character on the screen and its attributes. Figure out how to change the colour of every character on the screen so that it is WHITE on BLUE instead of LIGHTGREY on BLACK, regardless of what the character itself is. Write-up and Deliverables Where code has been requested, provide a well commented listing and a description of what you see when the code executes Please submit pictures of all waveforms and describe what you see on each and why they appear as they do. Answer any questions asked throughout the lab documentation.

15 Appendix A: Assembling and linking the part 1 executable Introduction From prior courses, you should already have acquired knowledge of how to use debug and how to assemble assembly language source. It would be very useful if you reviewed assembly level programming on the 80x86 as well as your common DOS commands. Below is a sample program that you can practice and run at home, as well as in the lab session. Procedure 1. Download tools.zip from the CULearn website. 2. Extract all the files from tools.zip (from website) into a directory (i.e. H:\BUILD). The files are a subset of the freely available Microsoft MASM assembler that as a minimum you need to assemble and build code. 3. Create a text file and save it as LAB1A.ASM 4. Copy the code below and paste it into a file LAB1A.ASM 5. On the PC/104 computer assemble the program by typing at the DOS prompt: ml LAB1A.asm 6. It produces LAB1A.EXE. 7. To test run it at the DOS prompt; you should see a friendly message at the top of the screen. ;*********** lab1a.asm ************* ; Displays the string (including the spaces) ; at various locations about the screen ; Note: ; - Code uses MASM 6.11 syntax ; - To assemble: ml lab1a.asm ;***********************************.MODEL small.stack 100h.386.data msg DB "Hello World, Welcome to ELEC4601!!!", 0 nsize DW ($ - msg).code _main PROC XOR SI, SI XOR DI, DI MOV MOV DS, DX MOV CX, nsize MOV SI, OFFSET msg MOV DX, 0B800h MOV ES, DX scanloop: MOV AL, byte ptr [SI] MOV byte ptr ES: [DI], AL INC DI INC SI INC DI LOOP scanloop terminate: MOV AX, 4C00h INT 21h _main ENDP END _main

16 Appendix B: Setting up the X-Windows connection Introduction There will be portions of the laboratory demonstration that you will be required to record a timing diagram or configuration screen. The logic analyzer is able to transmit its screen remotely onto a PC screen using X- Windows. How X-Window works is beyond the scope of this demonstration; if you require knowing more, Google it. Establishing a connection Figure 7 Exceed Icon from the Windows desk top Click on the Exceed icon (see above) on the Windows desktop to start the X-Windows Server or open from the Windows menu: Start>>Programs>>Open Text Exceed 14>> Exceed The following window appears: Figure 8 Display manager chooser (don t worry about all the other information in the dialog, we only need Passive mode) It does not matter which host name you use, we are not going to use that information. Click the Passive button from the Display Manager Chooser (see figure 2 above). If it hasn t been done already, turn the Logic Analyzer system is on and boot and wait for it to boot.

17 Currently, in the lab we have two models of Logic Analyzers; the procedures to connect are similar, but the initial configuration screens are different. For the model HP 16500B Logic Analyzer On first boot, the initial configuration screen will appear, touch the Communications button to access the X- Windows interface. Figure 9 HP16500B Main Configuration screen In the communications configuration screen, touch the X Window button to access the X Windows Connect/Disconnect button. Figure 10 HP16500B Communications Configuration Screen

18 Press the Connect button in the X Window Configuration screen, on the PC, a window will appear displaying the same graphic that you see on the Logic Analyzer. Figure 11 HP16500B X-Windows Configuration Screen (Note it is connected to the host PC) For the model HP 16500C Logic Analyzer Press the Connect button on the screen. The display will now be mirrored on the PC where you have started the X-Server. Figure 12 HP 16500C Logic analyzer display (now connected to the Windows PC)

19 When you are done, DO NOT KILL the window (click on the X in the title) mirroring the logic analyzer display; otherwise, you will have to reboot the logic analyzer. Press Disconnect to gracefully close down the server. Appendix C: Saving/Retrieving Configuration Introduction There is no guarantee that your configuration will survive or exist from one lab session to the next. You are going to have to save your configuration onto the 3.5 floppy and transfer it onto the H: network drive via the station lab PC. Procedure Saving your configuration 1. Insert the 3.5 disk supplied by the laboratory technologist into the disk drive of the HP logic analyzer. 2. From the Configuration screen displayed when the logic analyzer first boots up, press the Configuration button; a drop down menu appears. 3. Press the Flexible Disk menu item; a Flexible Disk activity screen appears. Figure 13 Configuration option menu

20 Figure 14 Flexible disk access page 4. Click on the Load button below the System button. A menu list drops down showing more actions. Figure 15 Flexible disk option menu 5. Select Store from the menu list that appears; you re here to store your configuration. Figure 16 Disk action dialog detail 6. Click on the button adjacent to the to file: label ; a text entry interface appears.

21 7. Enter a meaningful name to keep track of your configuration. You can do the same for the file description if you want, this is optional. Figure 17 Disk action file name 8. Click Execute and then Continue to store your configuration. Figure 18 Finished storing the config 9. Remove the 3.5 floppy from the Logic Analyzer and insert it into the Workstation PC. 10. Open Windows Explorer and Click on the Computer icon in the Left hand list; observe the Devices with Removable Storage area, 11. Double Click on the Floppy Disk Drive (A:) item; a new explorer window appears with the items. 12. Create a new directory on your network (H:) drive and copy the files with the name you supplied to the directory for safe storage.

22 Figure 19 Explorer Window Retrieving your configuration 1. The assumption here is that you have already saved your configuration that you have developed previously and need to retrieve it to continue your work. 2. Insert the 3.5 floppy into the Workstation PC computer. 3. Open a Windows explorer window on the workstation and go to the directory on the H: drive that you had previously save the configuration. 4. Copy the configuration files to the 3.5 floppy 5. Start up the Logic Analyzer, once it has finally booted, 6. Insert the 3.5 floppy into the floppy drive of the Logic Analyzer 7. As above, from the startup Configuration screen, select Configuration from the drop down list menu, 8. Select Flexible Disk, the Flexible Disk activity screen appears. 9. Select the Load 10. Press on the All button, a menu appears:

23 Figure 20 Configuration options 11. Select the 100/500MHz LA X E option (note, that the E may be different from machine to machine) 12. Press Execute to retrieve the configuration from disk, the disk LED is on when busy. 13. On completion, the disk LED will be off.