INSTITUTO DE PLASMAS E FUSÃO NUCLEAR

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1 ATCA-PTSW-AMC4 Technical Manual INSTITUTO DE PLASMAS E FUSÃO NUCLEAR October 29, 2013 Authored by: M. Correia

2 ATCA-PTSW-AMC4 Technical Manual Document Configuration COMPANY AUTHORS IPFN/IST- instituto de Plasmas e Fusão Nuclear Instituto Superior Técnico Av. Rovisco Pais, Lisbon Portugal M. Correia (miguelfc@ipfn.ist.utl.pt) VERSION 1.4 IDENTIFIER ATCA-PTSW-AMC4 LAST UPDATE NUMBER OF PAGES 17 (Including Cover) Historic DATE VERSION DESCRIPTION AUTHOR 2011/10/ Initial Version MiguelFC 2011/10/ Revised J. Sousa 2011/12/ Revised MiguelFC 2012/01/ New board title MiguelFC 2013/10/ Revised MiguelFC 2

3 Index DOCUMENT CONFIGURATION DESCRIPTION BOARD CONNECTIVITY ATCA FABRIC INTERFACE (ZONE 2) TIMING AND SYNCHRONIZATION INTERFACE RTM ZONE 3A INTERFACE AMC SLOTS PCI EXPRESS SWITCHING PEX UPSTREAM PORT SELECTION PORT STATE CLOCK DISTRIBUTION CROSS-POINT SWITCH TIMING SIGNALS PCIE REFERENCE CLOCK MHZ CLOCK AND IRIG-B REAR TRANSITION MODULE RTM ZONE 3A INTERFACE PCIEX16 HOST CONNECTOR PCIEX16 RE-DRIVERS CONNECTORS RMC-TMG-1588 EXTERNAL TIMING MODULE

4 Index of figures Figure 1. ATCA-PTSW-AMC4 connectivity block diagram Figure 2 ATCA-PTSW-AMC4_RTM Rear Transition Module block diagram and panel Figure 3 PCIe re-drivers and configuration resistors Figure 4 RMC-TMG-1588 add-on for ATCA-PTSW-AMC4_RTM with IEEE sync Index of tables Table 1. ATCA Fabric interface PCIe channels on Zone Table 2. ATCA Timing and Synchronization interface connector pinout Table 3. Zone 3A data connectors (J31/RP31, J32/RP32, J33/RP33) pinout Table 4. Zone 3A Power/nanagement connectors (J30/RP30) pinout Table 5. AMC slot clock and data port pinout Table 6. PEX port list Table 7. Upstream port selection Table 8. PEX port state LED behaviour table Table 9. CPS Timing signals correspondence Table 6. Equalization Configuration Pins for the re-drivers ports. Default values are shaded blue Table 7. De-Emphasis Configuration Pins for the re-driver ports. Default values are shaded blue Table 8. Other Configuration Pins for the re-drivers

5 1 Description The ATCA-PTSW-AMC4 board is a cutaway quad-amc carrier module, compliant with the ATCA (PICMG 3.0) specification. The board has the following main features: PCI Express Gen 2 switching (PLX Tech. PEX ), connecting: 13 fabric channels (thirteen 4 links), PICMG 3.4 R AMC modules (four 4 links), PICMG AMC.1 R2.0. RTM module (one 16 link), PCI Express External Cabling R1.0. Onboard FPGA (one 4 link). Crosspoint-switch for clock distribution Implemented on a Virtex-6 FPGA. Distributes clocking and synchronization signals to/from compliant AMC/RTM inserted modules. Distribution to other compliant ATCA blades within the shelf is assured via the ATCA clock and synchronization interface. Rear Transmission Module connectivity PICMG 3.8 compliant ( Zone 3A ). PCI Express over-cable ipass connector (16 link). 4 (four) connectors (4 link) to the FPGA s MGT transceivers. 1 (one) connector (1 link) to AMC1 slot Ethernet port. 1 External Timing module (RMC-TMG-1588), featuring IEEE over Ethernet sync to an external Grand Master Clock. MISC CoreIPM OPMA2368 IPM Controller Serial EEPROM for PEX configuration 5

6 AMC1 slot GbE ( 1 link) TCLKA/B/C/D, FCLKA PCIe (4 link) SATA (1 link) ATCA-PTSW-AMC4 (Front Board) ATCA Zone 3A (PICMG 3.8) J30/RP30 J31/RP31 J32/RP32 J33/RP33 ATCA-PTSW-AMC4_RTM ( 1 link) ( 1 link) ( 1 link) ( 1 link) SATA (1 link) AMC2 slot TCLKA/B/C/D, FCLKA PCIe (4 link) MGT (4 link) FPGA PCIe (4 link) ATCA Clock and Sync Interface TCLKA/B/C/D, FCLKA PCIe (4 link) J20 CLK1A/B CLK2A/B CLK3A/B PCIe (16 link) External Cable REFCLK (FCLKA) AMC3 slot SATA (1 link) SATA (1 link) PEX ATCA Zone 2 13 Fabric Channels (4 links) GbE (1 link) RMC-TMG-1588 External timing module TCLKA/B/C/D, FCLKA PCIe (4 link) J20 J21 J22 J23 TCLKA TCLKB TCLKC TCLKD GbE LEMO (4 ) AMC4 slot USB Link type: clock PCIe (GbE) (optical/gbe) SATA FIGURE 1. ATCA-PTSW-AMC4 CONNECTIVITY BLOCK DIAGRAM. 6

7 2 Board connectivity 2.1 ATCA Fabric Interface (Zone 2) The ATCA-PTSW-AMC4, inserted on any of the hub slots of the ATCA shelf, establishes a PCIe star network on the Fabric Interface (Zone 2). ATCA backplane Fabric Channels (1-13) connect to the PEX switch. Table 1 denotes the location of each fabric channel on the ATCA Zone 2 connectors (J20, J21, J22 and J23). TABLE 1. ATCA FABRIC INTERFACE PCIE CHANNELS ON ZONE 2. Con. Rows Zone 2 Fabric Channel Link type J20 10/9 fabric channel 13 PCIe 4 J21 2/1 fabric channel 12 PCIe 4 J21 4/3 fabric channel 11 PCIe 4 J21 6/5 fabric channel 10 PCIe 4 J21 8/7 fabric channel 9 PCIe 4 J21 10/9 fabric channel 8 PCIe 4 J22 2/1 fabric channel 7 PCIe 4 J22 4/3 fabric channel 6 PCIe 4 J22 6/5 fabric channel 5 PCIe 4 J22 8/7 fabric channel 4 PCIe 4 J22 10/9 fabric channel 3 PCIe 4 J23 2/1 fabric channel 2 PCIe 4 J23 4/3 fabric channel 1 PCIe Timing and Synchronization Interface ATCA Timing and Synchronization interface clocks are located on the upper rows of connector J20 (Table 2). TABLE 2. ATCA TIMING AND SYNCHRONIZATION INTERFACE CONNECTOR PINOUT. Con. Pin Name Pin J20 Reserved B2 J20 ATCA_CLK1A+ A1 J20 Reserved C2 J20 ATCA_CLK1A- B1 J20 ATCA_CLK1B+ C1 J20 ATCA_CLK1B- D1 J20 ATCA_CLK2A+ E1 J20 ATCA_CLK2A- F1 J20 ATCA_CLK2B+ G1 J20 ATCA_CLK2B- H1 J20 Reserved A2 J20 Reserved D2 J20 ATCA_CLK3A+ E2 J20 ATCA_CLK3A- F2 J20 ATCA_CLK3B+ G2 J20 ATCA_CLK3B- H2 7

8 2.3 RTM Zone 3A Interface ZONE 3A INTERFACE CONNECTS T O THE ATCA-PTSW-AMC4 REAR TRANSITION MODULE (ATCA-PTSW- AMC4_RTM). PICMG 3.8 DEFINES POWER/MANAGEMENT CONNECTORS J30 (FRONT BOARD) AND RP30 (RTM MATING), AND DATA CONNECTORS J31, J32, J33 (FRONT BOARD) AND RP31, RP32, RP33 (RTM MATING). THE PINOUT FOR THE DATA CONNECTORS IS SHOWN IN TABLE 3, CONTAINING THE FOUR FPGA MGT TRANSCEIVER LINKS (AND RESPECTIVE SIDEBAND SIGNALS) WHICH LINK TO THE RTM TRANSCEIVERS, THE 16 PCIE EXTERNAL CABLE LINK (AND RESPECTIVE SIDEBAND SIGNALS), ONE GBE LINK TO AMC1 SLOT AND THE FIVE RTM CLOCKS, DEFINED IN ANALOGY WITH THE AMC STANDARD. THE POWER/MANAGEMENT CONNECTOR PINOUT IS SHOWN ON Table 4. TABLE 3. ZONE 3A DATA CONNECTORS (J31/RP31, J32/RP32, J33/RP33) PINOUT. Con. Pin Name Pin # J32 Port 0 TX DISABLE D9 J33 GbE Rx- B9 J32 Port 0 Rx F7,E7 J32 Port 0 Tx H7,G7 J32 Port 1 Rx B7,A7 J32 Port 1 Tx D7,C7 J32 Port 2 Rx F8,E8 J32 Port 2 Tx H8,G8 J32 Port 3 Rx B8,A8 J32 Port 3 Tx D8,C8 J32 dprsnt# F9 J32 dwake# E9 J32 dpwron H9 J32 Reserved G9 J32 GbE TX DISABLE B9 J32 GbE LOS A9 J32 Port 0 LOS C9 J32 Port 1 TX DISABLE H10 J32 Port 1 LOS G10 J32 Port 2 TX DISABLE B10 J32 Port 2 LOS A10 J32 Port 3 TX DISABLE D10 J32 Port 3 LOS C10 J33 PCIe (lane 11-8) Row 3/4 J33 PCIe (lane 7-4) Row 5/6 J33 PCIe (lane 3-0) Row 7/8 J33 (n/c) E9 J33 dperst# F9 J33 GbE Rx+ A9 J33 GbE Tx- D9 J33 GbE Tx+ C9 J33 RTM_FCLKA- H9 J33 RTM_FCLKA+ G9 J33 RTM_TCLKD- B10 J33 RTM_TCLKD+ A10 J33 RTM_TCLKC- D10 J33 RTM_TCLKC+ C10 J33 RTM_TCLKB- F10 J33 RTM_TCLKB+ E10 J33 RTM_TCLKA- H10 J33 RTM_TCLKA+ G10 TABLE 4. ZONE 3A POWER/NANAGEMENT CONNECTORS (J30/RP30) PINOUT. Con. Pin # Pin name Pin # Pin name Pin # Pin name Pin # Pin name J30 A1 3.3V (MP) A2 GND A3 12V (PWR) A4 GND B1 N/C B2 PS# B3 12V (PWR) B4 GND C1 SCL_L C2 SDA_L C3 ENABLE# C4 N/C D1 JTAG TCK* D2 JTAG TDO* D3 JTAG TDI* D4 JTAG TMS* *not available on the ATCA-PTSW-AMC4_RTM 8

9 2.4 AMC slots All four AMC slots comply with the PICMG AMC.1 R2.0 specification. For each slot there is one 4 PCIe link (AMC ports 4-7), AMC clocks and one SATA link (AMC port 2). AMC1 (port 0) slot also contains links to the GbE connector on the RTM. Table 5 shows the pin location of the various link types present for each slot (AMCx with x=1, 2, 3 or 4). TABLE 5. AMC SLOT CLOCK AND DATA PORT PINOUT. Name AMC Pin# AMC Pin Name Connec ts to AMCx_FCLKA- B81 MB_FCLKA- FPGA AMCx_FCLKA+ B80 MB_FCLKA+ FPGA AMCx_TCLKB- B78 MB_TCLKB- FPGA AMCx_TCLKB+ B77 MB_TCLKB+ FPGA AMCx_TCLKA- B75 MB_TCLKA- FPGA AMCx_TCLKA+ B74 MB_TCLKA+ FPGA PCIe_AMCx_Port_3_ Tx- PCIe_AMCx_Port_3_ Tx+ PCIe_AMCx_Port_3_ Rx- B69 MB_Tx7- PEX B68 MB_Tx7+ PEX B66 MB_Rx7- PEX AMCx_SATA_Rx-(2) B30 MB_Rx2- AMC AMCx_SATA_Rx+(2) B29 MB_Rx2+ AMC AMCx_SATA_Tx- (2) B33 MB_Tx2- AMC AMCx_SATA_Tx+(2) B32 MB_Tx2+ AMC GbE_RTM_to_AMC- (1) GbE_RTM_to_AMC+ (1) GbE_AMC_to_RTM- (1) GbE_AMC_to_RTM+ (1) B15 MB_Tx0- GbE (RTM) B14 MB_Tx0+ GbE (RTM) B12 MB_Rx0- GbE (RTM) B11 MB_Rx0+ GbE (RTM) PCIe_AMCx_Port_3_ Rx+ PCIe_AMCx_Port_2_ Tx- PCIe_AMCx_Port_2_ Tx+ PCIe_AMCx_Port_2_ Rx- PCIe_AMCx_Port_2_ Rx+ PCIe_AMCx_Port_1_ Tx- PCIe_AMCx_Port_1_ Tx+ PCIe_AMCx_Port_1_ Rx- B65 MB_Rx7+ PEX B63 MB_Tx6- PEX B62 MB_Tx6+ PEX B60 MB_Rx6- PEX B59 MB_Rx6+ PEX B54 MB_Tx5- PEX B53 MB_Tx5+ PEX B51 MB_Rx5- PEX AMCx_TCLKC- B135 MB_TCLKC- FPGA AMCx_TCLKC+ B136 MB_TCLKC+ FPGA AMCx_TCLKD- B138 MB_TCLKC- FPGA AMCx_TCLKD+ B139 MB_TCLKC+ FPGA (1) Available on AMC1 slot only. (2) SATA link between slots AMC1 and AMC2, and between slots AMC3 and AMC PCIe_AMCx_Port_1_ Rx+ PCIe_AMCx_Port_0_ Tx- PCIe_AMCx_Port_0_ Tx+ PCIe_AMCx_Port_0_ Rx- PCIe_AMCx_Port_0_ Rx+ B50 MB_Rx5+ PEX B48 MB_Tx4- PEX B47 MB_Tx4+ PEX B45 MB_Rx4- PEX B44 MB_Rx4+ PEX 9

11 3 PCI Express switching 3.1 PEX The PEX PCIe Gen2 switch contains 6 port stations. Up to 24 ports and up to 96 lanes are available. Table 6 shows the configured PEX ports and where each port is connected to. The PEX supports lane reversal while establishing lane negotiation on all ports. TABLE 6. PEX PORT LIST. Station# Port# Size Connects to ** RTM AMC2 5 4 AMC1 6 4 (n/a) 7 4 FPGA* ATCA#2 9 4 ATCA# ATCA# ATCA# ATCA# ATCA# ATCA# ATCA# AMC3* 17 4 AMC4* 18 4 (n/a) 19 4 ATCA# ATCA#3* 21 4 ATCA#4* 22 4 ATCA#5* 23 4 ATCA#6* (*) lanes are reversed between the PEX and the PCIe x16 connector on RTM. (**) alternative configurations (8, 4 ) are available using the configuration EEPROM 11

3.1.1 Upstream port selection The upstream port can be selected through the shunt resistors R920 to R924, connected to the PEX pins STRAP_UPSTRM_PORTSEL[4..0] (Table 7).

12 3.1.1 Upstream port selection The upstream port can be selected through the shunt resistors R920 to R924, connected to the PEX pins STRAP_UPSTRM_PORTSEL[4..0] (Table 7). The resulting number corresponds to the selected upstream port number. The default setting is Port 0 (PCIe x16 connector on RTM). For programming these settings via configuration EEPROM please refer to the PEX databook. TABLE 7. UPSTREAM PORT SELECTION. Signal Res. Description default STRAP_UPSTRM_PORTSEL4 R924 OFF (not present)=0 ; ON (present)= 1 0 STRAP_UPSTRM_PORTSEL3 R923 OFF (not present)=0 ; ON (present)= 1 0 STRAP_UPSTRM_PORTSEL2 R922 OFF (not present)=0 ; ON (present)= 1 0 STRAP_UPSTRM_PORTSEL1 R921 OFF (not present)=0 ; ON (present)= 1 0 STRAP_UPSTRM_PORTSEL0 R920 OFF (not present)=0 ; ON (present)= Port state The status of each port can be checked by observing LEDs D0 to D23 (the numbering of the LEDs corresponds to the PCIe port number on table 6). Table 8 describes the blinking patterns associated to each port state, valid for all ports. Please refer to the PEX databook for further information. TABLE 8. PEX PORT STATE LED BEHAVIOUR TABLE. 12

13 4 Clock Distribution This section describes how timing signals on the ATCA-PTSW-AMC4 are distributed on the board and to all endpoints within the ATCA shelf. 4.1 Cross-point switch The Cross-point switch (CPS), implemented on a Virtex-6 FPGA, distributes all timing signals to/from ATCA, AMC, or RTM endpoints. There are 5 clocks for each AMC slot, 5 clocks for the RTM and 6 clocks on the Timing interfaces. Table 9 lists the clock signals present on those interfaces. TABLE 9. CPS TIMING SIGNALS CORRESPONDENCE. AMC1 AMC2 AMC3 AMC4 RTM ATCA AMC1_TCLKA AMC2_TCLKA AMC3_TCLKA AMC4_TCLKA RTM_TCLKA CLK1A AMC1_TCLKB AMC2_TCLKB AMC3_TCLKB AMC4_TCLKB RTM_TCLKB CLK1B AMC1_TCLKC AMC2_TCLKC AMC3_TCLKC AMC4_TCLKC RTM_TCLKC CLK2A AMC1_TCLKD AMC2_TCLKD AMC3_TCLKD AMC4_TCLKD RTM_TCLKD CLK2B AMC1_FCLKA AMC2_FCLKA AMC3_FCLKA AMC4_FCLKA RTM_FCLKA CLK3A/3B* *CLK3A if module is inserted in slot 2; CLK3B if module is inserted in slot 1. The CPS, configured via firmware, establishes for each clock type (each row of the table) which location (column) is the source and which are the sinks. 4.2 Timing signals This section describes the timing signals that are managed by the CPS on the current firmware implementation PCIe Reference Clock The PCIe reference clock (REFCLK) is defined to use the CLK3A and CLK3B physical lines on the ATCA Timing and Synchronization interface. For the AMC and RTM devices it uses its respective FCLKA lines, corresponding to the last row of Table 9. These clock lines, and in analogy the remaining rows of Table 9, converge to the FPGA s CPS. The CPS presents an additional output of the the PCIe REFCLK to a de-jittering device, which supplies this clock to the PEX and to one of the FPGA s MGT transceiver s clock inputs where its PCIe endpoint is implemented. By default, the REFCLK source is PCIe host connected by external cabling to the RTM, corresponding to the default upstream port of the PEX (Port 0). Any other selection for the REFCLK source can be implemented by firmware MHz Clock and IRIG-B For the synchronization of all compliant endpoints, a 100MHz clock and IRIG-B timecode signals are distributed. The 100MHz clock uses TCLKA and CLK1B physical lines (first row of Table 9), while IRIG-B uses TCLKD and CLK2B (fourth row of Table 9). By default, both sources are located at the RTM. Other configurations can be implemented by firmware. 13

14 5 Rear Transition Module The ATCA-PTSW-AMC4_RTM is the Rear Transition Module (RTM) developed for the ATCA-PTSW-AMC4 (Front Board). Its main features are below summarised: PICMG 3.8 R1.0 compliant (ARTM Zone 3A ) PCI Express 16 external host adapter, PCI Express External Cabling Rev1.0. Four General purpose links (Optical or Ethernet) One Gigabit link (Ethernet only) 1 External Timing module (RMC-TMG-1588), featuring IEEE over Ethernet sync to an external Grand Master Clock. ATCA-PTSW-AMC4_RTM ( 1 link) Rear panel ETH1 0 ATCA Zone 3A (PICMG 3.8) ( 1 link) ( 1 link) 1 2 (0-3) connectors RP30 RP31 RP32 RP33 ( 1 link) 3 LINK OK ETH (0-3) Link status LEDs PCIe Redrivers PCIe (16 link) External Cable REFCLK (FCLKA) PCIe 16 PCIe 16 External cable connector GbE (1 link) RMC-TMG-1588 External timing module TCLKA TCLKB TCLKC TCLKD GbE LEMO (4 ) USB L1 L3 ETH2 RJ45 ETH1 LINK OK L2 L4 Mini USB (GbE) connector (GbE) Link status LED Ethernet RJ45 connector External Timing connectors (LEMO) Mini USB connector FIGURE 2 ATCA-PTSW-AMC4_RTM REAR TRANSITION MODULE BLOCK DIAGRAM AND PANEL 14

15 5.1 RTM Zone 3A Interface THE FABRIC CONNECTOR FOLLOWS THE ADVANCEDTCA REAR TRANSITION MODULE ZONE 3A, PICMG 3.8 R1.0. DESCRIBED ON SECTION 2.3. AND THE PINOUTS FOR ZONE 3A CONNECTORS RP30-RP33 ARE THE SAME AS ITS MATING PARTS J30-J33, LISTED ON TABLE 43 AND Table PCIeX16 Host Connector The connector to the PCI external cable is the PCIe 16 ipass (PS ). The connector includes the 16 PCIe lanes which are presented to dedicated PCIe re-drivers before being connecting to the Front Board, via the Zone 3A interface, along with the PCIe sideband signals. 5.3 PCIeX16 Re-drivers The PCIe re-drivers (National Semiconductors DS50PCI402) can be configured according to adapt to the system s physical conditions. The re-drivers parameters are set via onboard resistors R100-R127 shown on Figure 3. Tables 6, 7 and 8, taken from the DS50PCI402 datasheet, show how to set onboard resistors for each re-driver configuration parameter. ATCA-PTSW-AMC4_RTM ATCA Zone 3A (PICMG 3.8) PCIe Re-driver Configuration Resistors RP30 RP31 RP32 RP33 ATCA side R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 PCIe Redrivers R100 R102 R104 R106 R108 R110 R112 R114 R116 Cable side R101 R103 R105 R107 R109 R111 R113 R115 R117 PCIe (16 link) External Cable FIGURE 3 PCIE RE-DRIVERS AND CONFIGURATION RESISTORS 15

16 Table 10 and Table 11 present the available onboard resistor settings for Equalization (input) and De-Emphasis (output) data lanes, both on the ATCA (Zone 3A) side and on the cable side. De-Emphasis settings are Rate dependent and may be configured according to Table 12. TABLE 10. EQUALIZATION CONFIGURATION PINS FOR THE RE-DRIVERS PORTS. DEFAULT VALUES ARE SH ADED BLUE. EQ1 EQ0 ATCA Side Cable Side EQ Gain 1.25 GHz EQ Gain 2.5 GHz Suggested Use EQ1 EQ0 EQ1 EQ0 (db) (db) F F 0 0 Bypass 1 1 R103 R105 R107 R " FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable 0 0 R102 R104 R106 R " FR4 (6-mil trace) or 1m (28 AWG) PCIe cable F 0 R104 R " FR4 (6-mil trace) or 5m (26 AWG) PCIe cable 1 0 R103 R104 R107 R " FR4 (6-mil trace) or 7m (24 AWG) PCIe cable F 1 R105 R " FR4 (6-mil trace) or 9m (24 AWG) PCIe cable 0 1 R102 R105 R106 R " FR4 (6-mil trace) or 10m (24 AWG) PCIe cable 0 F R102 R m (24 AWG) PCIe cable 1 F R103 R > 15m (24 AWG) PCIe cable TABLE 11. DE-EMPHASIS CONFIGURATION PINS FOR THE RE-DRIVER PORTS. DEFAULT VALUES ARE SH ADED BLUE. DEM1 DEM0 ATCA Side Cable Side De-Emphasis (db) VOD (V) Suggested Rate = 2.5GHz DEM1 DEM0 DEM1 DEM0 0 0 R114 R116 R110 R112 0dB R114 R117 R110 R dB 1 8 inches FR4 (6-mil trace) or less than 1 meter (28 AWG) PCIe cable 1 0 R115 R116 R111 R112-6dB R115 R117 R111 R113-6dB 1 15 inches FR4 (6-mil trace) 0 F R114 R110-9dB 1 1 F R115 R111-12dB 1 F 0 R116 R112-9dB inches FR4 (6-mil trace) F 1 R117 R113-12dB inches FR4 (6-mil trace) TABLE 12. OTHER CONFIGURATION PINS FOR THE RE-DRIVERS. Signal Name Options Description RATE R100 R101 SD_TH R128,R129, R130, R131 Rate is internally detected. Forces Gen1 (2.5Gbps). Forces Gen2 (5Gbps). Threshold select pin for electrical idle detect threshold. Float pin for default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND to set threshold voltage (See Data Sheet). Default: FLOAT. 16

17 5.4 Connectors The ATCA-PTSW-AMC4_RTM contains 5 connector cages, depicted on the main RTM diagram on Figure 2. The top four s (0-3) may be grouped as a single 4 link, connecting to the MGT transceiver port of the FPGA, located on the Front Board. The last connects to the AMC1 Ethernet port. The connectors are reserved for future implementations. 5.5 RMC-TMG-1588 External Timing Module The RMC-TMG-1588 was developed as an external timing module add-on for the ATCA-PTSW-AMC4_RTM. Its main purpose is to generate the IRIG-B 100MHz clock and timecode signals for distribution to the ATCA-PTSW- AMC4 Front Board and, through the Front Boards s FPGA CPS, to all system endpoints. CLK100MHz uses RTM TCLKA physical line and IRIG-B timecode uses TCLKD. The generated clock signals are synchronized with the IEEE protocol, which core is implemented on the RMC-TMG-1588 local firmware. The module provides an RJ45 GbE connector where an external master clock unit should be connected. The IRIG-B clock and time code signals, as well as an auxiliary pulse-per-second (PPS) sync signal are made available at the external LEMO connectors. The overall scheme is presented on Figure 4. IRIG-B CLK100MHz (to CPS) RMC-TMG-1588 (RTM add-on) TCLKA=CLK 100MHz TCLKD=IRIG-B RJ45 L1 L2 L3 L4 IEEE Grand master clock Clk 100MHz PPS IRIG-B Mini USB FIGURE 4 RMC-TMG-1588 ADD-ON FOR ATCA-PTSW-AMC4_RTM WITH IEEE SYNC. 17

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