PICMG AMC.2 Revision 1.0. Ethernet Advanced Mezzanine Card Specification

Transcription

1 PICMG.2 Revision 1.0 Ethernet Advanced Mezzanine Card Specification March 1, 2007

2 Copyright 2007, PCI Industrial Computer Manufacturers Group The attention of adopters is directed to the possibility that compliance with or adoption of PICMG specifications may require use of an invention covered by patent rights. PICMG shall not be responsible for identifying patents for which a license may be required by any PICMG specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG MAKES NO WARRANTY OFANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG, CompactPCI, AdvancedTCA, ATCA, CompactPCI Express and the PICMG, CompactPCI, AdvancedTCA and ATCA logos are registered trademarks, and COM Express, MicroTCA, µtca, CompactTCA, AdvancedMC and SHB Express are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. PICMG.2 R1.0 Specification 4/9/07 Page 2

3 TABLE OF CONTENTS Revision History INTRODUCTION AND OBJECTIVES Overview Scope Introduction Conformance PICMG.2 conformance PICMG.0 conformance Dimensions Reference documents Reference specifications Environment and regulatory documents specification contributors Special word use Name and logo use Signal naming conventions Intellectual property Acronyms and definitions BACKGROUND Overview of Next generation mezzanine standard Port mapping Port definition COMMON OPTIONS AND FAT PIPES REGION SPECIFICATION Common electrical and Link Layer rules Gigabit Ethernet and 10 Gigabit Ethernet support Types and Module/ compatibility Fat Pipes region interoperability PICMG.2 R1.0 Specification 4/9/07 Page 3

4 3.3.2 Type E Links in the Common Options region Module/ compatibility IEEE ETHERNET TRANSPORT Introduction IEEE compliance Gigabit Ethernet compliance Gigabit Ethernet compliance SIGNAL INTEGRITY Gigabit Ethernet at 1.25 GBd and 10 Gigabit Ethernet at GBd Receiver Requirements at 1.25 GBd and GBd signal interconnection requirements for 1.25 GBd and GBd Channel transmission characteristics MANAGEMENT AND E-KEYING E-Keying introduction point-to-point connectivity record Link Grouping ID asymmetric match Examples Type E2/Type 2 Module example Type E2/Type 5 Module example APPENDIX A..0 PIN ASSIGNMENTS APPENDIX B. CARRIER TOPOLOGIES (INFORMATIVE) PICMG.2 R1.0 Specification 4/9/07 Page 4

5 LIST OF FIGURES Figure 1..2 reference Basic connector...9 Figure 2..2 reference with Extended connector...10 Figure 3. Four Modules on a AdvancedTCA Board...15 Figure 4. Port mapping regions...16 Figure 5..0 Port 2 and Port 3 mapping illustration...17 Figure GBd GbE minimum eye mask at receiver input pins...27 Figure GBd minimum eye mask at receiver (far end) input pins...28 Figure 8. Module and portions used for TX loss budget...29 Figure 9. Module and portions used for RX loss budget...30 Figure 10. Module and portions used for TX loss budget...31 Figure 11. Module and portions used for RX loss budget...32 Figure Type E2/Type 2 Module example...37 Figure Type E2/Type 5 Module example...38 Figure application example # Figure application Example # Figure application example # PICMG.2 R1.0 Specification 4/9/07 Page 5

6 LIST OF TABLES Table 1. Acronyms and definitions...14 Table 2. List of.2 Fat Pipes region Types...20 Table 3..2 Type E assignments...20 Table 4. Common Options region interoperability...21 Table 5. Fat Pipes region interoperability...21 Table 6..2 GbE Links and Ports...24 Table GbE links and Ports...24 Table 8. Allocation of Module to TX interconnect path insertion loss...30 Table 9. Allocation of Module to RX interconnect path insertion loss...30 Table 10. Allocation of Module to to Module TX interconnect path insertion loss...31 Table 11. Allocation of Module to to Module RX interconnect path insertion loss...32 Table 12. Link Type Extension...35 Table pin assignments...39 PICMG.2 R1.0 Specification 4/9/07 Page 6

7 Revision History Revision Level Date R1.0 3/1/2007 Initial adoption Action PICMG.2 R1.0 Specification 4/9/07 Page 7

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9 1 Introduction and objectives 1.1 Overview This specification,.2, defines the implementation of 1 and 10 Gbps Ethernet (PICMG BASE-BX and PICMG GBASE-BX4 subset of IEEE XAUI signalling, respectively) links on.0 Modules and s. The intended implementation practice will normally include at least one link of Ethernet. 1.2 Scope.2 is a subsidiary specification to.0 and is limited in scope to defining link usage, management and Electronic-Keying (E-Keying) parameters for Gigabit Ethernet (GbE) and 10 Gigabit Ethernet (10 GbE) on s and Boards..2 may be implemented with any of the allowable sizes supported by the.0 specification. Refer to.0 for definition of the Module s mechanical, interconnect, management, power and thermal requirements. Outside the scope of this specification are the following topics: Higher-layer protocols (such as IP or flow control) used over the GbE or 10 GbE links. Implementation or usage of link-to-link forwarding, routing, or bridging between the defined links. Link aggregation methods or protocols. Specified usage of ATCA Zone 2 Connectors. Specification of allowable data content. 1.3 Introduction Figure 1 and Figure 2 provide generic references for.2 functionality using the Basic and Extended Connectors, respectively. These figures show general Board and Module layouts for the possible link configurations. Ports not used by an.2 implementation may be used for other purposes. Ports not used by.2 may be defined by other compliant specifications. Two GbE Ports in Common Options Region of connector. Basic Connector ATCA Zone 3 (optional).2 Egress I/O (optional) Implementation Function(s) -based Termination ATCA Backplane (optional).2 Module Management Logic Management Figure 1..2 reference Basic connector PICMG.2 R1.0 Specification 4/9/07 Page 9

10 Optional second 10 GbE on Basic Two GbE Ports in Common Options Basic Connector. Region of connector. Connector ATCA Zone 3 (optional).2 Egress I/O (optional) Implementation Function(s) -based Termination ATCA Backplane (optional).2 Module Up to four GbE Ports OR one 10 GbE Port on the extended connector. Management Logic Extended Connector Management Figure 2..2 reference with Extended connector 1.4 Conformance PICMG.2 conformance Statements of compliance with this specification take the form specified in the PICMG Policies and Procedures for Specification Development: This product complies with PICMG.2 Revision 1.0 Products making this simple claim of compliance must provide, at a minimum, all features defined in this specification as being mandatory by use of the keyword shall in the body of the specification. Such products are encouraged to also provide recommended features associated with the keyword should and may provide permitted features associated with the key word may PICMG.0 conformance The.2 specification is dependent upon, and leverages,.0 for definition of the Module s mechanical, interconnect, management, power and thermal requirements. Requirements REQ 1.1 A PICMG.2 compliant Module and Board shall conform to the PICMG.0 Revision 2.0 specification. PICMG.2 R1.0 Specification 4/9/07 Page 10

11 1.5 Dimensions The controlling dimensions shall be millimeters (mm) unless noted otherwise. The controlling units shall be metric unless noted otherwise. In some cases, English units have been provided in addition to the metric units due to common industry usage. Dimensions shown with an asterisk (*) are found in the referenced standards. All other dimensions and tolerances indicated are specific to. 1.6 Reference documents The following sections list publications that are relevant to this specification. Many of the specifications are subject to periodic and independent updates and are the responsibility of their respective organizations. Version and/or revision numbers of each specification should be carefully checked if used in conjunction with this specification Reference specifications The following publications are used in conjunction with this standard. When any of the referenced specifications are superseded by an approved revision, that revision shall apply. All documents may be obtained from their respective organizations. IEEE Std Information Technology Telecommunication & Information Exchange between Systems LAN/MAN Specific Requirements Part 3: Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. See and PICMG.0 - Advanced Mezzanine Card Specification, Revision 2.0; PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 600, Wakefield, MA USA, Tel: , Fax: , PICMG Policies and Procedures for Specification Development, Revision 2.0, September 14, 2004, PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 600, Wakefield, MA USA, Tel: , Fax: , PICMG 3.0 Revision 2.0 AdvancedTCA Specification, PCI Industrial Computer Manufacturing Group. PICMG 3.1 Revision 1.0 AdvancedTCA Ethernet Specification, PCI Industrial Computer Manufacturing Group. Signal Integrity Analysis Application Note, PCI Industrial Computer Manufacturing Group Environment and regulatory documents All environmental and regulatory requirements that pertain to the PICMG.2 specification are cited within the PICMG.0 Base specification. PICMG.2 R1.0 Specification 4/9/07 Page 11

12 1.7.2 specification contributors The following companies participated in the the Member Review of PICMG.2. ADLink GNP Performance Technologies Agere Systems Huawei PICMG Japan Artesyn Hybricon Pigeon Point Systems Bustronic Intel RadiSys Communication Automation Interphase SBS Continuous Computing Kontron Sun DSS Networks Motorola Tyco FCI Nortel Networks Tekelec Foxconn Nokia TeraChip General Micro Systems NX Technology ZNYX Networks 1.8 Special word use This document uses the following key words: may (in bold text): Indicates the flexibility of choice with no implied preference. should (in bold text): Indicates flexibility of choice with a strongly preferred implementation. The use of should not (in bold text) indicates flexibility of choice with a strong preference that the choice or implementation be avoided. shall (in bold text): Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interoperability and to claim conformance with this specification. The use of shall not (in bold text) indicates an action or implementation that is prohibited. These keywords have their common meaning when not in bold text and when outside enumerated requirements. Though it is contrary to preferred editorial practice, these keywords have their special meaning when in bold text regardless of the location in the specification. Though it is contrary to preferred editorial practice, these keywords have their special meaning when used inside enumerated requirements even if not in bold text. 1.9 Name and logo use The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows: Permission to use the PICMG organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at during the period of time for which their membership dues are paid. Non-members must not use the PICMG organization logo. The PICMG organization logo must be printed in black or color as shown in the files available for download from the member s side of the Web site. Logos with or without the Open Modular Computing Specifications banner can be used. Nothing may be added or deleted from the PICMG logo. Manufacturers distributors and sales representatives may use PICMG trademarked and registered logos and trademarks (but not the PICMG organization logo) in promoting products sold under the name of the manufacturer. The use of these logos and trademarks is a privilege granted by the PICMG organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and who believe their products comply with these specifications. Use of the logos and trademarks by either members or PICMG.2 R1.0 Specification 4/9/07 Page 12

13 non-members implies such compliance. PICMG may revoke permission to use logos if they are misused. All trademarked and registered logos and trademarks must carry the tm or symbols as appropriate and must be attributed to PICMG. The logos may be found on the members side of the website Nonmembers may fill out the logo request form therein. The PICMG name and logo are registered trademarks of PICMG. Registered trademarks must be followed by the symbol, and the following statement must appear in all published literature and advertising material in which the logo appears: The PICMG name and logo are registered trademarks of the PCI Industrial Computer Manufacturers Group Signal naming conventions All signals are active high unless denoted by a trailing # symbol. Differential signals are denoted by a trailing + (positive) or (negative) symbol Intellectual property The Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ( IPR ). The Consortium takes no position concerning the evidence, validity, or scope of this IPR. The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium. Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. The Consortium shall not be responsible for identifying any or all such IPR. No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification. This specification conforms to the current PICMG Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made: Necessary Claims (referring to mandatory or recommended features): None. Unnecessary Claims (referring to optional features or non-normative elements): None. Refer to PICMG IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage. PICMG makes no judgment as to the validity of these claims or the licensing terms offered by the claimants. PICMG.2 R1.0 Specification 4/9/07 Page 13

14 1.12 Acronyms and definitions Acronyms and definitions used throughout this document are defined and referenced in the PICMG.0 base specification. In order to facilitate consistency between.0 and.2, they are not repeated here. Table 1 defines select terms that are either used in this document exclusive of the PICMG.0 definitions or have been included to emphasize their meaning. Table 1. Acronyms and definitions Term or Acronym GbE Description In this document, synonymous with 1000BASE-BX. 10 GbE In this document, synonymous with 10GBASE-BX4 1000BASE-BX 10GBASE- BX4 GBd The common name of the standard of a one gigabit-per-second Ethernet data link over two pairs of copper: one pair for transmit and one for receive. See the PICMG 3.1 specification for electrical specification. The common name of the standard that defines 10 gigabit-per-second Ethernet data link over eight pairs of copper: four pairs for transmit and four pairs for received. See the PICMG 3.1 specification for electrical specification. Gigabaud. A measure of signaling rate which includes encoding overhead. For example, a link delivering data at 1 Gigabit per second using an 8B/10B coding scheme is operating at 1.25 Gbd. PICMG.2 R1.0 Specification 4/9/07 Page 14

15 2.0 background 2.1 Overview of The.0 Specification defines a modular add-on or child card that extends the functionality of a Board (see Figure 3). Often referred to as mezzanines, these cards are called Modules or Modules throughout this document. Modules lie parallel to and are integrated onto the Board by plugging into an Connector. Boards may range from passive Boards with minimal intelligence to high performance single Board computers. Figure 3. Four Modules on a AdvancedTCA Board Modules enable a modular building block design for both industry standard and proprietary Boards. The.0 specification has the goal of enabling larger markets with more unique functions and creates economies of scale that lower prices. Modules range in terms of their functionality but typically include the following categories: Telecom connectivity (ATM/POS (OC-3/12/48), T1/E1, VoIP, GbE, etc.) Processors (CPUs, DSPs, and FPGAs) Network communication processors (NPUs) Network communications co-processors (Classification, Security or Intrusion Detection) Mass storage PICMG.2 R1.0 Specification 4/9/07 Page 15

16 2.1.1 Next generation mezzanine standard represents the industry s next generation mezzanine standard supporting high-speed interfaces and AdvancedTCA optimization. In the early 1990s, another base mezzanine standard was developed to support parallel interfaces and was optimized to support PCI and CompactPCI environments. This earlier specification is the IEEE-1386 Common Mezzanine Card (CMC) specification. Many subsidiary specifications to CMC have been developed including: IEEE Std PCI Mezzanine Card (PMC) PICMG 2.15 PCI Telecom Mezzanine/ Card (PTMC) ANSI/VITA , Processor PMC (PrPMC or PPMC) A new mezzanine specification, rather than an extension of the CMC standard, was required to meet the design objectives of high-speed serial LVDS interface support and AdvancedTCA optimization. As such, is not backward compatible with mezzanine standards based on the CMC specification. is designed to take advantage of the strengths of the PICMG 3.0 AdvancedTCA specification and the grade needs of Reliability, Availability, and Serviceability (RAS). These strengths and needs required a new Hot-Swappable mezzanine that could either maximize density through the use of stacked Modules or through the use of greater surface area and Component height. In addition, the needs of higher electrical power with higher I/O bandwidth were also compelling reasons to launch a new mezzanine base specification Port mapping Section 6, Interconnect of the.0 specification partitions use of the 20 available Ports into three recommended regions: Common Options region, Fat Pipes region, and Extended Options region (see Figure 4). The purpose of this partitioning is to provide the industry with guidelines that will ultimately encourage interoperability between Modules and Boards; they are not intended to reserve or prohibit link usage..2 follows this convention and makes Port assignments for the Common Options and Fat Pipes regions accordingly. Basic Connector Extended Connector Port No. TCLKA TCLKB FCLKA TCLKC/D Port Mapping Strategy Clocks Common Options Region Fat Pipes Region Extended Options Region Figure 4. Port mapping regions PICMG.2 R1.0 Specification 4/9/07 Page 16

17 2.3 Port definition A Port is defined as a pair of transmit and receive differential pairs. All differential pairs are bound by Logic Ground. The shielding function of a Logic Ground is used for differential pairs on both sides of the differential pair as appropriate. The point of reference for Transmit and Receive is that of the Module (i.e., signals are transmitted from a Module to the and received by a Module from the ). Ports are numbered from 0-20 as illustrated in Figure 4. For ease of reference, an excerpt from the.0 pin mapping is provided in Figure 5. The complete pin assignment table of the Module Card-edge interface is available in Appendix A. Port 2 Port 3 Pin No. Signal Driven by Mating Pin Function on the Module 28 GND First Logic Ground 29 Tx2+ Module Third Port 2 Transmitter + 30 Tx2- Third Port 2 Transmitter - 31 GND First Logic Ground 32 Rx2+ Third Port 2 Receiver + 33 Rx2- Third Port 2 Receiver - 34 GND First Logic Ground 35 Tx3+ Module Third Port 3 Transmitter + 36 Tx3- Third Port 3 Transmitter - 37 GND First Logic Ground 38 Rx3+ Third Port 3 Receiver + 39 Rx3- Third Port 3 Receiver - 40 GND First Logic Ground Figure 5..0 Port 2 and Port 3 mapping illustration PICMG.2 R1.0 Specification 4/9/07 Page 17

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19 3 Common Options and Fat Pipes region specification The term.2 Interfaces is used when referring to Gigabit Ethernet (GbE) and/or 10 Gigabit Ethernet (10 GbE) links. 3.1 Common electrical and Link Layer rules The PICMG.0 specification defines support for up to 12.5 Gbps signaling rates, which is sufficient to support defined.2 Interfaces. Requirement REQ 3.1 A PICMG.2 Module and Board shall conform to all the Link layer requirements as set forth in the Ethernet Specification(s) defined in Section 1.6, Reference specifications. 3.2 Gigabit Ethernet and 10 Gigabit Ethernet support.2 defines interface signaling for both GbE and 10 GbE. In the Common Options Region of the Connector, two Links of GbE are defined. In the Fat Pipes Region four Links of GbE are defined and one Link of 10 GbE is defined, sharing the same Extended Connector space on Ports 8 through 11. In the Fat Pipes Region of the Extended Connector either GbE or 10 GbE may be implemented, but not both. The port assignments defined by.2 are given in Section Types and Module/ compatibility Types and Module/ compatibility.2 Modules and Slots are associated with an.2 Type designation that indicates how many GbE and 10 GbE Links they support and on which Ports. The.2 Type designation has two parts: one part that describes the Links available on the Ports in the Common Options Region (see Section 3.3.2) and one part for the Fat Pipes Region (see Section 3.3.1). All combinations between the Common Options Region part and the Fat Pipes Region part are allowed by.2. Although the.0 compliant E-Keying mechanism (see Section 6 Management and E-Keying) does not use the concept of.2 Types, they are useful for easily determining what level of interoperability can be achieved between specific.2 Slots and.2 Modules, as described in Section Fat Pipes region interoperability Table 2 enumerates the.2 Types available within the Fat Pipes Region. The Type designators apply to both the.2 Modules and Slots. PICMG.2 R1.0 Specification 4/9/07 Page 19

20 Table 2. List of.2 Fat Pipes region Types Basic Connector Port Basic + Extended Type 1 Type 2 Type 3 Type 4 Type 5 Type GbE GbE GbE GbE GbE 9 GbE GbE GbE 10 GbE GbE 10 GbE 10 GbE 11 GbE Requirements REQ 3.2 REQ 3.3 REQ 3.4 PICMG.2 Modules and Slots shall support one of the Types defined in Table 2, if the Fat Pipes Region of the Connector is used. If fewer than four Links of GbE are implemented in the Fat Pipes Region, Links shall be implemented beginning with Port 8 and progressing through Ports 9 and 10. Selection between 1 GbE and 10 GbE shall be performed exclusively by E-keying Type E Links in the Common Options region.2 specifies the optional assignment of one or two Ports in the Common Options Region for use as GbE Links (see Table 3). It is intended that the Type E implementation may be referenced by subsidiary specifications other than.2. Support for Type E is independent of the support for an.2 Fat Pipes interface. It is possible to support both interfaces on the same Module or. Requirements REQ 3.5 PICMG.2 Type E1 and Type E2 Modules and s shall provide Ethernet interfaces according to Table 3. Table 3..2 Type E assignments Port Number Type E1 Type E2 0 GbE GbE 1 (unassigned) GbE 2 (unassigned) (unassigned) 3 (unassigned) (unassigned) Module/ compatibility The.2 Type-naming specifications help identify common configurations of possible.2 products. The family of specifications does not require an exact match of Types between the Module and to achieve some level of functionality. In general, the connectivity obtained by plugging in a particular Module to a given will be a set-intersection of the Links supported by both. PICMG.2 R1.0 Specification 4/9/07 Page 20

21 Table 4 and Table 5 give the resulting connectivity in the various situations possible between s and Modules that are identified by name in this section. Table 4 and Table 5 provide the number of Links available between the Module and the. The light gray shade indicates full Module functionality, and the dark gray shade indicates no Module functionality. Table 4. Common Options region interoperability Module Type E1 Type E2 Type E1 1 GbE 1 GbE Type E2 1 GbE 2 GbE Table 5. Fat Pipes region interoperability Module Type 1 Type 2 Type 3 Type 4 Type 5 Type 6 Type 1 1 GbE 1 GbE 1 GbE 1 GbE Type 2 1 GbE 2 GbE 2 GbE 2 GbE Type 3 1 GbE 2 GbE 3 GbE 3 GbE Type 4 1 GbE 2 GbE 3 GbE 4 GbE Type GbE 1 10GbE Type GbE 2 10GbE These tables may be reproduced in.2 product documentation to clarify for the user what the expected result would be when combining.2 products. PICMG.2 R1.0 Specification 4/9/07 Page 21

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23 4 IEEE Ethernet transport 4.1 Introduction.0 provides an array of differential-signal pairs assigned to 20 Ports that are provided for Module-to- and Module-to-Module communication. As explained in Section 2.3 each Port includes a transmit pair and a receive pair. This section defines how Ports are used when they are in compliance with IEEE compliance IEEE specifies the signaling and formatting of data packets sent over the medium. The structure and composition of the Ethernet frame is the same regardless of the type of medium used to carry the frame. For complete details see the IEEE specification documents..2 requires no interpretation of the content of the Ethernet frame..2 Modules and s use one or both of two Ethernet Media types: 1000BASE-BX, which uses two pairs (one Port) to establish an Ethernet link that carries one Gb/s data in both directions 10GBASE-BX4, which uses eight pairs (four Ports) to establish an Ethernet link that carries 10 Gb/s data in both directions The requirements and Port assignments associated with each of these media types are provided in the following sections. Requirements REQ 4.1 REQ 4.2 REQ 4.3 An.2 Module or shall support at least one Ethernet link of one of the types described in Table 2 or Table 3. For 1000BASE-BX links,.2 Modules and s should enable IEEE autonegotiation as defined in Clause 37 for all parameters except for signaling speed. For 1000BASE-BX links having devices that do not support auto-negotiation, the parameters should be set to full duplex without flow control. PICMG.2 R1.0 Specification 4/9/07 Page 23

24 4.3 Gigabit Ethernet compliance An.2 Module may have up to six 1000BASE-BX Gigabit Ethernet links. The Ports of the Connector used for each Ethernet link are shown in Table 6. Table 6..2 GbE Links and Ports.2 GbE Link Port number Comments 0 0 Common Options Region 1 1 Common Options Region 2 8 Fat Pipes Region 3 9 Fat Pipes Region 4 10 Fat Pipes Region 5 11 Fat Pipes Region Each.2 GbE link is operated independent of any other link, although they may be used to provide aggregated paths. Requirements REQ 4.4 The signaling interfaces of Module and Slot Ports assigned to PICMG.2 Type E1, Type E2, Type 1, Type 2, Type 3 and Type 4 support shall conform to PICMG BASE- BX Gigabit Ethernet compliance An.2 Module may have up to two 10GBASE-BX4 10 Gigabit Ethernet (10 GbE) links. The Ports of the Connector used for each Ethernet link are shown in Table 7. Table GbE links and Ports.2 10GbE Link Signal pair # Port number The 10GbE link 0 uses the same Ports as GbE links 2, 3, 4 and 5. If any of these GbE links are used, the 10GbE link 0 cannot be used. Conversely, if 10GbE link 0 is used, GbE links 2, 3, 4, and 5 cannot be used. The 10GbE link 1 uses Ports on the Basic Side of the Connector (Component Side 2 of the ). Requirements PICMG.2 R1.0 Specification 4/9/07 Page 24

25 REQ 4.5 The signaling interfaces of Module and Slot Ports assigned to PICMG.2 Type 5 and Type 6 support shall conform to PICMG GBASE-BX4. PICMG.2 R1.0 Specification 4/9/07 Page 25

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27 5 Signal integrity This section describes the electrical requirements for.2-compliant Modules and s at both 1.25 GBd (for GbE) and GBd (for 10 GbE). An ancillary document,.2 Signal Integrity Analysis Application Note, which can be found on the PICMG website, discusses the signal integrity analysis that was performed to arrive at these requirements. The IEEE specification and the PICMG 3.1, Rev 1.0 specification, provide definition of 1.25 GBd and GBd operation. 5.1 Gigabit Ethernet at 1.25 GBd and 10 Gigabit Ethernet at GBd Receiver Requirements at 1.25 GBd and GBd For.2 at 1.25 GBd, the received LVDS differential signal must provide an eye larger than the eye mask shown in Figure 6. This mask must be observed across all environmental conditions. Figure GBd GbE minimum eye mask at receiver input pins PICMG.2 R1.0 Specification 4/9/07 Page 27

28 For.2 at GBd, the received eye mask will be per Figure 7. This is the worst-case specification across all environmental conditions. 0.2UI 200mV 0.45UI Requirements Figure GBd minimum eye mask at receiver (far end) input pins REQ 5.1 REQ 5.2 REQ 5.3 REQ 5.4 Minimum eye opening at the receiving end of a Link operating at 1.25 GBd on.2 Modules and s shall comply with the eye mask specified in Figure 6. Maximum deterministic jitter at the receiving end of a Link operating at 1.25 GBd on.2 Modules and s shall comply with the maximum jitter requirement per the eye mask shown in Figure 6. Minimum eye opening at the receiving end of a Link operating at GBd on.2 Modules and s shall comply with the eye mask for GBd operation as shown in Figure 7 of this specification. Maximum jitter at the receiving end of a Link operating at GBd on.2 Modules and s shall comply with the maximum jitter requirement for GBd operation as shown in Figure 7 of this specification. PICMG.2 R1.0 Specification 4/9/07 Page 28

29 signal interconnection requirements for 1.25 GBd and GBd Even though the minimum required eye amplitude is 200 mv, a margin of mv is recommended over the minimum due to the broad assumptions made for simulation purposes. Therefore, a 350 mv 400 mv eye opening is preferred. Several test cases indicated that there is adequate margin for both the configurations; Module-to- as well as Module-to--to-Module. These test cases indicated that the capacitor location is not critical at GBd. However, for clarity, capacitor locations are recommended for the TX and RX paths. The.2 Module follows capacitor placement requirements as defined in the.0 specification. At the longest trace lengths specified, the simulations indicated that some 10GBASE-BX4 compliant GBd devices could potentially see relatively small margins above the required 10GBASE-BX4 eye mask. This is due to particular device characteristics, frequency dependent trace losses (skin effect loss and dielectric loss), effects of the plated through holes, and the Connectors Channel transmission characteristics Module-to-: TX Link The maximum loss values in decibels (db) are specified for the Module to TX Link including the Connector. This budget distribution serves as a design guideline to help achieve the specified eye diagrams..2 Module-to to- TX Link Configuration Device #1 LM T LC T 0.01µF Device # Module (1.6mm thick) Connector 0.01µF 2.4mm thick = BGA via for 14 layer 1.6mm thick board = connector via for 20 layer 2.4mm thick board = Cap and BGA via for 20 layer 2.4mm thick board Figure 8. Module and portions used for TX loss budget PICMG.2 R1.0 Specification 4/9/07 Page 29

30 The losses shown in Table 8 are based on the simulation of the Module to TX Link. Table 8. Allocation of Module to TX interconnect path insertion loss Loss parameter Symbol Loss budget value at GHz Loss budget value at GHz Module LM T db db LC T db db Module-to-: RX Link The maximum loss values in decibels (db) are specified for the Module and RX Link including the Connector. This budget distribution serves as a design guideline to help achieve the specified eye diagrams..2 Module-to to- RX Link Configuration LM R LC R Device #1 0.01µF Device # µF Module (1.6mm thick) Connector 2.4mm thick = BGA via for 14 layer 1.6mm thick board = connector via for 20 layer 2.4mm thick board = Cap and BGA via for 20 layer 2.4mm thick board Figure 9. Module and portions used for RX loss budget The losses shown in Table 9 are based on the simulation of the Module to RX Link. Table 9. Allocation of Module to RX interconnect path insertion loss Loss parameter Symbol Loss budget value at GHz Loss budget value at GHz Module LM R db db LC R db db Module-to--to-Module: TX Link The maximum loss values in decibels (db) are specified for the Module and TX Link including the Connector. This budget distribution serves as a design guideline to help achieve the specified eye diagrams. PICMG.2 R1.0 Specification 4/9/07 Page 30

31 .2 Module-to to--to-module TX Configuration Device #1 LM T 2.4mm thick LMR T Device #2 0.01µF Module (1.6mm thick) LMCM T 0.01µF Module (1.6mm thick) Connector = BGA & Cap via for 14 layer 1.6mm thick board = connector via for 20 layer 2.4mm thick board Figure 10. Module and portions used for TX loss budget The losses shown in Table 10 are based on the simulation of the Module to to Module TX Link. Table 10. Allocation of Module to to Module TX interconnect path insertion loss Loss Parameter Symbol Loss Budget Value at GHZ Loss Budget Value at GHz Module Transmit LM T db db LMCM T db db Module Receive LMR T db db PICMG.2 R1.0 Specification 4/9/07 Page 31

32 Module-to--to-Module: RX Link The maximum loss values in decibels (db) are specified for the Module and RX Link including the Connector. This budget distribution serves as a design guideline to help achieve the specified eye diagrams..2 Module-to to--to-module RX Configuration Device #1 LM R 0.01µF 2.4mm thick LMR R Device # µF Module (1.6mm thick) LMCM R Module (1.6mm thick) Connector = BGA & Cap via for 14 layer 1.6mm thick board = connector via for 20 layer 2.4mm thick board Figure 11. Module and portions used for RX loss budget The losses in Table 11 are based on the simulation of the Module to to Module RX Link. Table 11. Allocation of Module to to Module RX interconnect path insertion loss Loss parameter Symbol Loss budget value at GHz Loss budget value at GHz Module Transmit LM R db db LMCM R db db Module Receive LMR R db db Requirements REQ 5.5 REQ 5.6 REQ 5.7 REQ 5.8 The trace length for GBd.2 compliant signals on a Module, from the transmitter to the Card-edge interface, shall not exceed 76 mm. The trace length for GBd.2 compliant signals on a, from the transmitter to the Connector shall not exceed 381 mm. The trace length for GBd.2 compliant signals on a Module, from the Card-edge interface to the receiver, shall not exceed 76 mm. The trace length for GBd.2 compliant signals on a, from the Connector to the receiver shall not exceed 381 mm. PICMG.2 R1.0 Specification 4/9/07 Page 32

33 REQ 5.9 Maximum trace length on a between two Module Connectors shall not exceed 305 mm for operation at GBd with.2 support. REQ 5.10 Maximum difference in length on the traces of a differential pair to the Connector on an.2 Module shall not exceed 0.75 mm for operation at GBd. At 1.25 GBd, a 1.5 mm of length difference can be tolerated. REQ Modules shall be capacitively coupled at the Module receiver interface to isolate transmitter and receiver common mode voltages. REQ Modules shall be direct coupled at the transmitter interface. REQ s providing an.2 Module-to- configuration shall be capacitively coupled at the receiver interface to isolate transmitter and receiver common mode voltages. REQ s providing an.2 Module-to- configuration shall be direct coupled at the transmitter interface. REQ 5.15 For 1 GbE links, the AC coupling capacitors at the receiver shall be no more than 10 nf +1% and matched within 2% with each other. REQ 5.16 For 10 GbE links, the AC coupling capacitors at the receiver shall be no more than 470 pf +1% and matched within 2% with each other. PICMG.2 R1.0 Specification 4/9/07 Page 33

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35 6 Management and E-Keying This section defines how to implement Electronic-Keying (E-Keying) required by the.0 specification on.2 Modules and Boards. The text requires understanding of the.0 specification, and is focused on the added information necessary for an.2 implementation. Refer to Section 3.3,.2 Types and Module/ compatibility. Examples are provided in Section 6.4 asymmetric match. The subsections of this section follow the outline of subsections of Section 3 of the.0 specification. Subsections that are not cited in this section do not have any additional requirements under E-Keying introduction E-Keying is a mechanism that identifies which Ports of the Module and the are compatible. The basic management role of both components is as follows: The Module via its MMC provides FRU information to the s IPMC. This information structure identifies which Links are supported and which subsidiary specifications they implement. For further information and the definitions of terms, see Section 3 of the.0 specification..0 allows the implementation of Modules and s that support a mix of subsidiary specifications. For example, on a Module it is possible to support Links specified by both.1 and.2. The specific values required to identify.2 protocol configurations in the descriptors are defined in the following subsections. Other values must be obtained from the.0 specification or other subsidiary specifications, if required. 6.2 point-to-point connectivity record.0 Section defines the Point-to-Point Connectivity Record, which contains Channel Descriptors and Link Descriptors. The Link Descriptors include the Link Type and Link Type Extension which are used to designate the use of the Link as defined by this specification,.2. See Table 3-16 of.0 for a full description. The Link Type value will always be 05h, which indicates the use of the.2 specification. The Link Type Extension for each link will be the value indicated in Table 12. All other values for Link Type Extension are reserved. Table 12. Link Type Extension Value 1h 2h.. Fh Definition 1000BASE-BX (SerDES Gigabit) Ethernet link 10GBASE-BX4 10 Gigabit Ethernet link Reserved PICMG.2 R1.0 Specification 4/9/07 Page 35

36 Requirements REQ 6.1 For Modules and s, the Link Descriptors of.2 compatible Links shall set the Link Type to 05h and the Link Type Extension to the value according to Table 12. The 10 GbE Link consists of four lanes, therefore it always requires four Ports. To facilitate consistency between implementations, the.2 specification requires the four lanes of a 10 GbE interface to be enumerated in a single Channel Descriptor. 6.3 Link Grouping ID The Link Descriptor includes the Link Grouping ID field which may be used to associate multiple Links. Links of an or which have an identical descriptor value in this field are assigned to be part of the same group. The specific value of the Link Grouping ID (which is 8 bits in size) is implementation specific. No interpretation of the value is specified, other than they are compared to other instances of the Link Grouping ID field. A common practice with Ethernet is to aggregate links in bundles or trunks to provide higher bandwidth and a layer of fault-tolerance than is provided by a single Ethernet link..2 allows the use of the Link Grouping ID field by implementations to indicate the intent to aggregate Ethernet links. Link aggregation may be implemented over any combination of Links, as long as the Links are of the same type. Specifically, 1 GbE links are aggregated with other 1 GbE links and not with 10 GbE links. Some implementations may also rely on higher-layer protocols such Link Aggregation Control Protocol (LACP) as described in IEEE 802.3ad or similar protocol to set up and control Ethernet links. These protocols, which are outside the scope of this specification, may co-exist and override structure identified by the collection of Link Grouping ID fields. For this reason the usage of the Link Grouping ID as described here is a recommendation and not a requirement. Requirements REQ 6.2 REQ 6.3 An Module may use the Link Grouping ID field to establish aggregated Ethernet links. An may use the Link Grouping ID field to establish aggregated Ethernet links. PICMG.2 R1.0 Specification 4/9/07 Page 36

37 6.4 asymmetric match All versions of Ethernet being symmetric, this bit field of the Link Descriptor will be set to 00b on Modules and s to signify the requirement for exact match. Requirements REQ 6.4 For.2 Links the Asymmetric Match field value shall be set to 00b. 6.5 Examples The examples in this section give the values specified by.2 within the Point-to-Point Connectivity record for Modules as described in Section of Type E2/Type 2 Module example Figure 12 shows an example of a typical data structure describing an.2 Module with four GbE links. Because each link is generally operated as its own channel, and does not depend or relate to any other link, there are four Channel Descriptors. The Channel Descriptors call out the first four links available to.2, which are two in the Common Options region and two in the Fat Pipes region. Channel Descriptors Lane 3 Lane 2 Lane 1 Lane 0 Only Lane 0 of each Channel Descriptor is used. 1Fh 1Fh 1Fh 0 1Fh 1Fh 1Fh 01h Point-to-Point Connectivity Record 1Fh 1Fh 1Fh 1Fh 1Fh 1Fh 08h 09h Header Part Channel Descriptors Link Descriptors Link Descriptors Reserved Asym. Match Link Group ID Link Type Ext. Link Type Link Designator 5h 10 5h 101h Each Link requires a symmetric match, and is designated to be a GbE link. 5h 5h 102h 103h Figure Type E2/Type 2 Module example PICMG.2 R1.0 Specification 4/9/07 Page 37

38 Type E2/Type 5 Module example Another.2 configuration might include two GbE links in the Common Options region and one 10 GbE link in the Fat Pipes region as shown in Figure 13. In this case, the four Ports used in the Fat Pipes region are associated with each other as four lanes of a Link, so they are referenced from a single Channel Descriptor. Channel Descriptors Lane 3 Lane 2 Lane 1 Lane 0 The 10 GbE Channel uses four.0 links. 1Fh 1Fh 1Fh 0 1Fh 1Fh 1Fh 01h Point-to-Point Connectivity Record 0Bh 0Ah 09h 08h Header Part Channel Descriptors Link Descriptors Link Descriptors Reserved Asym. Match Link Group ID Link Type Ext. Link Type Link Designator 5h 10 5h 101h Each Link requires a symmetric match, and is designated to be a GbE link. 1h 5h F02h Figure Type E2/Type 5 Module example PICMG.2 R1.0 Specification 4/9/07 Page 38

39 Appendix A..0 pin assignments Table 13 is a copy of the.0 R2.0 pin assignments. Table pin assignments Module Edge Connector Pin Assignment Basic Side (Component Side 1) Extended Side (Component Side 2) Pin No. Signal Driven by Mating Pin Function on the Pin No. Signal Driven by Mating Pin Function on the 85 GND First Logic Ground 86 GND First Logic Ground 84 PWR First Payload Power 87 Rx8- Third Port 8 Receiver - 83 PS0# Last Presence 0 88 Rx8+ Third Port 8 Receiver + 82 GND First Logic Ground 89 GND First Logic Ground 81 FCLKA- FCLKA Third Fabric Clock A - 90 Tx8- Third Port 8 Transmitter - 80 FCLKA+ driver Third Fabric Clock A + 91 Tx8+ Third Port 8 Transmitter + 79 GND First Logic Ground 92 GND First Logic Ground 78 TCLKB- TCLKB Third Telecom Clock B - 93 Rx9- Third Port 9 Receiver - 77 TCLKB+ driver Third Telecom Clock B + 94 Rx9+ Third Port 9 Receiver + 76 GND First Logic Ground 95 GND First Logic Ground 75 TCLKA- TCLKA Third Telecom Clock A - 96 Tx9- Third Port 9 Transmitter - 74 TCLKA+ driver Third Telecom Clock A + 97 Tx9+ Third Port 9 Transmitter + 73 GND First Logic Ground 98 GND First Logic Ground 72 PWR First Payload Power 99 Rx10- Third Port 10 Receiver - 71 SDA_L IPMI Agent Second IPMB-L Data 100 Rx10+ Third Port 10 Receiver + 70 GND First Logic Ground 101 GND First Logic Ground 69 Rx7- Third Port 7 Receiver Tx10- Third Port 10 Transmitter - 68 Rx7+ Third Port 7 Receiver Tx10+ Third Port 10 Transmitter + 67 GND First Logic Ground 104 GND First Logic Ground 66 Tx7- Third Port 7 Transmitter Rx11- Third Port 11 Receiver - 65 Tx7+ Third Port 7 Transmitter Rx11+ Third Port 11 Receiver + 64 GND First Logic Ground 107 GND First Logic Ground 63 Rx6- Third Port 6 Receiver Tx11- Third Port 11 Transmitter - 62 Rx6+ Third Port 6 Receiver Tx11+ Third Port 11 Transmitter + 61 GND First Logic Ground 110 GND First Logic Ground 60 Tx6- Third Port 6 Transmitter Rx12- Third Port 12 Receiver - 59 Tx6+ Third Port 6 Transmitter Rx12+ Third Port 12 Receiver + 58 GND First Logic Ground 113 GND First Logic Ground 57 PWR First Payload Power 114 Tx12- Third Port 12 Transmitter - 56 SCL_L IPMI Agent Second IPMB-L Clock 115 Tx12+ Third Port 12 Transmitter + 55 GND First Logic Ground 116 GND First Logic Ground 54 Rx5- Third Port 5 Receiver Rx13- Third Port 13 Receiver - 53 Rx5+ Third Port 5 Receiver Rx13+ Third Port 13 Receiver + 52 GND First Logic Ground 119 GND First Logic Ground 51 Tx5- Third Port 5 Transmitter Tx13- Third Port 13 Transmitter - 50 Tx5+ Third Port 5 Transmitter Tx13+ Third Port 13 Transmitter + 49 GND First Logic Ground 122 GND First Logic Ground 48 Rx4- Third Port 4 Receiver Rx14- Third Port 14 Receiver - 47 Rx4+ Third Port 4 Receiver Rx14+ Third Port 14 Receiver + 46 GND First Logic Ground 125 GND First Logic Ground 45 Tx4- Third Port 4 Transmitter Tx14- Third Port 14 Transmitter - 44 Tx4+ Third Port 4 Transmitter Tx14+ Third Port 14 Transmitter + 43 GND First Logic Ground 128 GND First Logic Ground 42 PWR First Payload Power 129 Rx15- Third Port 15 Receiver - 41 ENABLE# Second Enable 130 Rx15+ Third Port 15 Receiver + 40 GND First Logic Ground 131 GND First Logic Ground 39 Rx3- Third Port 3 Receiver Tx15- Third Port 15 Transmitter - 38 Rx3+ Third Port 3 Receiver Tx15+ Third Port 15 Transmitter + 37 GND First Logic Ground 134 GND First Logic Ground 36 Tx3- Third Port 3 Transmitter TCLKC- TCLKC Third Telecom Clock C - 35 Tx3+ Third Port 3 Transmitter TCLKC+ Driver Third Telecom Clock C + 34 GND First Logic Ground 137 GND First Logic Ground 33 Rx2- Third Port 2 Receiver TCLKD- TCLKD Third Telecom Clock D - 32 Rx2+ Third Port 2 Receiver TCLKD+ Driver Third Telecom Clock D + 31 GND First Logic Ground 140 GND First Logic Ground PICMG.2 R1.0 Specification 4/9/07 Page 39

40 Basic Side (Component Side 1) Module Edge Connector Pin Assignment Extended Side (Component Side 2) 30 Tx2- Third Port 2 Transmitter Rx17- Third Port 17 Receiver - 29 Tx2+ Third Port 2 Transmitter Rx17+ Third Port 17 Receiver + 28 GND First Logic Ground 143 GND First Logic Ground 27 PWR First Payload Power 144 Tx17- Third Port 17 Transmitter - 26 GA2 Second Geographic Addr Tx17+ Third Port 17 Transmitter + 25 GND First Logic Ground 146 GND First Logic Ground 24 Rx1- Third Port 1 Receiver Rx18- Third Port 18 Receiver - 23 Rx1+ Third Port 1 Receiver Rx18+ Third Port 18 Receiver + 22 GND First Logic Ground 149 GND First Logic Ground 21 Tx1- Third Port 1 Transmitter Tx18- Third Port 18 Transmitter - 20 Tx1+ Third Port 1 Transmitter Tx18+ Third Port 18 Transmitter + 19 GND First Logic Ground 152 GND First Logic Ground 18 PWR First Payload Power 153 Rx19- Third Port 19 Receiver - 17 GA1 Second Geographic Addr Rx19+ Third Port 19 Receiver + 16 GND First Logic Ground 155 GND First Logic Ground 15 Rx0- Third Port 0 Receiver Tx19- Third Port 19 Transmitter - 14 Rx0+ Third Port 0 Receiver Tx19+ Third Port 19 Transmitter + 13 GND First Logic Ground 158 GND First Logic Ground 12 Tx0- Third Port 0 Transmitter Rx20- Third Port 20 Receiver - 11 Tx0+ Third Port 0 Transmitter Rx20+ Third Port 20 Receiver + 10 GND First Logic Ground 161 GND First Logic Ground 9 PWR First Payload Power 162 Tx20- Third Port 20 Transmitter - 8 RSRVD8 Second Reserved, not assigned 163 Tx20+ Third Port 20 Transmitter + 7 GND First Logic Ground 164 GND First Logic Ground 6 RSRVD6 Second Reserved, not assigned 165 TCK Second JTAG Test Clock Input 5 GA0 Second Geographic Addr TMS Second JTAG Test Mode Select In 4 MP First Management Power 167 TRST# Second JTAG Test Reset Input 3 PS1# Last Presence TDO Second JTAG Test Data Output 2 PWR First Payload Power 169 TDI Second JTAG Test Data Input 1 GND First Logic Ground 170 GND First Logic Ground PICMG.2 R1.0 Specification 4/9/07 Page 40