CorePCIX. v2.0. High Performance Customizable PCI-X Bus Interface

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1 v2.0 CorePCIX Product Summary Intended Use High Performance Customizable PCI-X Bus Interface Key features PCI-X 1.0a Compliant 100 MHz PCI-X Transfers 33 MHz PCI 2.2 Legacy Support PCI-X Only Option 133 MHz PCI-X Transfers Lower Gate Count for Embedded Applications Local Bus Interface Additional Logic can be Easily Integrated Easily Connect Local Bus to FIFOs Implemented in FPGA Embedded RAM Blocks Minimal Latency Customizable, Programmable, Single-Chip Solution Highly-Parameterized Core Web-based Configuration and Delivery Permits Personalization and Reduction of Unused Logic Both Target and Master Functions Both 32-bit and 64-bit Operation Supports Split Completion Supports PCI-X/PCI Commands Supports PCI-Only Commands 4kb Bursts for Data throughput of up to 1GB/sec Designed for Repeatable Timing Results with Minimal Place-and-Route Effort Targeted Family Axcelerator Core Deliverables Netlist Version Compiled RTL Simulation Model, Compliant with the Actel Libero Integrated Design Environment (IDE) Fixed Configuration Netlist Compatible with the Actel Designer Place-and-Route Tool (with and without I/O pads) User-Defined Configuration Supported Via Web-based Configuration System RTL Version VHDL or Verilog Core Source Code Synthesis Scripts Actel-Developed Testbenches Simple to use VHDL and Verilog Testbenches Complete Reference Design (Figure 2 on page 3) VHDL and Verilog Source Code PCI-X to SDRAM Memory DMA Controller Split Completion Logic Development System Complete PCI-X Development System Available (Optional) 100 MHz PCI-X Plug-in Card Complete Reference Design Windows-Compatible Support Drivers Synthesis and Simulation Support Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler Simulation: Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Verification and Compliance PCI-X 1.0a Compliance Verified Using Catalyst TA700-X-E PCI-X Exerciser May Actel Corporation

2 Table of Contents Section Page Initiator Control Local Bus Initiator Interface General Description 2 CorePCIX Delivery Mechanism 2 CorePCIX Device Requirements 2 Reference Design 3 Recommended Design Experience 3 Architecture 4 PCI-X/PCI Interface Description 6 CorePCIX Parameters 12 Local Bus Interface 14 CorePCIX Design Examples 41 Ordering Information 43 General Description CorePCIX provides an easy-to-use, highly flexible, high-performance interface to the PCI bus. The PCI core is available in two versions: PCI-X/PCI 2.2 Supports PCI-X up to 100 MHz Supports conventional PCI Ideal for applications in which the PCI-X/PCI bus configuration is unknown or variable: PCI-X add-in cards such as frame buffers, network adaptors and data acquisition boards Systems with many configurations Transitional systems with mixed PCI-X and PCI devices PCI-X Supports PCI-X up to 133 MHz Does not support conventional PCI Smaller size results in lowest cost implementation Ideal for applications in which the PCI-X/PCI bus configuration is known: Embedded applications with a single or limited known configurations such as networking, industrial, HiRel and Telecom Cost-sensitive applications requiring the smallest programmable logic devices Designs requiring the quickest time to market There are two versions: one provides a fully compliant PCI-X 1.0a with PCI 2.2 support solution. The other provides a lower gate count PCI-X only solution optimized for embedded systems that operate in PCI-X mode only. PCI-X/PCI Bus PCI Configuration Space Datapath Target Control PCI Target Decoder Figure 1 CorePCIX Block Diagram Local Bus Target Interface CorePCIX Delivery Mechanism CorePCIX is available in both netlist and RTL formats. For netlist cores, a standard configuration core is provided. To reconfigure the core (i.e. define the configuration space parameters), Actel provides a web-based form to licensed customers. When the form is completed, Actel generates a netlist that fulfills the user requirements. The configurable parameters are described in Table 9 on page 12 through Table 12 on page 13. For RTL cores, the complete source code is provided allowing the user to directly synthesize the core with the desired parameterization. CorePCIX Device Requirements CorePCIX is a high performance core targeted for the Axcelerator family. The actual device performance and utilization varies based on the core configuration. Table 1 shows the typical core-only utilization. A complete PCI-X implementation will also require the user to implement logic to connect the core to the required backend interface, as shown in Tables 13 and 14. The size of this logic can be significant. Table 1 on page 3 also shows the reference design utilization that includes split completion support, DMA controllers, and an SDRAM controller (Figure 2 on page 3). CorePCIX meets PCI-X timing requirements when implemented in an AX500-3, AX or AX device. 2 v2.0

3 Table 1 CorePCIX Utilization Cells or Tiles Core Type Combinatorial Sequential Device PCI Performance Utilization PCI-X Only AX MHz 33.5% PCI-X with PCI2.2 Support AX MHz 38.0% Reference Design* 5,685 3,920 AX MHz 52.5% Reference Design with PCI2.2 Support* 6,111 4,090 AX MHz 56.0% Note: *Includes PCI-X or PCI-X/PCI core Reference Design Actel provides a complete reference design that implements all the logic required around the core to implement a complete PCI-X solution. This code is supplied as both VHDL and Verilog source code, enabling it to be easily adapted to fit into the actual application. The reference design implements a PCI-X/PCI interface with an internal DMA controller to an external SDRAM module and to internal FPGA SRAM memory. This demonstrates a complex interface to external SDRAM, requiring the implementation of split completion logic and a simple interface to internal SRAM memory. Refer to the CorePCIX Design Examples section on page 41 for more information. Axcelerator DEVICE init Init Arbiter DMA Ctrl SDRAM PCI-X/ PCI PCI-X Core Arbiter SDRAM Ctrl SDRAM targ Targ Ctrl DMA Registers Internal SRAM Figure 2 PCI-X Reference Design Recommended Design Experience CorePCIX implements the complex PCI-X/PCI protocol logic and provides an easy to use backend interface. Along with the provided reference design, a compete PCI-X solution can be implemented with reasonable effort. However, implementing a 133 MHz PCI-X-based system is a challenging design activity at the system design level, RTL implementation, and layout phases. Actel provides support through its Design Consulting Services to aid in the process. Table 2 lists devices supported by CorePCIX Table 2 CorePCIX supported Devices Device Speed Grade Package AX500 3 FG484 AX500 3 FG676 AX FG484 AX FG676 AX BG729 AX FG896 AX FG896 AX FG1152 v2.0 3

4 Architecture CorePCIX consists of five main blocks as shown in Figure 3. The PCI-X/PCI Initiator Control block implements the bus initiator functions (master) for both PCI-X and PCI operations. It contains a state machine that implements the PCI-X/PCI initiator protocol. The PCI-X/PCI Target Control block responds to the PCI bus activity as a target for both PCI-X and PCI activity. It contains a state machine that implements the PCI-X/PCI target protocol. The PCI-X/PCI Data Path implements the data path through the core. This is a high performance 64-bit wide data path that enables data from the Initiator, Target, or Configuration Space block to be read from or written to the PCI bus. It handles the 64 to 32-bit multiplexing requirements, as well as parity generation and checking. The PCI-X/PCI Configuration Space block implements the PCI-X/PCI type 00 configuration space, including the extensions required for PCI-X. Finally, the PCI-X/PCI decode block implements the address decoder required for target operations. Initiator Control Local Bus Initiator Interface PCI-X/PCI Bus Datapath Target Control Local Bus Target Interface PCI Configuration Space PCI Target Decoder Figure 3 CorePCIX Architecture 4 v2.0

5 Port Diagram Figure 4 illustrates the CorePCIX ports by function. Port descriptions are provided in the following sections: PCI Bus Signals section on page 6 Local Bus Target Signals section on page 28 Local Bus Target Signals section on page 28 Local Bus Miscellaneous Signals section on page 40 pci_clk pci_rst_n pci_req_n pci_gnt_n pci_frame_n pci_irdy_n pci_devsel_n pci_trdy_n pci_stop_n pci_idsel pci_ad[63/31#:0] pci_cbe_n[7/3#:0] pci_par pci_perr_n pci_serr_n pci_inta_n pci_req64_n pci_ack64_n pci_par64 PCI-X/PCI SIGNALS INITIATOR LOCAL BUS SIGNALS init_enable init_req init_gnt init_req_size_64_32_n init_cmd[3:0] init_addr[63:0] init_attr[35:0] init_trans_active init_trans_start init_trans_end init_trans_status[4:0] init_data_req init_data_response[1:0] init_data_xfer_size_64_32_n init_wr_ack init_wr_xfer init_wr_last init_wr_data[63/31#:0] init_rd_en init_rd_last init_rd_be[7/3#:0] init_rd_data[63/31#:0] local_mode_pcix_pci_n local_mode_pcix_66 local_mode_pcix_100 local_mode_pcix_133 local_mode_64_32_n local_int local_pcix_set_split_comp_disc local_pci_cmd[15:0] local_pci_status[15:0] local_pcix_cmd[15:0] local_pcix_status[31:0] MISC TARGET LOCAL BUS SIGNALS targ_accepts_64_32_n targ_trans_active targ_trans_start targ_trans_end targ_cs[4:0] targ_addr_64_32_n targ_addr[63:0] targ_cmd[3:0] targ_wr_rd_n targ_burst targ_attr[35:0] targ_data_req targ_data_req_init targ_data_req_cont targ_data_response[6:0] targ_data_xfer_size_64_32_n targ_wr_en targ_wr_data[63/31#:0] targ_wr_be[7/3#:0] targ_rd_ack targ_rd_xfer targ_rd_data[63/31#:0] targ_rd_be[7/3#:0] Figure 4 CorePCIX Interfaces v2.0 5

6 PCI-X/PCI Interface Description PCI Bus Signals Interface Description The CorePCIX PCI signals are listed in Table 3 and Table 4. Refer to Chapter 2 (pages 7-20) of the PCI Local Bus Specification for a detailed description of the PCI signals. Table 3 32-bit PCI Bus Signals CorePCIX Port Type PCI Specification Signal Name pci_clk Input CLK (Clock) pci_rst_n Input RST# (Reset) pci_req_n REQ# (Request) pci_gnt_n Input GNT# (Grant) pci_frame_n Bidirectional FRAME# (Cycle Frame) pci_irdy_n Bidirectional IRDY# (Initiator Ready) pci_devsel_n Bidirectional DEVSEL# (Device Select) pci_trdy_n Bidirectional TRDY# (Target Ready) pci_stop_n Bidirectional STOP# (Stop) pci_idsel Input IDSEL (Initialization Device Select) pci_ad[63/31#:0] Bidirectional AD (Address and Data) pci_cbe_n[7/3#:0] Bidirectional C/BE# (Bus Command and Byte Enables) pci_par Bidirectional PAR (Parity) pci_perr_n Bidirectional PERR# (Parity Error) pci_serr_n Open Drain SERR# (System Error) pci_inta_n Open Drain INTA# (Interrupt A) Note: # = port size for 64-bit CorePCIX / 32-bit CorePCIX, respectively. Table 4 64-bit PCI Bus Signals CorePCIX Port Type PCI Signal pci_req64_n Bidirectional REQ64# (Request 64-bit Transfer) pci_ack64_n Bidirectional ACK64# (Acknowledge 64-bit Transfer) pci_par64 Bidirectional PAR64 (Parity Upper DWORD) Note: # = port size for 64-bit CorePCIX / 32-bit CorePCIX, respectively. PCI Configuration Space CorePCIX implements the Header Type 00 PCI configuration registers as detailed in the PCI Local Bus Specification Revision 2.2 and the Addendum to the PCI Local Bus Specification Revision 1.0a. See Table 4 on page 6, Table 5 on page 7, Table 6 on page 7, and Table 7 on page 7. 6 v2.0

7 Table 5 Standard Type 00 Configuration Registers ADDR BYTE3 BYTE2 BYTE1 BYTE0 00 Device ID Vendor ID 04 Status Command 08 Class Code Revision ID 0C BIST Header Type Latency Timer Cache Line Size C Base Address Registers CardBus CIS Pointer 2C Subsystem ID Subsystem Vendor ID 30 Expansion ROM Base Address 34 Reserved Capabilities Pointer 38 Reserved 3C Max Latency Min Grant Interrupt Pin Interrupt Line Table 6 Capabilities List ADDR BYTE3 BYTE2 BYTE1 BYTE0 40 PCI-X Command Next Capability PCI-X Capability ID 44 PCI-X Status Table 7 Standard Type 00 Configuration Registers ADDR PCI Configuration Register Vendor ID Device ID Command Register Description Read Only: This field identifies the manufacturer of the device. Reads return the value of parameter VENDOR_ID Read Only: This field identifies the particular device. Reads return the value of parameter DEVICE_ID Command Register Bits: Bits 10, 8, 6, and 2..1 are Read/Write. Others are Read Only Bits (Reserved) = Not implemented Bit 10 (Interrupt Disable): Set to disable interrupt generation if PCI 2.3 Support enabled Bit 9 (Fast Back-to-Back Enable) = 0. Not implemented Bit 8 (SERR# Enable): Set to enable system error reporting Bit 7 (Reserved) = 0. Not implemented Bit 6 (Parity Error Response): Set to enable parity error (PERRn) reporting Bit 5 (VGA Palette Snoop) = 0. Not implemented Bit 4 (Memory Write and Invalidate Enable) = 0. Not implemented Bit 3 (Special Cycles) = 0. Not implemented Bit 2 (Bus Master): Set to enable CorePCIX to master the PCI bus. Ignored in PCI-X mode for Split Completion transactions Bit 1 (Memory Space): Set to enable memory accesses Bit 0 (I/O Space) = 0. Not implemented. All BARs are memory spaces v2.0 7

8 Table 7 Standard Type 00 Configuration Registers ADDR Status 08 Revision ID Status Register Bits: Bits and 8 are Read/Write. Writing a 1 to a bit location, clears that bit. Writing a 0 to a bit location has no effect. Other bits are read only Bit 15 (Detected Parity Error): Set if the core detected a parity error Bit 14 (Signaled System Error): Set if the core asserted SERRn Bit 13 (Received Master Abort): Set if the core terminated an initiator transaction with master abort (no target claimed the transaction by asserting DEVSEL#) Bit 12 (Received Target Abort): Set if the core received a target abort termination from the target during an initiator transaction Bit 11 (Signaled Target Abort): Set to indicate that the core asserted target abort while it was the target of a transaction Bits (DEVSEL timing) = 10. This is a slow decode device Bit 8 (Master Data Parity Error): Set if the core asserted PERR# on an initiator read or detected PERR# asserted on an initiator write and Parity Error Response (bit 6) in the Command Register is enabled Bit 7 (Fast Back-to-back Capable) = 0. Not implemented Bit 6 (Reserved) = 0. Not implemented Bit 5 (66 MHz capable) = value of parameter PCI_66MHZ_CAPABLE Bit 4 (Capabilities List) = 1. A capabilities linked list starts at address offset 0x34 Bit 3 (Interrupt Status): Status of the local bus local_int interrupt input Bits 2..0 (Reserved) = 000. Not implemented Read Only: This register specifies the device specific revision identifier. Reads return the value of parameter REVISION_ID 0B - 09 Class Code Read Only: The Class Code identifies the generic function of the device. Reads return the value of parameter CLASS_CODE 0C 0x0C: Cache Line Size Read Only: (Reserved) = 0x00. Not implemented 0D PCI Configuration Register 0x0D: Latency Timer Register Description Read/Write: The Latency Timer register is written with the number of clock cycles that the PCI core is allowed to retain control of the PCI bus. Bits 2..0 are hardwired to 000, so the smallest value that may be written is 0x8. The default value is set to 64 as specified in the PCI-X specification 0E 0x0E: Header Type Read Only: This register reads 0x00 to indicate that the PLD complies to the standard PCI configuration register mapping and that it is a single function device 0F 0x0F: BIST Not implemented. Reads return 0x00 8 v2.0

9 Table 7 Standard Type 00 Configuration Registers ADDR Up to three memory Base Address Registers (BARs) are supported. I/O BARs are not supported. All three memory BARs are implemented as 64-bit (as required by PCI-X Specification) The three BARs are configured through three parameters particular to that BAR: BARx_ENABLE is set to implement the BAR or clear to not implement the BAR. If all three BARs are not implemented, then the BARs must be implemented in consecutive order beginning with BAR0 BARx_PREFETCHABLE is returned as the read only prefetchable status bit (Bit 3) BARx_SIZE sets the size of the region decoded by the BAR == 2BARx_SIZE; valid values are 12 to 63 (4kb to 2 63 Bytes); 2 40 =1,024GB The meaning of the bit fields for the upper DWORD of the BARs is as follows: Bits are Read/Write Base Address Register 0 Bits Written to specify where to locate this region in memory space (when appended to Read/Write Bits of the lower DWORD and to hardcoded bits [11:0] == 0x000 results in the 4kbyte-aligned, 64-bit base address of the BAR) The meaning of the bit fields for lower DWORD of the BARs is as follows: Bits are Read/Write; are read only Bit Written to specify where to locate this region in memory space (see upper DWORD description above) Bits Hardcoded to 0x00 to limit the minimum BAR size to 4kb Bit 3 = Prefetchable: Reads return the value of parameter BARx_PREFETCHABLE.Bits 2..1 = 10 (for locate anywhere in 64-bit address space) Bit 0 = 0 to indicate that this is a memory space BAR 1F-18 Base Address Register 1 See description of Base Address Register 0 above Base Address Register 2 See description of Base Address Register 0 above 2B - 28 Card Bus CIS Pointer Not implemented. Reads return 0x D - 2C 2F - 2E PCI Configuration Register Subsystem Vendor ID Subsystem ID Exp. ROM Base Addr. Reg. Register Description Read Only: Additional vendor information. Reads return the value in parameter SUBSYSYSTEM_VENDOR_ID Read Only: Additional device information. Reads return the value in parameter SUBSYSYSTEM_ID The expansion ROM Base Address Register is supported.two parameters control the behavior of the Expansion ROM BAR EXP_ROM_ENABLE is set to implement the BAR; clear to not implement EXP_ROM_SIZE sets the size of the region decoded by the BAR == 2^EXP_ROM_SIZE; valid values are 12 to 31 (4kb to 2 GB) Read/Write: Expansion ROM Base Address Register Bit Written to specify where to locate this region in memory space Bits = 0..0 Reserved Bit 0 = Set by S/W to enable decoding the Expansion ROM and clear to disable 34 Capabilities Pointer Read Only: Reads return 0x40 indicating that the capabilities list starts at address 0x Reserved Not implemented. Reads return 0x B - 38 Reserved Not implemented. Reads return 0x v2.0 9

10 Table 7 Standard Type 00 Configuration Registers ADDR 3C 3D 3E 3F PCI Configuration Register Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Register Description Read/Write if parameter INT_ENABLE is set: Written by configuration software to indicate to which system interrupt line INTAn is connected. Read Only = 0 if parameter INT_ENABLE is clear Read Only: Only PCI interrupt INTAn is implemented by the PCI core, so this register always reads 0x01 when parameter INT_ENABLE is set or 0 when INT_ENABLE is clear Read Only: This register is set to the minimum amount of 250 ns time increments that the PCI core wants to retain mastership of the PCI bus assuming a 33 MHz clock rate. This register returns the value of the MIN_GRANT parameter Read Only: Specifies how often a device needs access to the PCI bus. This register returns the value of the MAX_LATENCY parameter Table 8 Capabilities List ADDR PCI Configuration Register Register Description 40 PCI-X Capability ID Read Only: Reads return 0x07 indicating that this is a PCI-X register set. 41 Next Capability Read Only: Reads return 0x00 indicating that this is the last capability in the list PCI-X Command Command Register Bits: Bits 6..0 are Read/Write. Others are Read Only Bits (Reserved) = Not implemented Bits 6..4 (Maximum Outstanding Split Transactions): Software sets to the maximum number of Split Transactions that the PCI core is permitted to have outstanding: 0=1, 1=2, 2=3, 3=4, 4=8, 5=12, 6=16, and 7=32. On reset, this register is set to the value of the DEF_MAX_SPLIT_TRANS parameter Bits 3..2 (Maximum Memory Read Byte Count): Software sets to the maximum byte count that can be used by an initiator read bust command: 0=512, 1=1024, 2=2048, and 3=4096 bytes Bit 1 (Enable Relaxed Ordering): If this bit is set, the local bus is permitted to initiate transactions with the Relaxed Ordering bit set in the Requester Attributes Bit 0 (Data Parity Error Recovery Enable): Software sets this bit to enable the device to attempt to recover from data parity errors 10 v2.0

11 Table 8 Capabilities List ADDR PCI Configuration Register Register Description PCI-X Status Status Register Bits: Bits 29, 19, and 18 are Read/Write. Writing a 1 to a bit location, clears that bit. Writing a 0 to a bit location has no affect. Other bits are Read Only Bits (Reserved) = 00. Not implemented Bit 29 (Received Split Completion Message): Set when the core receives a Split Completion message with the Split Completion Error bit set Bits (Designed Maximum Cumulative Read Size): Reads return the value of the DESIGNED_MAX_CUM_RD_SIZE parameter Bits (Designed Maximum Outstanding Split Transactions): Reads return the value of the DESIGNED_MAX_SPLIT_TRANS parameter Bits (Designed Maximum Memory Read Byte Count): Reads return the value of the DESIGNED_MAX_MEM_RD_BCNT parameter Bit 20 (Device Complexity): Reads return the value of the DEVICE_COMPLEXITY parameter Bit 19 (Unexpected Split Completion): Set by the PCI core if an unexpected Split Completion with this device's Requester ID is received Bit 18 (Split Completion Discarded): Set by the PCI core if a Split Completion transaction was not accepted by the requester. Bit 17 (133 MHz Capable): Reads return the value of the PCI_133_CAPABLE parameter Bit 16 (64-bit Device): Reads return the value of the PCI_64_32_N parameter Bits (Bus Number): Indicates the bus number on which the PCI core device resides Bits 7..3 (Device Number): Indicates the number of the device on which the PCI core device resides Bits 2..0 (Function Number) = 000 to indicate that the core is always function #0 v2.0 11

12 CorePCIX Parameters The CorePCIX contains numerous parameters to enable users to customize the core for their application. Parameters are provided for users to control the contents of the PCI read-only configuration registers, to support configurable memory base address registers, and to scale the feature set to make optimum use of PLD resources. For netlist versions of the core, Actel has provided a web-based form to set these parameters. Actel then creates a specific netlist built to these parameters. RTL users can directly set these parameters. The parameters listed in Table 9 have a drastic impact on the functionality of the core and should be carefully selected. Table 9 Core Version Parameters Parameter Size Description CONVENTIONAL_PCI_ENABLE Bit Set to support PCI-X with backward compatible support for conventional PCI. Clear to support PCI-X only. Note that supporting PCI-X is only technically a violation of the PCI-X Specification but is perfectly acceptable if the user can guarantee (as in many embedded or fixed implementation systems) that conventional PCI mode will not be required. Setting this parameter requires that the design meet both the 133 MHz PCI-X and the 66 MHz PCI timing criteria and results in a larger core with more difficult timing constraints than when this bit is clear to indicate support for PCI-X mode only. The Local Bus interface ports are identical for both PCI-X and conventional PCI modes of operation although some ports on the Local Bus interface have different meanings in PCI-X mode than in conventional PCI mode PCI23_ENABLE Bit Set to set the conventional PCI to support the PCI 2.3 specification. The PCI-X specification requires PCI 2.2 support only. Specifically, this enables the interrupt disable bit in the PCI command register PCI_64_32_N Bit Set to implement a 64-bit CorePCIX; clear to implement a 32-bit CorePCIX INT_ENABLE Bit Interrupt Enable: Set to enable support for interrupts. Clear to disable support for interrupts Table 10 lists the 64-bit Memory-base address registers (BAR0, BAR1, and BAR2), each with three parameters. Table 10 Base Address Register Parameters Parameter Size Description BAR0_ENABLE Bit Set to enable this Memory Base Address Register. If clear, all accesses to the BAR are ignored and the BAR reads return all zeros. If fewer than three BARs are implemented, they must be implemented in sequential order starting from BAR0. Disabled BARs minimize out during synthesis so unused BARs do not consume any PLD resources BAR0_PREFETCHABLE Integer Set if the memory region defined by this Base Address Register is prefetchable. If a region is marked as prefetchable, read performance will be improved. A region may not be marked as prefetchable if there are any side effects on reads. Generally, spaces mapped to block memories (such as SDRAM, SRAM) are prefetchable while spaces mapped to control registers are not BAR0_SIZE Bit Sets the desired size of the BAR. The size set is 2^BAR0_SIZE. Valid values are 12 to 63 (4 kb to 2 63 GB) i.e. BARx_SIZE == 16 => 2 16 = 64 kb i.e. BARx_SIZE == 20 => 2 20 = 1 MB i.e. BARx_SIZE == 34 => 2 34 = 16 GB BAR1_ENABLE Bit See description of BAR0_ENABLE above BAR1_PREFETCHABLE Integer See description of BAR0_PREFETCHABLE above BAR1_SIZE Bit See description of BAR0_SIZE above BAR2_ENABLE Bit See description of BAR0_ENABLE above BAR2_PREFETCHABLE Integer See description of BAR0_PREFETCHABLE above BAR2_SIZE Integer See description of BAR0_SIZE above 12 v2.0

13 Table 11 lists the one expansion ROM Base Address Registers with two parameters. Table 11 Expansion ROM Parameters Parameter Size Description EXP_ROM_ENABLE EXP_ROM _SIZE Table 12 lists the read-only PCI-X/PCI Configuration Space parameters. Bit Integer Table 12 Read-only PCI-X/PCI Configuration Space Parameters Parameter Size Description VENDOR_ID [15:0] DEVICE_ID [15:0] REVISION_ID [7:0] CLASS_CODE [23:0] PCI_66MHZ_CAPABLE Bit SUBSYSYSTEM_VENDOR_ID [15:0] SUBSYSYSTEM_ ID [15:0] MIN_GRANT [7:0] MAX_LATENCY [7:0] DEF_MAX_SPLIT_TRANS [2:0] DESIGNED_MAX_CUM_RD_SIZE [2:0] DESIGNED_MAX_SPLIT_TRANS [2:0] DESIGNED_MAX_MEM_RD_BCNT [1:0] DEVICE_COMPLEXITY PCI_133_CAPABLE Bit Bit Set to enable the Expansion ROM BAR. If clear, all accesses are ignored and the Expansion ROM BAR reads 0x Sets the desired size of the Expansion ROM BAR. The size set is 2^EXP_ROM_SIZE. Valid values are 12 to 31 (4 kb to 2 GB) e.g. EXP_ROM_SIZE == 16 => 2 16 = 64 kb e.g. EXP_ROM_SIZE == 20 => 2 20 = 1 MB Set this parameter to the vendor ID assigned to the user's company by the PCI Special Interest Group. If used in an embedded application in which all of the PCI bus devices in the system are known, this field may be set to any value that will not conflict with another PCI device. The Actel vendor ID is 11AA hex and may be used with Actel s permission Assigned by the user. Should be a unique identifier that distinguishes this card from all of the company's other PCI cards Assigned by the user. Set by the user to identify different revisions of the PLD code Set in accordance with the PCI Specification to identify the device class to which this device belongs Set if the device supports conventional PCI at 66 MHz. Clear for 33 MHz. The CorePCIX supports both 66 and 33 MHz. This bit indicates whether the place-and-route of CorePCIX was done to achieve 66 or 33 MHz conventional PCI performance. This parameter only affects the read data of bit 5 of the PCI Status Register and is otherwise unused Mandatory. Assigned by the user. Set to uniquely identify cards that use the same vendor ID and device ID Mandatory. Assigned by the user. Set to uniquely identify cards that use the same vendor ID and device ID Specifies how long a burst period the device needs assuming a clock rate of 33 MHz. Set to 0 to indicate no major requirements Specifies how often the PCI core needs access to the PCI bus. Set to 0 to indicate no major requirements. Reset default value for PCI-X Command Register Bits [6:4] (Maximum Outstanding Split Transactions) This parameter is returned as PCI-X Read Only Status Register bits [28:26] (Designed Maximum Cumulative Read Size) This parameter is returned as PCI-X Read Only Status Register bits [25:23] (Designed Maximum Outstanding Split Transactions) This parameter is returned as PCI-X Read Only Status Register bits [22:21] (Designed Maximum Memory Read Byte Count) This parameter is returned as PCI-X Read Only Status Register bit 20 (Device Complexity) This parameter is returned as PCI-X Read Only Status Register bit 17 (133 MHz capable). Set if the device supports PCI-X at 133 MHz. Clear for 66 MHz. The CorePCIX supports both 133 and 66 MHz. This bit indicates whether the place-and-route of CorePCIX was done to achieve 133 or 66 MHz. This parameter only affects the read data of bit 17 of the PCI-X Status Register and is otherwise unused. v2.0 13

14 Local Bus Interface The Local Bus Interface is divided into independent Initiator (Master) and Target (Slave) interfaces to make the local bus easy to use. Local Bus Initiator Signals The Local Bus initiator interface signals are described in Table 13. Table 13 Local Bus Initiator Interface Port Type Function init_enable init_req init_req_size_64_32_n init_cmd[3:0] init_addr[63:0] Note: Input Input Input Input * = port size for 64-bit CorePCIX / 32-bit CorePCIX respectively. Set if initiator operation has been enabled in the configuration register space; initiator requests will not be granted unless init_enable is 1 Assert to request that a new command be started; init_cmd, init_addr_64_32_n, init_addr, init_req_size_64_32_n, and init_attr must be valid when init_req is asserted. Local bus logic is free to change the command information on any clock cycle with init_req asserted or deasserted in order to elevate a higher priority command over a lower priority command. Once asserted, init_req must remain asserted at least until init_active is sampled asserted, at which time init_req may remain asserted to pipeline a new request or indicate the desire to do a very long transfer. If left asserted, init_req must be deasserted at latest combinatorially with init_trans_end if it is not desired to request the start of a new transaction Requested data transfer size; set for 64-bit, clear for 32-bit. This signal must always be 0 for 32-bit PCI-X/PCI cores PCI-X/PCI command; dual address cycle commands are indicated by init_addr_64_32_n and are never indicated on init_cmd init_addr contains either the PCI starting address for the command or a Split Completion Address depending upon init_cmd: PCI Starting Address (init_cmd!= Split Completion): If init_addr[63:32] is non-zero, then a 64-bit dual address cycle transaction will be generated using the full 64-bit address. If init_addr[63:32] is 0, then a 32-bit single address cycle transaction will be generated using init_addr[31:0]. Any access into the < 4 GB range and any nonmemory access must use a 32-bit address (as per PCI Specification). If a 64-bit transaction begins on a non-64-bit aligned address, then the transaction will be demoted to 32-bit (required for conventional PCI). This change is transparent to the Local Bus (data is still accepted on init_wr_data in the size requested via init_req_size_64_32_n) and will appear as if the target demoted the transaction to 32-bit. Alignment to a 64-bit boundary will be achieved at the first disconnect on an ADB and a subsequent transaction to complete the desired byte count would then be completed at the desired 64-bit size Split Completion Address (init_cmd == Split Completion): The init_addr contains the Split Completion Address which identifies the original requestor transaction. See PCI-X Specification section for information for forming the Split Completion Address. The init_addr[63:32] must be 0 in this case 14 v2.0

15 Table 13 Local Bus Initiator Interface (Continued) Port Type Function init_attr[35:0] Input Contains the attributes for the current transaction; byte enables are generated on data automatically going to the PCI bus by the core from init_attr[35:32], init_attr[7:0], and the starting address. This is true for both burst and nonburst (DWORD) commands. For nonburst transactions, the attributes are reformed by the core to include the byte enables in the relevant location The meaning of init_attr depends upon init_mode_pcix_pci_n and whether init_cmd is a Split Completion command PCI-X Mode (init_mode_pcix_pci_n == 1); Non-Split Completion Burst Transaction Encoded per the Burst Transaction Requester Attribute Bit Assignments in the PCI-X Specification: Bits {[35:32], [7:0]}: Requested number of bytes to transfer in this transaction; 0 is a special case and indicates 4,096 bytes Bit 31 (Reserved): Must be set to 0 by Local Bus Bit 30 (No Snoop): Set by Local Bus (in accordance with usage in PCI-X) Bit 29 (Relaxed Ordering): set by Local Bus (in accordance with usage in PCI-X) Bits [28:24] (Tag): set by Local Bus (in accordance with usage in PCI-X) Bits [23:16] (Requester Bus Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values Bits [15:11] (Requester Device Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values Bits [10:8] (Requester Function Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values PCI-X Mode (init_mode_pcix_pci_n == 1); with Split Completion (Burst) Transaction Encoded as per the Completer Attribute Bit Assignments in the PCI-X Specification: Bits {[35:32], [7:0]}: Requested number of bytes to transfer in this transaction; 0 is a special case and indicates 4,096 bytes Bit 31 (Byte Count Modified): Set by Local Bus (in accordance with usage in PCI-X) Bit 30 (Split Completion Error): Set by Local Bus (in accordance with usage in PCI-X) Bit 29 (Split Completion Message) set by Local Bus (in accordance with usage in PCI-X) Bits [28:24] (Reserved): Must be set by Local Bus to 00000Bits Bits [23:16] (Completer Bus Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values Bits [15:11] (Completer Device Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values Bits [10:8] (Completer Function Number): These inputs are ignored by the core. The core will correctly set these PCI attribute bits from its configuration space values PCI Mode (init_mode_pcix_pci_n == 0); all commands Patterned after the Burst Transaction Requester Attribute Bit Assignments in the PCI-X Specification: Bits {[35:32], [7:0]}: Requested number of bytes to transfer in this transaction; 0 is a special case and indicates 4,096 bytes Bits [31:8] (Reserved): All fields are reserved. Set to 0x v2.0 15

16 Table 13 Local Bus Initiator Interface (Continued) Port Type Function init_gnt Asserted for one clock cycle in response to an asserted init_req to indicate that the transaction requested on the last clock cycle will be tried on the PCI bus as soon as PCI-X/PCI arbitration is successful init_trans_active Asserted when a local bus PCI transaction is actively being executed on the PCI-X/PCI bus init_trans_start Asserted for one clock to indicate that the PCI-X/PCI bus transaction has started init_trans_end Asserted for one clock to indicate that the PCI-X/PCI bus transaction has ended init_trans_status[4:0] init_data_req Note: * = port size for 64-bit CorePCIX / 32-bit CorePCIX respectively. Initiator transaction status; valid when init_end_trans is asserted 00001: Complete This termination condition occurs when the transaction ends and the entire requested bye count has transferred 00010: Incomplete This termination condition occurs when the transaction ends without transferring the entire requested bye count. The local bus must issue a new request to complete the transaction. This termination condition occurs on a target retry or initiator disconnect, target disconnect, or master latency timeout when all requested data did not transfer Split Response, Target Abort, and Master Abort also indicate an incomplete transaction; however, the Local Bus must take a different action than retrying the transaction where it last ended: 00110: Split_Response (PCI-X Only) The target ended the transaction with Split Response and has assumed responsibility for completing the transaction; the transaction should not be retried 01010: Target Abort The target ended the transaction with target abort; the transaction should not be retried 10010: Master Abort The target did not claim the transaction resulting in a master abort termination; the transaction should not be retried Local bus initiator continuation request. Initiator transactions are partitioned into 1 or more blocks along naturally 128-byte aligned addresses. This is in accordance with the allowable disconnect boundaries (ADBs) and ADB delimited quantum (ADQ) of the PCI-X specification and is true in both PCI-X and PCI modes of operation. A transaction starting and ending within the same 128-byte aligned address region will be completed in a single ADQ. A transaction that starts in one 128-byte aligned address region and ends in a different 128-byte aligned address region will be executed in two or more ADQ When a Local Bus initiator requests a new transaction, it must be capable of transferring a minimum of the lesser of the first 2 ADQ or the full transaction byte count (transactions beginning too close to an ADB cannot assert init_data_req and receive init_data_response in time to stop the transaction on the first ADB) When init_data_req is asserted, the Local Bus must respond to the request within four clocks by asserting a valid response on init_response. The init_data_req must be the direct output of a register in order for the core to meet PCI-X timing (all CorePCIX inputs should also be registered whenever possible) 16 v2.0

17 Table 13 Local Bus Initiator Interface (Continued) Port Type Function init_data_response[1:0] init_data_xfer_size_64_32_n init_wr_ack Note: Input * = port size for 64-bit CorePCIX / 32-bit CorePCIX respectively. Local bus initiator continuation response. Local Bus initiator logic must indicate a non-wait state value within four clocks of detecting init_data_req asserted to indicate the initiator's response to the current request. The init_response is encoded as follows: 00: Wait state; no response indicated; This is the default value 01: Data Transfer initiator is ready to provide data for the lesser of the entire next 128 byte block or the amount of data required to satisfy the transaction byte count 10: Disconnect at Next ADB initiator will not continue into the next block and requires a disconnect once the current block is complete 11: Reserved; must not be used Not all initiator responses may be used in all situations. User Local Bus initiator logic is required to adhere to the disconnect conditions permitted by the PCI and PCI-X Specifications Data transfer size; set for 64-bit, clear for 32-bit; indicates the size of the transaction as accepted by the PCI-X/PCI target device; this signal will always be 0 for 32-bit PCI-X/PCI cores; init_data_xfer_size_64_32_n is not valid until the target has asserted devsel_n and should only be used in conjunction with the data transfer signals (init_wr_xfer, init_rd_en); init_data_xfer_size_64_32_n is not used in conjunction with init_wr_ack; init_wr_ack always acknowledges data in the size requested by init_req_size_64_32_n Asserted during initiator write transactions when the core accepts one write data from the Local Bus; init_wr_ack is used to take data from the Local Bus but does not guarantee its transmission; init_wr_ack is not guaranteed to be continuously asserted for either PCI-X or PCI modes and may be gapped whenever the PCI core must prefetch data in preparation for a transaction start or when the target inserts a wait state; init_wr_ack always accepts data in the requested transaction size init_req_size_64_32_n init_wr_ack may be asserted for more clocks than required by the initiator byte count specified in init_attr; Local Bus logic must be designed to accommodate this without causing errors (i.e. AND init_wr_ack with ~fifo_empty, etc.) This requirement exists since it is difficult to stop init_wr_ack generation without compromising the ability to meet PCI-X timing v2.0 17

18 Table 13 Local Bus Initiator Interface (Continued) Port Type Function init_wr_xfer init_wr_last init_wr_data[63/31:0]* init_rd_en init_rd_last Note: Input * = port size for 64-bit CorePCIX / 32-bit CorePCIX respectively. Asserted if a previously accepted write data (via targ_wr_ack) transferred across the PCI-X/PCI bus; data must be accepted by the core before it is known whether the data phase containing the data will occur and complete; in order to support bursting at rate it is necessary to acknowledge data transfers on the Local Bus (so the Local Bus can immediately advance to the next value) before the transfer occurs; Local Bus initiator logic must use the end of transaction signal init_trans_end to reconcile the different amount of data acknowledged with init_wr_ack and transferred with init_wr_xfer if the Local Bus data path suffers adverse affects from having extra data consumed; There are two recommended ways to handle data recovery: For FIFOs, a convenient way to handle this discrepancy is to keep two address pointers for the Local Bus write data buffer; one pointer uses init_wr_ack and the other pointer uses init_wr_xfer; when init_trans_end is received, the pointer kept by init_wr_xfer is copied into the pointer kept by init_wr_ack; in this scheme the Local Bus must not overwrite data in the write data buffer until the data has been guaranteed to transfer via init_wr_xfer (init_wr_xfer should be used rather than init_wr_ack to alter the write FIFO level) Another option for FIFOs is to arrange their use such that the FIFO can be flushed at the end of all PCI-X transactions (init_trans_end asserted); this mechanism is simpler to implement but has reduced performance if transactions will often be disconnected before they are completed (PCI Bridge with small FIFOs; devices that frequently retry, etc.) init_wr_xfer indicates that data of size init_data_xfer_size_64_32_n transferred and may be different from the size acknowledged via init_wr_ack/init_req_size_64_32_n if the PCI-X/PCI target completes a 64-bit transaction as 32-bits Asserted coincident with the last init_wr_xfer in a transaction; this signal is useful for circuits implementing data aggregation logic from PCI-X 32/64-bit data into Local Bus 64-bit data since there is no guarantee that a target will end a transaction on a 64-bit boundary Write data; when the core asserts targ_wr_ack the current data has been accepted and the Local Bus must transition to the next data; init_wr_data must be valid from the clock following the assertion of INIT_GNT since the Local Bus cannot know when the PCI transaction will begin and the first data in conventional PCI mode must be taken from the Local Bus before init_trans_start is asserted For ease of connecting the core to FIFOs/RAM the core has been designed to accept data with a latency of 1; thus the data registered into the core is the data on init_wr_data the clock cycle immediately following a clock cycle with init_wr_ack asserted For 32-bit transactions targ_wr_data[31:0] carries the valid data and targ_wr_data[63:32] is ignored Asserted during initiator read transactions to transfer one read data of size init_data_xfer_size_64_32_n to the Local Bus; for PCI-X mode init_rd_en will be asserted continuously for the length of the transaction; for conventional PCI mode init_rd_en is not guaranteed to be continuously asserted and will be gapped whenever the target inserts a wait state; Local Bus logic must be designed to handle the more restrictive conventional PCI behavior Asserted coincident with the last init_rd_en in a transaction; this signal is useful for circuits implementing data aggregation logic from PCI-X 32/64-bit data into Local Bus 64-bit data since there is no guarantee that a target will end a transaction on a 64-bit boundary 18 v2.0

19 Table 13 Local Bus Initiator Interface (Continued) Port Type Function init_rd_be[7/3:0]* Note: * = port size for 64-bit CorePCIX / 32-bit CorePCIX respectively. Read data byte enables; generated by the core from the PCI starting address, byte count, and PCI target claimed data width; valid when init_rd_en is asserted; for 32-bit transactions (init_data_xfer_size_64_32_n = 0) init_rd_be[3:0] carries the valid byte enables and init_rd_be[7:4] is undefined; for 64-bit transactions (init_data_xfer_size_64_32_n = 1) init_rd_be[7:0] carries the data v2.0 19

20 Local Bus Initiator Operation The following section describes the operation of the local bus for initiator operations. Local Bus Initiator Burst Write Crossing an ADB in PCI-X Mode Figure 5 on page 21 illustrates Local Bus behavior for a 64-bit Local Bus initiator burst write transaction that crosses an ADB boundary when CorePCIX is operating in PCI-X mode. The target completes the transaction as a 64-bit transaction without requesting a disconnection. The transaction begins on clock cycle one when the Local Bus initiator issues init_req along with the desired command information. It is assumed that the starting address and attributes indicate a byte count that is completed with bit data transfers and that an ADB will be crossed after 10 data transfers. init_gnt is asserted with minimal timing to indicate that the transaction that was requested on clock cycle one will be attempted as soon as the PCI bus arbitration can be completed. init_trans_active is asserted on clock cycle 8 indicating to the Local Bus that the transaction has begun on the PCI bus. Also on clock cycle 8, CorePCIX begins prefetching initiator write data in preparation for placing the first several write data on the PCI bus. init_wr_data is provided to the core with a latency of one so the first write data is available on clock cycle nine. CorePCIX is not limited to begin prefetching on clock cycle eight and may begin prefetching any clock after the transaction has been granted via init_gnt. The first PCI data transfer occurs on clock cycle 11. The Local Bus is notified of the first data transfer two clocks later on clock cycle 13 via init_wr_xfer. The PCI-X core detects that an ADB is approaching and asserts init_data_req on clock cycle 14 to determine the Local Bus initiator's intentions for continuing into the next ADB. When the transaction is requested by the local bus, the first ADQ, or first two ADQ if the transaction address starts fewer than 10 transfers from an ADB, is authorized for transfer by the local bus. For transactions starting fewer than 10 transfers from an ADB, init_data_req is not asserted for the first ADB (starting the transaction indicates an implicit acceptance of at least the first two ADQ). For transactions starting fewer than 10 transfers from an ADB, init_data_req is not asserted for the first ADB (starting the transaction indicates an implicit acceptance of at least the first two ADQ). On clock cycle 17, the Local Bus initiator asserts the Data Transfer response (with maximum latency) on init_response indicating that it will guarantee that it can transfer all data in the next ADQ without requiring any wait states or a disconnect. Therefore, CorePCIX leaves pci_frame_n asserted on clock cycle 19, allowing the transaction to continue into the next ADQ. On clock cycle 21, CorePCIX deasserts pci_frame_n, since the transaction byte count will be satisfied after two more transfers. On clock cycle 24, the Local Bus is notified of the end of the PCI transaction via init_trans_end and reads the transaction status Complete on init_trans_status. This indicates the transaction was completed as requested by the Local Bus initiator. CorePCIX has received more data from the Local Bus target than it transferred across PCI. The Local Bus target must detect this condition through monitoring init_wr_ack and init_wr_xfer and correct its buffers to recover data that was acknowledged with init_wr_ack but not transferred as indicated by init_wr_xfer. If the Local Bus target data buffers can tolerate extra data being consumed (most applications except those involving FIFOs) then the Local Bus target logic does not need to monitor init_wr_xfer. The extra data read by CorePCIX is discarded when the transaction completes. 20 v2.0

21 Cycle <- ADB PCI_CLK PCI_REQn PCI_GNTn PCI_REQ64n PCI_FRAMEn PCI_IRDYn PCI_ACK64n PCI_DEVSELn PCI_TRDYn PCI_STOPn PCI_AD[63:32] PCI_AD[31:0] PCI_CBEn[7:4] PCI_CBEn[3:0] 0..0 D-1 D-3 D-5 D-7 D-9 D-11D-13 D-15 D-17 D-19D-21 D-23 ADDR ATTR D-0 D-2 D-4 D-6 D-8 D-10 D-12 D-14D-16 D-18D-20 D-22 B-1 B-3 B-5 B-7 B-9 B-11 B-13 B-15 B-17 B-19 B-21 B-23 CMD ATTR B-0 B-2 B-4 B-6 B-8 B-10 B-12 B-14 B-16 B-18 B-20 B-22 INIT_ENABLE INIT_REQ INIT_GNT INIT_REQ_SIZE_64_32_N INIT_CMD[3:0] CMD INIT_ADDR_64_32_N INIT_ADDR[63:0] INIT_ATTR[35:0] ADDR ATTR INIT_TRANS_ACTIVE INIT_TRANS_START INIT_TRANS_END INIT_TRANS_STATUS[4:0] STAT INIT_DATA_REQ INIT_RESPONSE[1:0] WAIT XFER WAIT INIT_DATA_XFER_SIZE_64_32_N INIT_WR_ACK INIT_WR_XFER INIT_WR_LAST INIT_WR_DATA[63:32] INIT_WR_DATA[31:0] D-1 D-3 D-5 D-7 D-9 D-11D-13 D-15 D-17 D-19 D-21 D-23 D-0 D-2 D-4 D-6 D-8 D-10 D-12 D-14 D-16 D-18 D-20 D-22 INIT_RD_EN INIT_RD_LAST INIT_RD_DATA[63:32] INIT_RD_DATA[31:0] INIT_RD_BE[7:4] INIT_RD_BE[3:0] Figure 5 Local Bus Initiator Burst Write Crossing an ADB in PCI-X Mode v2.0 21

22 Local Bus Initiator Burst Read Crossing an ADB in PCI-X Mode Figure 6 on page 23 illustrates Local Bus behavior for a 64-bit Local Bus initiator burst read transaction that crosses an ADB boundary when CorePCIX is operating in PCI-X mode. The target completes the transaction as a 64-bit transaction and without requesting a disconnection. The transaction begins in clock cycle one when the Local Bus initiator issues init_req along with the desired command information. It is assumed that the starting address and attributes indicate a byte count that is completed with bit data transfers and that an ADB will be crossed after 10 data transfers. init_gnt is asserted with minimal timing to indicate that the transaction that was requested on clock cycle one will be attempted as soon as the PCI bus arbitration can be completed. init_trans_active is asserted on clock cycle eight indicating to the Local Bus that the transaction has begun on the PCI bus. The first PCI data transfer occurs on clock cycle 11. The Local Bus is notified of the first data transfer two clocks later on clock cycle 13 via init_rd_en. The PCI-X core detects that an ADB is approaching and asserts init_data_req on clock cycle 14 to determine the Local Bus initiator's intentions for continuing into the next ADB. When the transaction is requested by the local bus, the first ADQ or first two ADQ if the transaction address starts fewer than 10 transfers from an ADB, is authorized for transfer by the local bus. For transactions starting fewer than 10 transfers from an ADB, init_data_req is not asserted for the first ADB (starting the transaction indicates an implicit acceptance of at least the first two ADQ). For transactions starting fewer than 10 transfers from an ADB, init_data_req is not asserted for the first ADB (starting the transaction indicates an implicit acceptance of at least the first two ADQ). On clock cycle 17 the Local Bus initiator asserts the Data Transfer response (with maximum latency) on init_response indicating that it will guarantee that it can transfer all data in the next ADQ without requiring any wait states or a disconnect. CorePCIX leaves pci_frame_n asserted on clock cycle 19, allowing the transaction to continue into the next ADQ. On clock cycle 21 CorePCIX deasserts pci_frame_n, since the transaction byte count will be satisfied after two more transfers. On clock cycle 24, the Local Bus is notified of the end of the PCI transaction via init_trans_end and reads the transaction status Complete on init_trans_status, indicating the transaction completed as requested by the Local Bus initiator. 22 v2.0