Configurable Fault Tolerant Processor (CFTP) for Space Based Applications

Transcription

1 Error Interrupt Status & I/O Memory Control Clock Control Interface/switching logic Configuration Control Interface/switching (GLUE) logic EDAC TMR PRLOS PRLOS Command and Status Registers Bus Transceivers FPGA 2 µp µp µp voter Configuration Memory Naval Postgraduate School FPGA 1 Memory RLOS Configurable Fault Tolerant Processor (CFTP) for Space Based Applications Presented by Capt Charles Hulme, USMC With Dr. Alan A. Ross Naval Postgraduate School 777 Dyer Rd., Code (SP) Monterey, CA 93943

2 Agenda Introduction Components Architecture Configuration Testing Small Satellite Conference 2

3 CFTP Objective Design a fault-tolerant reconfigurable System-On-a-Chip (SOC) to mitigate bit errors in computation for evaluation onorbit Evaluate techniques for configuration protection Small Satellite Conference 3

4 CFTP Concept CFTP is centered on a reconfigurable Triple Modular Redundant (TMR) SOC that will overcome transient errors without full system resets and the commensurate loss of data The flexibility of this design will enable on-orbit reconfigurations to the on-board architecture supporting dynamic mission requirements Reducing development time and cost Improving reliability in hardware Increasing flexibility and upgradeability Small Satellite Conference 4

5 Motivation Current processors require radiation hardened (RADHARD), custom built, inflexible systems. RADHARD parts lag current technology and are years old by the time of launch Space systems development times are long with designs frozen early in the process Upgrading to newer technologies difficult Space systems are often replenished for years without significant design changes (e.g. GPS) CFTP can provide updateable architectures for backwards and forward compatibility between systems via reconfiguration Small Satellite Conference 5

6 Space Application Once a satellite is in orbit, hardware changes are expensive, if even possible. If reconfigurable logic can be used instead, then changes can be made via command and control communications, vice a personal visit. CFTP can be reconfigured on orbit to correct errors, meet dynamic mission requirements, upgrade, or serve as back-up devices to several on-board systems. Small Satellite Conference 6

7 Effects of Radiation Total Ionizing Dose (TID) Single Event Effects (SEE) Single Event Latchup (SEL) Can be destructive Single Event Upset (SEU) Can be mitigated Many Others Small Satellite Conference 7

8 Conceptual framework FPGA implementation of TMR softcore microprocessors SOC design 16 or 32 bit softcore microprocessors Maximize use of COTS products Or at least provide COTS-like functionality Maximize system speed and reliability Minimize component cost and power consumption Introduce real time on-orbit orbit reconfigurability Small Satellite Conference 8

9 Physical Framework Size 5.3 in x 7.3 in PC-104 Bus Bus interface PC/104 Reconfigurability Cornerstone of the research, using an FPGA Reliability COTS hardware preferred COTS performance targeted Low Power Target 11 Watts or less, max Small Satellite Conference 9

10 The CFTP Concept Error Interrupt Clock Control FPGA 2 Configurable Processor Configuration Controller µp µp µp voter EDAC TMR PRLOS Status & I/O Interface/switching logic FPGA 1 Memory Control PRLOS Memory Configuration Memory System Memory Configuration memory Configuration Control Command and Status Registers Interface/switching (GLUE) logic RLOS PC/104 Bus Bus Transceivers Small Satellite Conference 10

11 Fault-Tolerant Architecture Error Interrupt Clock Control FPGA 2 µ P µ P voter EDAC ADDRESS DATA System Memory CONTROL Status & I/O µpp TMR PRLOS Interface/switching logic Small Satellite Conference 11

12 CFTP Components SOC Processor Xilinx XQVR600-4 CB228 FPGA Xilinx XQV600-4 CB228 FPGA 661,111 system gates 228 pins (162 I/O pins) Controller XQVR600-4 CB228 FPGA XQV600-4 CB228 FPGA Small Satellite Conference 12

13 CFTP Components Configuration storage for both FPGAs Flash Memory (EEPROM) µprocessor Intel TE28F320C3 32 Mbit EPROM Configuration Controller Xilinx XC18V04 ISP PROM Development ROM Configuration Controller Xilinx XQR17V16 OTP SPROM Flight Small Satellite Conference 13

14 CFTP Components System Memory RAM SDRAM: Elpida (Hitachi) HM BTT Mbit, 16.7M-word x 4bit x 4bank, 3.3 V Small Satellite Conference 14

15 Putting it all together Small Satellite Conference 15

16 Primary Data Paths X X X Configuration Data Data Control Address Small Satellite Conference 16

17 Additional Data Paths Theses paths exist for additional adhoc storage for the µprocessor These paths exist for additional adhoc communications between FPGAs Small Satellite Conference 17

18 Current Project Status 2 Prototypes Manifested on LEO Midshipman Space Technologies Applications Research (MidSTAR-1) Naval Postgraduate School Satellite (NPSAT1) Seeking High-Radiation Orbit MidStar-1 NPSat1 SPACE TEST PROGRAM (STP-1), ATLAS V LAUNCH VEHICLE, Est Launch March 2006 Small Satellite Conference 18

19 Required Tests Development Tests Hardware Functionality Tests Operational Tests Environmental Tests Small Satellite Conference 19

20 Development Tests Verify Physical performance Electrical performance Stuck-at Faults, Bridge Faults, etc.. Small Satellite Conference 20

21 Hardware Functionality Tests Confirm Functionality with FPGAs ROM RAM EEPROM PC104 Bus Error Interrupt Status & I/O µp µp µp FPGA 2 Clock Control EDAC voter TMR PRLOS Interface/switching logic FPGA 1 Memory Control PRLOS Memory Configuration Memory Configuration Control RLOS Command and Status Registers Interface/switching (GLUE) logic Bus Transceivers Small Satellite Conference 21

22 voter Operational Tests Evaluate missions µp TMR Design Built-In Self Test Triple Modular Redundancy Reconfiguration µp EDAC memory µp Status I/O Small Satellite Conference 22

23 Environmental Tests Launch Environment Testing Random Vibration Testing Simulates vibrations on Spacecraft due to Launch Vehicle On-Orbit Environment Testing Thermal Vacuum Testing Verifies proper operation of Spacecraft under simulated space vacuum and temperature Radiation Tests Evaluate susceptibility to SEUs and Total Dose Tolerance Small Satellite Conference 23

24 Conclusions The design provides maximum flexibility Allows for redundant reconfiguration methods Provides for configuration error mitigation Provides numerous options for future configurations with multiple data paths through the configurable logic Provides a fault-tolerant architecture for SEU mitigation Small Satellite Conference 24

25 Questions? Small Satellite Conference 25

26 Error Interrupt Status & I/O Memory Control Clock Control Interface/switching logic Configuration Control Interface/switching (GLUE) logic EDAC TMR PRLOS PRLOS Command and Status Registers Bus Transceivers FPGA 2 µp µp µp voter Configuration Memory Naval Postgraduate School FPGA 1 Memory RLOS BACK-UP Presented by SLIDES Naval Postgraduate School 777 Dyer Rd., Code (SP) Monterey, CA 93943

27 Radiation Environment Galactic Cosmic Rays Solar Wind Solar Protons & Heavier Ions Trapped Particles Nikkei Science, Inc. of Japan, by K. Endo Small Satellite Conference 27

28 FPGA Description A Field Programmable Gate Array (FPGA) is a high density Programmable Logic Device (PLD) Built of small logic blocks in a sea of interconnects Each logic block can emulate a digital circuit Small Satellite Conference 28

29 FPGA Description (cont) If the circuit is large, smaller portions are instantiated in separate logic blocks and interconnected This allows for implementation of complex digital circuits such as microprocessors An FPGA is reconfigurable, which means it can be erased and rewritten with new designs The configuration is data Small Satellite Conference 29

30 Soft-Core Description A soft-core is a software expression in HDL of a hardware design It is typically a slower design than the hardwired version But it is not permanently wired Small Satellite Conference 30

31 FPGA/Soft-core (cont) Combining these two technologies, (softcore and FPGA), the capability exists to implement a soft-core processor in an environment where reconfiguring hardwired systems is difficult Thus introducing COTS like performance in a non-cots device Small Satellite Conference 31

32 Design Considerations Radiation induced Errors Can occur in the data as it is processed Can occur in the configuration of the FPGA Can occur in memory Mitigation Strategies Avoid if possible Parts selection If/when they occur, reduce their impact Use of TMR Use of EDAC Use of background reconfiguration Small Satellite Conference 32

33 Design Considerations Configuration errors FPGAs can self-correct configuration errors Some errors may still slip through CFTP design is intended for frequent reconfiguration, correcting configuration errors is important. Configuration errors corrected in background through readback/reconfiguration process I/O Errors FPGAs have a large number of I/O pins Voting each input and output is costly and complex Small Satellite Conference 33

34 Configuration Methods Master Slave Serial Mode Default Load for the Configuration Controller Configuration Control FPGA (X1) MODE 0/1/ SPROM MASTER Configurable Processor FPGA (X2) DATA DIN 2 MODE 0/1/2 1 CCLK CE OE/ RESET CF 3 CONFIG_CLK 1 DONE 1 INIT 2 PROGRAM 1 DOUT/BUSY 2 DIN 2 SLAVE CONFIG_CLK 1 DONE 1 INIT 1 1 These are dedicated pins PROGRAM 1 2 These standard configuration pins that revert to I/O pins post-configuration 3 CF specific to XC18V04 ISP PROMS. Red connection must be made during test and evaluation Small Satellite Conference 34

35 Configuration Methods SelectMAP Mode Default for Configurable Processor FASH ADDRESS FLASH CONTROL FASH DATA Flash Memory Controller soft core MODE 0/1/2 1 SelectMAP Controller soft core MODE 0/1/2 2 USER I/O_DATA[7:0] USER I/O_DONE USER I/O_INIT USER I/O_BUSY USER I/O_CS USER I/O_WRITE D[7:0] 2 DONE 1 INIT 2 DOUT/BUSY 2 CS 2 WRITE 2 PROGRAM 1 PROGRAM 1 USER I/O_CONFIG_CLK Configuration Control FPGA (X1)** OSCILLATOR CONFIG_CLK 1 Configurable Processor FPGA (X2)** ** X1 or X2 can serve as the Flash memory and SelectMAP controller, as all required physical connections exist. 1 These are dedicated pins 2 These are user I/O pins configured to drive the SelectMAP mode Small Satellite Conference 35

36 Configuration Methods JTAG/Boundary Scan This layout uses inherent JTAG functionality to waterfall load, or selectively load (using the JTAG Header), the configurable components. PROM_JTAG_TDO X1_JTAG_TDI X1_JTAG_TDO X2_JTAG_TDI X2_JTAG_TDO TMS TCK TDI JTAG JUMPER JTAG_TMS JTAG_TCK PROM_JTAG_TDI SPROM JTAG_TMS 1 JTAG_TCK 1 PROM_JTAG_TDI 1 Configuration Control FPGA (X1) MODE 0/1/ Configurable Processor FPGA (X2) MODE 0/1/ PROM_JTAG_TDO 1 X1_JTAG_TDI 1 JTAG_TCK 1 JTAG_TMS 1 X1_JTAG_TDO 1 X2_JTAG_TDI 1 JTAG_TCK 1 JTAG_TMS 1 X2_JTAG_TDO 1 1 These are dedicated JTAG pins Arc represents optional connections for JTAG Daisy Chain Small Satellite Conference 36

37 Configuration Methods Self-Scrubbing JTAG Configuration Control FPGA (X1) X1_MODE 0/1/ MODE 0/1/2 1 X1_JTAG_TDO 2 JTAG_TMS 2 JTAG_TCK 2 X1_JTAG_TDI 2 JTAG Controller soft core X1_JTAG_TDI 1 JTAG_TCK 1 JTAG_TMS 1 X1_JTAG_TDO 1 1 These are dedicated pins 2 These are user I/O pins configured as JTAG controller pins Small Satellite Conference 37

38 Configuration Methods JTAG Loading the other FPGA Configuration Control FPGA (X1) Configurable Processor FPGA (X2) MODE 0/1/ X2_MODE 0/1/ MODE 0/1/2 1 X1_JTAG_TDO 2 JTAG_TMS 2 JTAG_TCK 2 JTAG Controller soft core X1_JTAG_TDI 2 X1_MODE 0/1/2 2 X1_JTAG_TDI 1 X1_JTAG_TDI 1 JTAG_TCK 1 JTAG_TCK 1 JTAG_TMS 1 X1_JTAG_TDO 1 JTAG_TMS 1 X1_JTAG_TDO 1 When JTAG daisy chain used, eliminate green connections and make blue connections 1 These are dedicated pins 2 These are user I/O pins configured to drive JTAG mode Small Satellite Conference 38