Building Reliable High-Performance Hardware. Fraunhofer FOKUS. Fraunhofer FOKUS
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1 Fraunhofer Institute for Open Communication Systems Kaiserin-Augusta-Allee Berlin, Germany 1 Building Reliable High-Performance Hardware Friedrich Schön System Quality Center München 2 1
2 FOKUS System Quality Center History and Mission Merger of 3 Fraunhofer Institues in Berlin 1. July 2012 FIRST Computer Architecture and Software Technology ISST Software and System Technology FOKUS Open Communication Systems COTS based OBC for space For more than 10 years Last launch wasobc on TET OOV July Architectural Solutions in different Domains AUTOSAR IMA SAVOIR 4 2
3 OBC-SA: From Motivation to OMAC4S Get rid of antiquated burdens! Keep it smart and simple (KISS) Make use of Standards from other domains! Make use of Technologies which are successfully applied in other domains! Provide interfaces for Backwards Compatibility Make architecture specifications available to public 5 OMAC4S framework based on the CompactI Serial standard 6 3
4 MUSE & OBC-SA Introduction Why multi-core in the space domain? High performance, low power Improved flexibility through programmability Redundant resources for fault-tolerance Uses cases: Intelligent descent and landing Docking maneuvers Formation flying Large antennae arrays 7 Multi-Core: Forecast Source: ITRS
5 MUSE & OBC-SA Processor Criteria for selection of processor (in 2010!): Silicon-On-Insulator (SOI) technology High performance multicore Modern I/O and memory interfaces Power saving capabilities Long-term availability Power QorIQ P4080 eight-core 9 Pre-Qualification (irradiation) Proton Irradiation facility Injector Cyclotron JULIC Temperature Energies 23 ±1 C 35, 31.5, 27, 25 and 22 MeV (achieved with Aluminum degraders) SEU probabilities for 550 km circular orbit proton-induced SEU rates with SPENVIS under worst case conditions Gamma Irradiation Irradiation source TK1000B Co-60 gamma radiation with mean energy of 1.25MeV Nominal activity 15.8 TBq(401 Ci) at Dose steps 15 krad(si) 1 Irradiation Step
6 RJ 45 Debug JTAG MicroSD RS-232 CON RS-232 CON Magnetics 1Gb-Ethernet RS-232 RS-232 IeX4 IeX4 1 Gb-Ethernet XAUI n x spare SERDES SMBus SGPIO control/state n x spare LVDS Architecture Redundancy and I/O Structure 11 OBC-SA P4080 CPU-Board Freescale P4080, 1.2 GHz, 8-core 32 Bit processor PICMG CI-S.O CompactI Serial compliant board Up to 4 GB DDR3 DRAM, ECC 32 Mbyte redundant NOR Flash 4 GB NAND Flash + microsd card slot (Front) Rear I/O: 3 x le, 2 x Gb Ethernet Front I/O: 1 x Gb Ethernet, 2 x RS 485 Effective SEU mitigation Fully self-checking node design Radiation tolerant system (TMR implementation) Ethernet Independent hardware watchdog (system ) 2 GB DDR3 SDRAM DDR SDRAM + ECC ECC FREESCALE P4080 Fast Worker/Monitor node switch (system ) Test CPU Monitor Monitor Power Conversion Housekeeping Clock NOR Flash Radiation tolerant elbc NAN D Flash ci serial connector Board Support Package (BSP) and PikeOS operating system Support for SMP Linux Proton irradiations with energies between 22 and 35 MeV Co-60 gamma irradiations at the Gammamat TK1000B 6-12 V P C 12 6
7 OBC-SA I/OBoard Flexible interface configuration by separate I/O node IP based implementation Radiation tolerant with TMR logic (Xilinx Virtex-5) Synchronization and voting unit (TMR) for reliable control output Backplane Interfaces: 3 x I Express x4 2 x Gbit TTEthernet 2 x SpaceWire 1 x Gbit Ethernet Front Interfaces: 2 x SpaceWire 1 x RS 485 for test and debug 1 x RS 485 for reliable control output 13 Fault Tolerant P4080 Multi-Core based High Performance System Computing System 7_PE 7_ETH Sys Slot 5_ETH 8_ETH 1_SPL 1_SPL I/O Node 2_SPL... 2_SPL... 1_SPL 1_SPL 2_SPL 1_SPL 2_SPL 1_PE 8_ETH 1_SPL SPW/ TTTech Router1 SPW/ TTTech Router2 5_PE 6_ETH 1_PE 1_PE 1_SPL Node1 1_SPL 8_ETH 1_PE 2_SPL 1_ETH IO(3-01) 2_ETH IO(2-08) 1_SPL Node2 6_ETH IO(5-05) 6_ETH IO(5-04) ci Serial Backplane SMB / GPIO INC Ie x2x4 10G ETH OBC-SA High Performance Computing System ETH 100/1000 XAUI TTTech ETH SPW Redundant Routers 14 7
8 FDIR Concept: Hardware Error Detection and Error Handling System level 1oo2d system Multi-Core P4080 Redundant computations Caches EDC (L3) and Parity (L1, L2) Node memory Redundant memory banks with EDC Flash memory Redundant copies with CRC Radiation tolerant (TMR) Control output Synchronizing Voter () Hardware watch-dog for unspecific errors in HW or SW Dual Node (Worker/Monitor) concept Node-Switch for all errors not handled within the nodes 15 FDIR Concept: System Software Process- and task level redundancy: Computational intensive: No redundancy (plausibility check) Mission critical: Dual mode redundancy (compare and restart) Mission critical and real-time: Triple mode redundancy (synchronized voting) Diagnoses tasks for self checking of the nodes Hardware watchdog for heartbeat control: Diagnoses- and application tasks Supervisor process (replicated) Supervisor process Re-triggers hardware watchdog (TMR logic) Dual node concept (Worker/Monitor) Node-switch is triggered by RESET of the Worker Node Software RESET for all detected errors not handled locally in the node, Hardware RESET by watchdog timeout, power or temperature problems Outage time can be optimized by continuously sending actual state information to the monitor node (task-specific) 16 8
9 Cam1 Cam2 Dataflow Structure MoonDetect 1 MoonDetect 2 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 parallelized and dual redundant C 2 C 3 C 4 C 6 C 7 C 8 Consolidate C 2 Consolidate C 3 Consolidate C 6 triple redundant HW Watchdog Output C 7 ELB HW Voter Safety Critical Control Output EDC shared memory 17 Cam1 Cam2 MoonDetect 1 MoonDetect 2 Safety Concepts Fault Isolation C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 2 C 3 C 4 C 6 C 7 C 8 Modularization Partitioning Consolidate C 2 Consolidate C 3 Consolidate C 6 HW Watchdog Output C 7 ELB HW Voter Safety Critical Control Output EDC shared memory 18 9
10 Plausibility checks Cam1 Cam2 MoonDetect 1 MoonDetect 2 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 Safety Concepts Fault Detection C 2 C 3 C 4 C 6 C 7 C 8 Consolidate C 2 Consolidate C 3 Consolidate C 6 Secured protocols HW Watchdog Output C 7 ELB HW Voter Voting Safety Critical Control Output EDC shared memory 19 Cam1 Cam2 Supervisor MoonDetect 1 MoonDetect 2 monitor C 2 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 Supervisor worker C 1 C 2 C 3 C 4 C 6 C 7 C 8 Safety Concepts Fault Detection Timeout Monitoring Hardware Watchdog Consolidate C 2 Consolidate C 3 Consolidate C 6 Heartbeats Heartbeat re-triggering HW Watchdog Output C 7 ELB HW Voter Safety Critical Control Output EDC shared memory 20 10
11 Plausibility Checks on Redundant Results Cam1 Cam2 MoonDetect 1 MoonDetect 2 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 Safety Concepts Fault Recovery C 2 C 3 C 4 C 6 C 7 C 8 Check Point / Restart Node Switch Consolidate C 2 Consolidate C 3 Consolidate C 6 HW Watchdog Output C 7 ELB HW Voter Voting Safety Critical Control Output EDC shared memory 21 FDIR Concept: Application Software Double redundancy supervisor process: worker/monitor Fault recognition: Each processes through heartbeats Plausibility check Whole board through heartbeats Fault correction: restart process, restart board Triple redundancy in data path Modularity: Fine granular fault-tolerance Partitioning: memory protection 22 11
12 OBC-SA Demonstrator System Redundancy Concept System Compact I serial 3U Rack P4080 Processing Node 1 I/O Node P4080 Compact I Processing Node serial 2 Backplane 23 Next steps to TRL 6 improvement High Reliability semiconductor for Space Applications e.g E2V P4080, rugged Memory, B. Conductive Cooled Design Thermal vacuum qualification Measurement at high proton energies (up to 250 MeV) 24 12
13 Architecture 4 Space Summary Interest in multi-core architectures for space Eight-core P4080 processor selected, SOI COTS based redundant boards worker-monitor system radiation-hardened s Multiple, configurable layers of fault-tolerance in system-software Open Modular Architecture based on CompactI Serial Demonstrator available 25 Q&A?! 26 13
14 Contact Fraunhofer Institute for Open Communication Systems FOKUS Kaiserin-Augusta-Allee Berlin, Germany Tel. +49 (30) Fax +49 (30) Competence Center for System Quality Engineering Friedrich Schön Tel. +49 (30)
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