Dynamically Reconfigurable Processing Module (DRPM), Application on Instruments and Qualification of FPGA Package

Transcription

1 INSTITUTE OF COMPUTER AND NETWORK ENGINEERING Dynamically Reconfigurable Processing Module (DRPM), Application on Instruments and Qualification of FPGA Package Björn Fiethe, Frank Bubenhagen, Tobias Lange, Harald Michalik, Holger Michel, Wafy Nayif INSTITUTE OF COMPUTER AND NETWORK ENGINEERING

2 Outline 1. Heritage of FPGAs in Scientific Space Instruments 2. Dynamically Reconfigurable Processing Module (DRPM) 3. Application on Solar Orbiter PHI Instrument 4. Application on Proba-3 ASPIICS Instrument 5. System-on-Chip (SoC) Solution for DPUs 6. Virtex-4 FPGA CF1140 Package Assembly Qualification 7. Conclusion Page 2

3 On-Board Data Processing Unit (DPU) Heritage Based on Xilinx SRAM FPGAs: First European System-on-Chip Computer in Space Proven solution for scientific space instruments if appropriate mitigation techniques against radiation effects are applied High flexibility, but reconfigurability has only been used in development phase (VMC, DawnFC) NO support for dynamic in-flight reconfiguration VMC operational since 6 years with only a few numbers of predicted reboots due to SEE Availability Venus Montoring Camera (VMC) Dawn Framing Camera (DawnFC) Page 3

4 Implementation of CCSDS 122 IDC on space-qualified FPGA One RTAX2000S FPGA: Property Proba-V EnMAP Resource Proba-V EnMAP lossy/lossless both lossless R-cell 7125(66%) 7620(71%) image line size 1024 or C-cell 8455(39%) 9772(45%) tile size 408x x128 total cells 15580(48%) 17392(54%) segment size block RAMs 54/64 58/64 bit-depth frequency (MHz) in/out bus width 12 8 throughput (Mbits/s) Mbit/s@66MHz clock frequency ~ 14 Mpix/s@12bit/pix Page 4

5 Dynamically Reconfigurable Processing Module (DRPM) Demonstrator for Dynamic Reconfigurable Processing Module (DRPM) is currently in development and validation under ESA contract Primary objective of study is to provide development environment demonstrating feasibility of reconfigurable FPGA technology for flight programs Modules of demonstrator platform are equipped with devices and interfaces also available in space qualified versions Page 5

6 DRPM Architecture Modular concept: System Controller (Overall system control and supervision) SpaceWire Router (Sub-module interconnection and expandability) Dynamically reconfigurable FPGA (DFPGA) module (Processing unit) Processing capacity scalable by addition of further DFPGA modules Redundancy by addition of DFPGA modules with identical functionality Page 6

7 DRPM Demonstrator Hardware Page 7

8 Polarimetric and Helioseismic Imager (PHI) Instrument SO/PHI will probe the solar interior and provide maps of the continuum intensity, the magnetic field vector and the line-of-sight velocity in the solar photosphere Two Active Pixel Sensors (APS) with pixel each Dedicated Image Stabilization System (ISS) Acquisition of one set of images containing 24 observables every minute at each detector 2x Mbit/s Parallel real-time processing not achievable due to limited power and thermal resources Unused module resident in FPGA wastes power, resource utilization and costs Dynamic reconfiguration allows flexible use of FPGAs for Time Space Partitioning Acquired data have to be stored in memory until FPGAs are reconfigured Page 8

9 Application of DRPM on SO/PHI Page 9

10 Dynamic Reconfiguration for Time Space Partitioning (TSP) 1. Dedicated configuration for image data acquisition: Image stabilization system (ISS) in FPGA #1 Data accumulation in FPGA #2 Page 10

11 Dynamic Reconfiguration for Time Space Partitioning (TSP) 2. Different configuration for subsequent data processing: RTE inversion in FPGA #1 Data pre-processing in FPGA #2 Page 11

12 SO/PHI DPU Prototype Development from DRPM Prototype of the Solar Orbiter DPU: Fully capable to demonstrate dynamic reconfiguration approach Based on DRPM study demonstrator Baseboard with flash-based Microsemi FPGA as prototype for RTAX Xilinx Virtex-4 SX55 FPGA + local memory Front panel to support all internal and external DPU interfaces Available, HW verified Successful interface and full functional tests with other breadboard units Page 12

13 SO/PHI DPU EQM Development Page 13

14 Application of DRPM on Proba-3 ASPIICS (Association de Satellites Pour l Imagerie et l Interférométrie de la Couronne Solaire) Page 14

15 System-on-Chip (SoC) Solution Reconfigurable GP-Processor is prefect SoC solution for single board DPUs: Atmel ATF697FF: LEON2-FT fast enough, but FPGA area much too small Microsemi SmartFusion2: Full SoC solution, ARM Cortex-M3, not FT, not rad-tolerant Xilinx Virtex-4: Dual PowerPC, external configuration, not FT, too powerful(?) Xilinx Zynq-7000: Full SoC solution, Dual-Core ARM Cortex-A9, availability?? Page 15

16 Virtex-4 FPGA CF1140 Package Assembly Qualification Currently no qualified process manufacturer available in Europe Mission specific assembly qualification: Based on general requirements according to ECSS-Q-ST-70-38C and TEC-QT/2009/1059/CV Mission specific adaptations, qualification levels and acceleration factor Double-tracked approach: 1. Soldering: Using same process already qualified for military application 2. Optional non-soldering socket: Flexible connection, e.g. spring probe Reliable interface with no solder joints Qualified for military applications Shock and vibration to 25 Gs with no disconnect Consistent resistance over extreme temperature ranges Additional thermal strap to structure to ensure good conductivity Page 16

17 Virtex-4 FPGA CF1140 Package Assembly Qualification Manufacturing and assembly of completely representative PCB and mounting frame Daisy-chain packages for probing of all connections Repair process will not be used No qualification of repair process Detailed qualification plan available Page 17

18 Virtex-4 FPGA CF1140 Package Assembly Qualification Main Failure Model: Solder joint fatigue on the solder joints due to coefficients of thermal expansion (CTE) mismatch Modified Coffin-Manson: 1.9 AA = T 1 L f 3 M T M f L Number of boards: EEE T M 1 T L Up to 4 internal capability samples to optimize assembly and soldering 4 qualification test boards Microsection of one board after mission specific thermal cycling Continuing thermal cycling with 3 boards until first error to provide better statistics Microsection of failed board Page 18

19 Conclusion Dynamic approach is much more favorable within very tight power and thermal constraints of space science missions First European application of dynamic reconfiguration of FPGAs for scientific space instrument In-flight adaptive hardware enhances the system with adaptive functionality on demand and significant operational flexibility Major maintenance and performance improvement Data integrity must be guaranteed and mitigation techniques against SEU induced errors have to be applied Perfect System-on-Chip (SoC) solution for DPUs still to come Mission specific Virtex-4 FPGA CF1140 package assembly qualification started Page 19

20 THANK YOU FOR YOUR ATTENTION! Questions? Page 20