MAG3110 Frequently Asked Questions

Transcription

1 Freescale Semiconductor Frequently Asked Questions Document Number: Rev 1, 05/2012 MAG3110 Frequently Asked Questions Applications Collateral for the MAG3110 to Aid Customer Questions Data Sheet, Fact Sheet, User s Guide MAG3110 MAG3110FS MAG3110UG Application Notes AN4246: Calibrating an ecompass in the Presence of Hard and Soft-Iron Interference AN4247: Layout Recommendations for PCBs Using a Magnetometer Sensor AN4248: Implementing a Tilt-Compensated ecompass using Accelerometer and Magnetometer AN4249: Accuracy of Angle Estimation in ecompass and 3D Pointer Applications Software and Tools LFSTBEB3110: Sensor Toolbox board for MAG3110 Videos Freescale Xtrinsic MAG3110 Magnetometer for Consumer Applications Freescale Xtrinsic MAG3110 Magnetometer 3D Pointer and ecompass Freescale Semiconductor, Inc. All rights reserved.

2 Technical FAQs Q: What is the maximum bus speed for the I 2 C? A: I 2 C is rated up to 400 khz (Fast Mode) communications. Anything above this has not been verified at the moment. Q: What are the I 2 C device address options for the device? A: 7-bit I 2 C address is fixed as 0x0E. Shift in 0b for Write and 1b for Read Write(0x1C) // for I 2 C Address 0x0E Read(0x1D) // for I 2 C Address 0x0E Q: I am having a problem communicating with the device. MAG3110 is not acknowledging any I 2 C requests. Am I missing something? A: Some alpha versions of silicon had I 2 C addresses of 0x1D and 0x1C. If you requested samples during this preproduction period, your device may not have an I 2 C address of 0x0E. You can try communicating with MAG3110 using the above-mentioned addresses. We recommend you request the most recent samples and obtain the latest documentation through our website since the latest revision silicon contains fixes to the alpha errata. Q: I am having a problem communicating with the device. There seems to be a bus collision. SDA and/or SCL stay low. Am I missing something? A: I 2 C read operations, whether it is a BURST read or SINGLE read, must be terminated by a NACK (the MASTER must leave SDA floating at the end of the last byte read desired) by the MASTER. Failing to do so will cause unwanted behavior. Q: Does the MAG3110 work with SPI communication? A: No. Q: What is the DR_STATUS register for? How are the Data Ready (DR) bits cleared? A: The DR_STATUS register contains bits for indicating new data on each of the data registers for the three axes (ZDR, YDR, XDR) plus ZYXDR bit that is a logical OR of ZDR, YDR and XDR bits. The register also contains bits for indicating an overwrite (OW) condition of the data registers for each axis (ZOW, YOW, XOW) plus a ZYXOW bit that is a logical OR of ZOW, YOW and XOW bits. The DR bits can be cleared by reading the MSB of magnetic data register of the particular axis. This will also clear the corresponding OW bit. Q: The data in registers OUT_Y and OUT_Z are not updating. Am I missing something? OUT_X_MSB should be read first so that the data in registers OUT_X_LSB through OUT_Z_LSB is updated. Q: What does the FR (fast-read selection) bit do in CTRL_REG1? A: By setting the FR bit, the user can make MAG3110 auto-increment the I 2 C address so that the LSB locations are skipped during a burst I 2 C read operation. 2 Freescale Semiconductor

3 Q: What are the offset registers (reg0x09 reg0x0e) used for? A: Offset registers are to correct for offset shifts that may happen after the PCB population of MAG3110. By using 2 s complement numbers, users can zero-out these unwanted shifts that are reflected in the corresponding data registers (registers 0x01 0x06). Q: Can you connect the MAG3110 pin 3 which says NC to VDD or to GND? A: This pin is recommended to be left floating. Connecting the pin to VDD or GND may cause malfunction. Q: What is the input voltage range for the device? A: The analog supply voltage (VDD) is 1.95V to 3.6V and the digital supply (VDDIO) ranges from 1.62V to VDD. Note: Please see the errata for your particular version of silicon. Q: What is the bandwidth at the different selectable ODRs? A: Bandwidth is defined as half the data rate. Maximum bandwidth is expected to be 40 Hz typical, but may vary due to ODR variations. Refer to the data sheet. Q: What is the expected duration for the part to go from OFF to Standby Mode? A: A typical startup sequence takes about 1.64 ms. INT1 pin can be monitored to detect the end of startup sequence. During startup, INT1 first goes high and then low indicating end of startup. Q: What is the expected duration for the part to go from Standby to Active Mode? A: 2/ODR + 1 ms. With ODR, 80 Hz ~25 ms. Q: What is the expected duration for the part to go from Active to Standby Mode? A: Once clearing the AC bit in CTRL_REG1 it can take MAG3110 up to roughly t = 1/ODR to transition from Active to Standby mode. (The maximum delay can be up to ~12 seconds). This is important because once the AC bit is cleared, changes made to ODR and OSR settings in CTRL_REG1 will be ignored if AC bit is set again before the part fully transitions into Standby mode. Q: I am having a hard time switching between different OSR/ODR settings. CTRL_REG1 does not seem to update after a I 2 C write. What is happening? A: To switch between different OSR/ODR settings, MAG3110 first must be put back into Standby Mode. Once the part fully transitions into Standby Mode it can be put into Active Mode with new OSR/ODR settings. Q: What is the sensitivity of the part? A: 0.1 μt/lsb. Please refer to the data sheet Q: How precise is the temperature sensor on MAG3110? A: Per specification, MAG3110 has ±1 C repeatability. Q: The temperature measurement seems way off. What am I doing wrong? A: Nothing. The temperature output for MAG3110 is not trimmed for offset so the readings will be off. You can correct the offset in software. Sensitivity is OK. Freescale Semiconductor 3

4 Q: The magnetic data I am reading seems way off from what it used to be. Is the part damaged? What am I doing wrong? A: When exposed to strong magnetic fields, the sensing element may get magnetically contaminated. MAG3110 has a reset mechanism to get rid of the effects of this exposure. It is recommended that CTRL_REG2 bit 7 (AUTO_MRST_EN) be set in the initialization routines of your application before starting to acquire any measurements. Q: Can you describe the Active Mode and Standby Mode? What does the TM bit do in CTRL_REG1? A: In Active mode, the device will keep acquiring data continuously according to settings in CTRL_REG1 (CTRL_REG1 = 0bXXXXXX01). In this case (See the next question.) it is possible to synchronize with the acquisition rate via the INT1 pin. In Standby mode, the part is in a low-power state and no data acquisition is taking place. The part defaults to Standby mode upon power-up (AC = TM = 0). Set the TM bit when you want the part to acquire only one sample on each axis. See the following table for details. AC TM Description 0 0 ASIC is in low-power standby mode. 0 1 The ASIC shall exit standby mode, perform one measurement cycle based on the programmed ODR and OSR setting, update the I 2 C data registers, and re-enter standby mode. 1 0 The ASIC shall perform continuous measurements based on the current OSR and ODR settings. 1 1 The ASIC shall continue current measurement at fastest applicable ODR for programmed OSR. The ASIC shall return to programmed ODR after completing the triggered measurement. Q: How do I know that new data is ready to be read on a particular axis in Active mode? How can we synchronize with MAG3110 and minimize overhead I 2 C instructions? A: The DR register has flags (bits) for indicating if there is new data ready on a particular axis. The user application can poll these registers to detect new data. However, a more efficient method exists; if any of the three DR flags (ZDR, YDR, XDR) in CTRL_REG1 is set (by the ASIC upon new data acquisition), the ZYXDR bit will also be set. INT1 pin logically follows the state of the ZYXDR bit. The user application can utilize the INT1 pin to synchronize with MAG3110 as follows: 1. Put MAG3110 in Active mode (CTRL_REG1 = 0bXXXXXX01). 2. Wait on INT1 to go high. 3. Read at least one MSB from any of the three data registers. (This will clear INT1.) 4. Go back to Step 2. Q: How do I clear the interrupt pin / ZYXDR flag? A: Interrupt pin / ZYXDR is cleared by reading the MSB (most-significant byte) from any one of the three magnetic data registers. Q: What are hard-iron effects? How do we compensate for them? A: Hard-iron effects are magnetic-interference effects that are due to materials which have permanent magnetism. Such effects can be detected as offset shifts in one or more of the axes and through mathematical algorithms be compensated for. See above-mentioned application notes for details. 4 Freescale Semiconductor

5 Q: What are soft-iron effects? How do we compensate for them? A: Soft-iron effects are magnetic-interference effects that are due to materials which have no permanent magnetization, but become magnetized when an external field is applied (materials that have high magnetic permeability, such as non-magnetized iron). Such effects can be detected as a distortion of the magnetic vector throughout 3D space and compensated for through mathematical algorithms. See abovementioned application notes for details. Q: What is the total time it takes the MCU to make a single byte read out of MAG3110? A: Please refer to the I 2 C command format in the design specification. If the I 2 C is running at 400 khz, the AK is one cycle period (2.5 μs). For a single byte read, it requires 4 x 9 bits time (= 36 x 2.5 μs = 90 μs) + START, Repeat START and STOP condition times (minimum 0.6 μs each in the I 2 C specification by Philips) times. Thus it requires a total of 91.8 μs minimum. It is possible however for MAG3110 to resort to clock stretching in case the ASIC is not free to service the read request. The link to the I 2 C specification of NXP (formerly Philips' Semiconductor Division) I 2 C-system is: Q: Does the same timing apply for multiple byte reads? A: You can calculate using the same format. N bytes read requires 91.8 μs + (N-1)*9 bit time. Q: Once the previous measurement has been read, how long does it take to get the next one? What is the duration between two DRDY flags? Does the 80-Hz output data rate mean 12.5 ms between two DR flags? A: The duration between two measurements in active mode (CTRL_REG1 = 0bXXXXXX01) depends on the data rate (ODR) and oversampling ratio (OSR) settings (CTRL_REG1[DR2:DR0] and CTRL_REG1[OS1:OS0] respectively). The 80-Hz output data rate means 12.5 ms between two DR flags. Q: What is the operating temperature of the device? A: -40 C to +85 C. Q: What does QFN stand for? A: Quad Flat No Lead. Q: Is the device lead-free? A: MAG3110 is a RoHS lead-free compliant product. Q: What is the purpose of the Who Am I register? A: This identifies the device and provides an easy way for verifying I 2 C communications. The MAG3110 WHO_AM_I register is 0xC4. Freescale Semiconductor 5

6 How to Reach Us: Home Page: Web Support: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Xtrinsic is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. All rights reserved. Rev 1 05/2012