Homework 5: Theory of Operation and Hardware Design Narrative Due: Friday, October 3, at NOON

Transcription

1 Homework 5: Theory of Operation and Hardware Design Narrative Due: Friday, October 3, at NOON Team Code Name: ECE Grande Group No. 3 Team Member Completing This Homework: Ashley Callaway Address of Team Member: acallawa@purdue.edu NOTE: This is the second in a series of four design component homework assignments, each of which is to be completed by one team member. The completed homework will count for 20% of the individual component of the team member s grade. The body of the report should be 3-5 pages, not including this cover page, references, attachments or appendices. Evaluation: SCORE DESCRIPTION Excellent among the best papers submitted for this assignment. Very few 10 corrections needed for version submitted in Final Report. Very good all requirements aptly met. Minor additions/corrections needed for 9 version submitted in Final Report. Good all requirements considered and addressed. Several noteworthy 8 additions/corrections needed for version submitted in Final Report. Average all requirements basically met, but some revisions in content should 7 be made for the version submitted in the Final Report. Marginal all requirements met at a nominal level. Significant revisions in 6 content should be made for the version submitted in the Final Report. Below the passing threshold major revisions required to meet report * requirements at a nominal level. Revise and resubmit. * Resubmissions are due within one week of the date of return, and will be awarded a score of 6 provided all report requirements have been met at a nominal level. Comments:

2 1.0 Introduction This project is to design and build a Digital Poker Table. Individual player stations will include a graphic LCD screen and pushbuttons. Each station will be controlled by a slave microcontroller that interfaces with the master microcontroller through SPI. The master also functions as the main controller of the RFID reader and the Ethernet connection. The RFID reader will read data from a tag to allow the player to logon to a station to begin play. The Ethernet connection will house all of the information of the current state of game as well as player information, and other pertinent information. Ethernet will also be used to update the community screen that will be placed at the center of the table for all players to view. With all of these subsections functioning correctly together, a digital poker experience results. 2.0 Theory of Operation There are six main subsections in the design of the circuit: microcontrollers, RFID reader, Ethernet, power supply, buttons, and LCD screens. 2.1 Microcontrollers The Freescale 9S12NE64 is the master microcontroller of the project and interface to all of the major peripherals of the system. It will operate at a frequency of 25MHz, off of an external crystal oscillator. This operating frequency satisfies the computational requirements of the game as well as conserves power that would have been used if the maximum frequency of 32MHz would have been chosen[1]. The Freescale 9S12GC32, the slave microcontroller, will be operating at a frequency of 16MHz. The operating frequency is lower than the master microcontroller because it does not require the same computational power. Each of the individual slave microcontrollers will run off of their own external crystal oscillators. 2.2 RFID Reader The Parallax RFID reader, used for reading RFID tags, allows players to logon to a station and being play. The tag must be parallel to the surface of the reader s antenna to ensure an accurate reading. A read-only mode will be implemented due to the fact that there is no need for the RFID reader to write to any tags. Since the reader outputs a 5 volt TTL signal, a level -1-

3 translator must be used to convert the TTL to CMOS and visa versa[2]. The level translated to be used is the Texas Instruments TX0104. It allows a range of 1.2 to 3.6 volts on port A (on the level translator) and a range of 1.6 to 5.5 volts on port B. This satisfies the requirements of level shifting between 3.3V and 5V for operation of this circuit[3]. The conversion from TTL to CMOS is required in order for the RFID reader to interface with the microcontroller. 2.3 Ethernet The Ethernet communicates the state of game to the community screen as well as sends player information to a server for safe keeping. This specific component is the reason that the clocking speed of the master microcontroller must be at a higher frequency than the slave microcontrollers. The protocol will be handled within the software of the microcontroller and the client software. The RJ45 Ethernet transformer contains internal magnets which are necessary for the Ethernet connection to function properly[4]. It will connect directly to the microcontroller. 2.4 LCD Screens The CrystalFontz CFAL12864L-Y-B2, graphical LCD screen will be displaying player s cards, actions, and balance. These screens will be interfacing directly with the slave microcontrollers using general purpose I/O pins. The screens will be interfacing over an 8-bit bidirectional data bus. An operating voltage of 3.3V is required for the logic as well as the power supply. The current draw will be approximately 90-mA for each of the LCD screens[5]. With regard to the drawing mode, the internal memory layout of the LCD screens uses a matrix to represent the pixels to draw. A cell is addressed and can specify an activation state[5]. This enables lights to illuminate in such a way that the combination of pixels will form an image. 2.5 Buttons Buttons are used to input player action. These specific buttons are Terminal Microswitch pushbuttons, which are noted in [6] to be reliable for up to 10,000,000 presses. This is extremely important for the design of this game because players will be using these buttons in every action of the game. They are the only inputs that will affect the poker game itself. The pushbuttons will -2-

4 function as a switch, sending a signal to the slave microcontroller whenever the button has been pressed. 2.6 Power Supply Since most of the subsections of the circuit will require 3.3V or 5V, a 9V wall wart will be used initially. Then linear regulators will be used to produce the 3.3V and 5V lines that will be necessary for the subsections of the circuit. 3.0 Hardware Design Narrative The master microcontroller is the center of the project and it interfaces with the RFID reader, slave microcontroller, and Ethernet subsections of the circuit using on-chip peripherals as well as general purpose I/O pins. Interfaces with on-chip modules will be explained in the following paragraphs Another on-chip module to be used is the timer. The timing module will be used to implement a countdown that notifies the players when the next game is going to begin. This feature allows the players to either join or exit a game before the next game begins. The RFID reader and the master microcontroller are connected in two ways: through SCI and through 1 GPIO pin. The PAD0 signal, which is the output enable, is only going in one direction, and that is to the RFID at RFIDOE, through the level translator. This used to turn on and off the antenna. The RFIDTX signal, which is the transmit signal from the RFID, communicates serially at 2400 baud to the microcontroller at PS0, through the level translator. Level Translator (TXB0104) MASTER IN OUT RFID PS0 A1 B1 RFIDTX PAD0 A2 B2 RFIDOE Table 3.1 Master-RFID The master and the Ethernet transformer will be connected in parallel using 4 general purpose I/O pins. Between the RJ45 and the microcontroller there are impedances to deal with to ensure quality of signal and other such things unknown at this point. Special consideration will -3-

5 be taken into account to ensure that the layout will meet the specification for the microcontroller to properly handle connection from the RJ45. Ethernet Master Transformer Signal Pin Name R+ PHY_RXP R- PHY_RXN T- PHY_TXN T+ PHY_TXP Table 3.2 Master-Ethernet Communication between the master and slave microcontrollers is performed through the on-chip SPI modules of both. Four 3-bit SPI bus will connect the master with each of the four slaves. It also requires slave selects for each of the master-slave connections. Master Micro Slave Micro: SIGNAL Master Pin Name SIGNAL Slave Pin Name MISO PS4 MISO PM2/MISO MOSI PS5 MOSI PM4/MOSI SCK PS6 SCK PM5/SCK Slave Select (SS) PAD1, PAD2, PAD3, PAD4 Slave Select (SS) PM3/SS Table 3.3 Master-Slave Each of the slave microcontrollers connect to its LCD screen in parallel through an 8-bit bidirectional data bus. The communication between the slave microcontroller and the LCD is broken up between data and command signals. There are eight data lines for addressing the matrix of pixels, one of which is a clock. These are responsible for specifying which pixel to toggle with the cursor. The remaining six pins transmit signals which manage the various operating modes on the LCD. Operating mode will be decided on a later date. -4-

6 LCD Signal Slave Pin Name D0 XCLK D1:D7 PAD1:PAD7 Data/Command Select PW3 (D/C#) MCU interface input pin GND (R/W#) MCU interface input pin GND E(RD#) Chip Select (CS) IOC4/PT4 Reset (active low) RESET MCU interface input selection 3.3V M80/68# Table 3.4 The buttons will interface to the slave using one pin for each of the buttons (3 pins per station). The buttons will be active high. We chose the Terminal Microswitch because of their long lifetime rated at 10,000,000 cycles [4]. Button Signal Slave Pin Name B1 PW0 B2 PW1 B3 PW2 Table Summary The ECE Grand Digital Poker Table has been designed in such a way to ensure that proper communication between the microcontrollers and the peripherals does not have any interference. Considerations were also taken into account regarding the speed needed to relay information between the master-ethernet as well as the mater-slave. The Ethernet component forces the master to require a higher operating frequency than that of the slave. Special consideration will -1-

7 be taken in designing the PCB layout for the placement of all of the components. Since the slave microcontrollers have their own subsystem, the placement of these subsystems with respect to each other is also very important. Even though the master microcontroller is the main control unit of the design, the slaves will require a lot of space, forcing the RFID and Ethernet connection to be on one side of the master while the four slave subsystems will likely take up the remainder of the layout space. With the circuit design mentioned in this paper along with any other necessary impedance calculations needed between the connections, a working digital poker table will result. -2-

8 List of References [1] MC9S12NE64 Data Sheet, [Online Document], [cited 2 September 2008], Available HTTP: =1&WT_TYPE=Data%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT= pdf&wt_asset=documentation [2] RFID Reader Module (#28140), [Online Document], [cited 1 October 2008], Available HTTP: Reader-v1.2.pdf [3] 4-Bit Bidirectional Level Translator, [Online Document], [cited 2 October 2008], Available HTTP: [4] Transformer: MIC W-LF3, [Online Document], [cited 2 October 2008], Available HTTP: [5] CrystalFontz America, Inc. Module No. CFAL12864L-Y-B2, [Online Document], [cited 1 October 2008], Available HTTP: [6] Competition Button, [Online Document], [cited 2 October 2008], Available HTTP: -3-

9 Appendix A: System Block Diagram -4-

10 Appendix B: Preliminary Master Micro Schematic -5-

11 Appendix C: Preliminary Slave Micro Schematic -6-