SBC Gen2 with CAN high speed and LIN interface

Transcription

1 NXP Semiconductors Data Sheet: Advance Information SBC Gen2 with CAN high speed and LIN interface The is the second generation family of the System Basis Chip (SBC). It combines several features and enhances present module designs. The device works as an advanced power management unit for the MCU with additional integrated circuits such as sensors and CAN transceivers. It has a builtin enhanced highspeed CAN interface (ISO and 5) with local and bus failure diagnostics, protection, and failsafe operation modes. The SBC may include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It includes up to four wakeup input pins that can also be configured as output drivers for flexibility. This device is powered by SMARTMOS technology. This device implements multiple Lowpower (LP) modes, with very lowcurrent consumption. In addition, the device is part of a family concept where pin compatibility adds versatility to module design. The also implements an innovative and advanced failsafe state machine and concept solution. Features Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with possibility of usage external PNP to extend current capability and share power dissipation Voltage, current, and temperature protection Extremely low quiescent current in LP modes Fullyprotected embedded 5.0 V regulator for the CAN driver Multiple undervoltage detections to address various MCU specifications and system operation modes (i.e. cranking) Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with overcurrent detection and undervoltage protection MUX output pin for device internal analog signal monitoring and power supply monitoring Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and monitoring. Multiple wakeup sources in LP modes: CAN or LIN bus, I/O transition, automatic timer, SPI message, and V DD overcurrent detection. ISO highspeed CAN interface compatibility for baud rates of 40 kb/s to 1.0 Mb/s Scalable product family of devices ranging from 0 to 2 LINs which are compatible to J26022 and LIN 2.1 EK Suffix (Pbfree) 98ASA10556D 32PIN SOIC Applications Document Number: MC33903_4_5 Rev. 14.0, 2/2018 SYSTEM BASIS CHIP EK Suffix (Pbfree) 98ASA10506D 54PIN SOIC Aircraft and marine systems Automotive and robotic systems Farm equipment Industrial actuator controls Lamp and inductive load controls DC motor control applications requiring diagnostics Applications where highside switch control is required * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. NXP B.V

2 Table of Contents 1. Simplified application diagrams Orderable part Internal block diagrams Pin Connections Pinout diagram Electrical characteristics Maximum ratings Static electrical characteristics Dynamic electrical characteristics Timing diagrams Functional description Introduction Functional pin description Functional device operation Mode and state description LP modes State diagram Mode change Watchdog operation Functional block operation versus mode Illustration of device mode transitions Cyclic sense operation during LP modes Cyclic INT operation during LP VDD on mode Behavior at power up and power down Failsafe operation CAN interface CAN interface description CAN bus fault diagnostic LIN block LIN interface description LIN operational modes Serial peripheral interface High level overview Detail operation Detail of control bits and register mapping Flags and device status Typical applications Packaging SOIC 32 package dimensions SOIC 54 package dimensions Revision history NXP Semiconductors

3 SIMPLIFIED APPLICATION DIAGRAMS 1 Simplified application diagrams V BAT D1 Q D Q1* (5.0 V/3.3 V) * = Optional VBAUX VCAUX VSUP1 VAUX VSUP2 SAFE DBG GND VSENSE I/O0 VE VB VDD INT MOSI SCLK MISO CS MUXOUT SPI V DD A/D MCU CAN Bus LIN Bus LIN Bus I/O1 CANH SPLIT CANL LINTERM 1 LIN1 LINTERM 2 LIN2 5VCAN TXD RXD TXDL1 RXDL1 TXDL2 RXDL2 Figure D simplified application diagram V BAT D1 Q S Q1* (5.0 V/3.3 V) * = Optional VBAUX VCAUX VSUP1 VAUX VSUP2 SAFE DBG GND VSENSE I/O0 VE VB VDD INT MOSI SCLK MISO CS MUXOUT SPI V DD A/D MCU V BAT CAN Bus LIN Bus I/O1 CANH SPLIT CANL LINT LIN 5VCAN TXD RXD TXDL RXDL I/O3 Figure S simplified application diagram NXP Semiconductors 3

4 SIMPLIFIED APPLICATION DIAGRAMS V BAT D1 Q Q1* (5.0 V/3.3 V) * = Optional VBAUX VCAUX VSUP1 VAUX VSUP2 SAFE DBG GND VSENSE I/O0 VE VB VDD INT MOSI SCLK MISO CS MUXOUT SPI V DD A/D MCU V BAT CAN Bus I/O1 CANH SPLIT CANL 5VCAN TXD RXD I/O2 I/O3 Figure simplified application diagram V BAT D VSUP1 DBG SAFE GND I/O0 VSUP2 VDD INT MOSI SCLK MISO CS SPI V DD MCU CAN Bus CANH SPLIT CANL 5VCAN TXD RXD Figure simplified application diagram 4 NXP Semiconductors

5 SIMPLIFIED APPLICATION DIAGRAMS V BAT D D Q1* * = Optional VSUP VE VB VDD V DD SAFE DBG GND VSENSE IO0 INT MOSI SCLK MISO CS MUXOUT SPI A/D MCU CAN Bus LIN Bus LIN Bus CANH SPLIT CANL LINT1/I/O2 LIN1 LINT2/IO3 LIN2 5VCAN TXD RXD TXDL1 RXDL1 TXDL2 RXDL2 Figure D simplified application diagram V BAT D S Q1* * = Optional VSUP VE VB VDD V DD SAFE DBG GND VSENSE IO0 INT MOSI SCLK MISO CS MUXOUT SPI A/D MCU V BAT CAN Bus LIN Bus CANH SPLIT CANL LINT1/I/O2 LIN1 I/O3 5VCAN TXD RXD TXDL1 RXDL1 Figure S simplified application diagram NXP Semiconductors 5

6 SIMPLIFIED APPLICATION DIAGRAMS V BAT D P Q1* * = Optional VSUP VE VB VDD V DD SAFE DBG GND VSENSE IO0 CANH INT MOSI SCLK MISO CS MUXOUT SPI A/D MCU CAN Bus V BAT SPLIT CANL 5VCAN TXD RXD V BAT I/O2 I/O3 Figure P simplified application diagram 6 NXP Semiconductors

7 ORDERABLE PART 2 Orderable part Table 1. MC33905 orderable part variations (all devices rated at T A = 40 C TO 125 C) NXP part number Version (1), (2), (3) V DD output voltage LIN interface(s) Wakeup input / LIN master termination Package V AUX V SENSE MUX MC33905D (Dual LIN) MCZ33905BD3EK/R2 B MCZ33905CD3EK/R2 MCZ33905DD3EK/R2 MCZ33905D5EK/R2 MCZ33905BD5EK/R2 MCZ33905CD5EK/R2 C D B C 3.3 V 5.0 V 2 2 Wakeup + 2 LIN terms or 3 Wakeup + 1 LIN terms or 4 Wakeup + no LIN terms SOIC 54pin exposed pad Yes Yes Yes MCZ33905DD5EK/R2 D MC33905S (Single LIN) MCZ33905BS3EK/R2 B MCZ33905CS3EK/R2 C 3.3 V MCZ33905DS3EK/R2 MCZ33905S5EK/R2 MCZ33905BS5EK/R2 MCZ33905CS5EK/R2 D B C 5.0 V 1 3 Wakeup + 1 LIN terms or 4 Wakeup + no LIN terms SOIC 32pin exposed pad Yes Yes Yes MCZ33905DS5EK/R2 D Notes 1. Design changes in the B version resolved V SUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. B version has an errata linked to the SPI operation. 2. Design changes in the C version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 3. C versions are no longer recommended for new design. D versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. Table 2. MC33904 orderable part variations (all devices rated at T A = 40 C TO 125 C) NXP part number Version (4), (5), (6) V DD output voltage LIN interface(s) Wakeup input / LIN master termination Package V AUX V SENSE MUX MC33904 MCZ33904B3EK/R2 B MCZ33904C3EK/R2 C 3.3 V MCZ33904D3EK/R2 MCZ33904A5EK/R2 MCZ33904B5EK/R2 MCZ33904C5EK/R2 D A B C 5.0 V 0 4 Wakeup SOIC 32 pin exposed pad Yes Yes Yes MCZ33904D5EK/R2 D Notes 4. Design changes in the B version resolved V SUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. B version has an errata linked to the SPI operation. 5. Design changes in the C version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 6. C versions are no longer recommended for new design. D versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. NXP Semiconductors 7

8 ORDERABLE PART Table 3. MC33903 orderable part variations (all devices rated at T A = 40 C TO 125 C) NXP part number Version (8), (9), (10) V DD output voltage LIN interface(s) Wakeup input / LIN master termination Package V AUX V SENSE MUX MC33903 MCZ33903B3EK/R2 B MCZ33903C3EK/R2 C 3.3 V (7) MCZ33903D3EK/R2 MCZ33903B5EK/R2 D B 0 1 Wakeup SOIC 32 pin exposed pad No No No MCZ33903C5EK/R2 C 5.0 V (7) MCZ33903D5EK/R2 D MC33903D (Dual LIN) MCZ33903BD3EK/R2 B MCZ33903CD3EK/R2 MCZ33903DD3EK/R2 MCZ33903BD5EK/R2 MCZ33903CD5EK/R2 C D B C 3.3 V 5.0 V 2 1 Wakeup + 2 LIN terms or 2 Wakeup + 1 LIN terms or 3 Wakeup + no LIN terms SOIC 32 pin exposed pad No Yes Yes MCZ33903DD5EK/R2 D MC33903S (Single LIN) MCZ33903BS3EK/R2 B MCZ33903CS3EK/R2 C 3.3 V MCZ33903DS3EK/R2 MCZ33903BS5EK/R2 D B 1 2 Wakeup + 1 LIN terms or 3 Wakeup + no LIN terms SOIC 32 pin exposed pad No Yes Yes MCZ33903CS5EK/R2 C 5.0 V MCZ33903DS5EK/R2 D MC33903P MCZ33903CP5EK/R2 MCZ33903DP5EK/R2 MCZ33903CP3EK/R2 MCZ33903DP3EK/R2 C D C D 5.0 V 3.3 V 0 3 Wakeup SOIC 32 pin exposed pad No Yes Yes Notes 7. V DD does not allow usage of an external PNP on the Design changes in the B version resolved V SUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. B version has an errata linked to the SPI operation. 9. Design changes in the C version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature. 10. C versions are no longer recommended for new design. D versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes. 8 NXP Semiconductors

9 INTERNAL BLOCK DIAGRAMS 3 Internal block diagrams VBAUX VCAUX VAUX VSUP1 VE VB VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5 V Auxiliary Regulator V DD Regulator VDD VSUP2 5V Auxiliary Regulator V DD Regulator VDD V S2INT V S2INT SAFE DBG GND VSENSE Failsafe Power Management State Machine Oscillator Analog Monitoring SPI INT MOSI SCLK MISO CS SAFE DBG GND VSENSE Failsafe Power Management State Machine Oscillator Analog Monitoring SPI INT MOSI SCLK MISO CS Signals Condition & Analog MUX MUXOUT Signals Condition & Analog MUX MUXOUT I/O0 I/O1 CANH SPLIT CANL V S2INT Configurable InputOutput 5VCAN Regulator Enhanced High Speed CAN Physical Interface 5 VCAN TXD RXD I/O0 I/O1 I/O3 CANH SPLIT CANL Configurable InputOutput V S2INT 5VCAN Regulator Enhanced High Speed CAN Physical Interface 5 VCAN TXD RXD LINT1 LIN1 LINT2 LIN2 V S2INT LIN Term #1 V S2INT LIN Term #2 LIN 2.1 Interface #1 LIN 2.1 Interface #2 TXDL1 RXDL1 TXDL2 RXDL2 LINT LIN V S2INT LIN Term #1 LIN 2.1 Interface # S TXDL RXDL 33905D Figure internal block diagram VBAUX VCAUX VAUX VSUP1 VE VB VSUP2 5V Auxiliary Regulator V DD Regulator VDD V S2INT SAFE DBG GND VSENSE Failsafe Power Management State Machine Oscillator Analog Monitoring SPI INT MOSI SCLK MISO CS Signals Condition & Analog MUX MUXOUT I/O0 I/O1 I/O2 I/O3 Configurable InputOutput V S2INT 5VCAN Regulator 5VCAN CANH SPLIT CANL Enhanced High Speed CAN Physical Interface TXD RXD Figure internal block diagram NXP Semiconductors 9

10 INTERNAL BLOCK DIAGRAMS VSUP1 VSUP VE VB VSUP2 V DD Regulator VDD V SINT V DD Regulator VDD SAFE DBG GND I/O0 CANH SPLIT CANL V S2INT Oscillator Configurable InputOutput Power Management State Machine V S2INT 5VCAN Regulator Enhanced High Speed CAN Physical Interface SPI INT MOSI SCLK MISO CS 5 VCAN TXD RXD SAFE DBG GND VSENSE I/O0 I/O2 I/O3 Oscillator Configurable InputOutput Failsafe Power Management State Machine Analog Monitoring Signals Condition & Analog MUX V SINT 5VCAN Regulator SPI INT MOSI SCLK MISO CS MUXOUT 5 VCAN CANH SPLIT CANL Enhanced High Speed CAN Physical Interface TXD RXD VSUP VE VB 33903P V SINT V DD Regulator VDD VSUP VE VB SAFE DBG GND VSENSE IO0 Failsafe Power Management Oscillator State Machine SPI Analog Monitoring Signals Condition & Analog MUX V SINT Configurable 5VCAN InputOutput Regulator INT MOSI SCLK MISO CS MUXOUT 5 VCAN SAFE DBG GND VSENSE V SINT V DD Regulator Failsafe Power Management Oscillator State Machine SPI Analog Monitoring Signals Condition & Analog MUX VDD INT MOSI SCLK MISO CS MUXOUT CANH SPLIT CANL Enhanced Highspeed CAN Physical Interface TXD RXD I/O0 I/O3 Configurable InputOutput V SINT 5VCAN Regulator 5 VCAN LINT1 LIN1 LINT2 LIN2 V SINT V SINT LIN Term #1 LIN Term #2 LIN 2.1 Interface #1 LIN 2.1 Interface #2 TXDL1 RXDL1 TXDL2 RXDL2 CANH SPLIT CANL LINT LIN V SINT Enhanced High Speed CAN Physical Interface LIN Term #1 LIN 2.1 Interface #1 TXD RXD TXDL RXDL 33903D 33903S Figure internal block diagram 10 NXP Semiconductors

11 PIN CONNECTIONS 4 Pin Connections 4.1 Pinout diagram NC NC NC VSUP1 VSUP2 LINT2/I/O3 LINT1/I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT VBAUX VCAUX VAUX MUXOUT I/O0 DBG NC NC NC TXDL2 GND RXDL2 LIN2 NC MC33905D GROUND GND LEAD FRAME 54 pin exposed package NC NC NC VB VE RXD TXD VDD MISO MOSI SCLK CS INT I/O1 VSENSE RXDL1 TXDL1 LIN1 NC NC NC NC GND NC NC NC VSUP1 VSUP2 I/O3 LINT/I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT VBAUX VCAUX VAUX MUXOUT I/O0 DBG MC33905S GROUND GND LEAD FRAME 32 pin exposed package VB VE RXD TXD VDD MISO MOSI SCLK CS INT I/O1 VSENSE RXDL TXDL LIN VSUP1 VSUP2 I/O3 I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT VBAUX VCAUX VAUX MUXOUT I/O0 DBG MC GROUND VB VE RXD TXD VDD MISO MOSI SCLK CS INT I/O1 VSENSE NC NC NC VSUP1 VSUP2 NC NC SAFE 5VCAN CANH CANL GND CAN SPLIT NC NC NC NC I/O0 DBG MC GROUND NC NC RXD TXD VDD MISO MOSI SCLK CS INT NC NC NC NC NC GND LEAD FRAME 32 pin exposed package GND LEAD FRAME 32 pin exposed package Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible, Figure D, MC33905S, MC33904 and MC33903 pin connections NXP Semiconductors 11

12 PIN CONNECTIONS VB VSUP LINT2 / I/O3 LINT1 / I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT MUXOUT IO0 DBG TXDL2 GND RXDL2 MC33903D GROUND VE RXD TXD VDD MISO MOSI SCLK CS INT VSENSE RXDL1 TXDL1 LIN1 GND LIN2 VB VSUP I/O3 LINT / I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT MUXOUT I/O0 DBG NC GND NC MC33903S GROUND VE RXD TXD VDD MISO MOSI SCLK CS INT VSENSE RXDL TXDL LIN GND NC GND LEAD FRAME 32 pin exposed package GND LEAD FRAME 32 pin exposed package VB VSUP I/O3 I/O2 SAFE 5VCAN CANH CANL GND CAN SPLIT MUXOUT I/O0 DBG NC GND NC MC33903P GROUND VE RXD TXD VDD MISO MOSI SCLK CS INT VSENSE N/C N/C N/C GND NC GND LEAD FRAME 32 pin exposed package Note: MC33903D, MC33903S, and MC33903P are footprint compatible. Figure D, MC33905S, MC33904 and MC33903 pin connections 12 NXP Semiconductors

13 PIN CONNECTIONS 4.2 Pin definitions A functional description of each pin can be found in the Functional pin description section beginning on page 32. Table 4. pin definitions 54 Pin 33905D 32 Pin 33905S 32 Pin Pin Pin 33903D 32 Pin 33903S 32 Pin 33903P Pin Name Pin Function Formal Name Definition 13, 20 22, 27 30, 32 35, N/A 17, 18, 19 34,11 14, 17 21, 31, 32 N/A N/A N/A N/C No Connect Connect to GND. N/A N/A N/A N/A N/A 14, 16, 17 14, 16, 17, N/C No Connect VSUP/1 Power Battery Voltage Supply 1 Do NOT connect the N/C pins to GND. Leave these pins Open. Supply input for the device internal supplies, power on reset circuitry and the V DD regulator. VSUP and VSUP1 supplies are internally connected on part number MC33903BDEK and MC33903BSEK N/A N/A N/A VSUP2 Power N/A N/A LINT2 or I/O3 LINT1 or LINT or I/O2 Output or Input/ Output Output or Input/ Output SAFE Output Battery Voltage Supply 2 LIN Termination 2 or Input/Output 3 LIN Termination 1 or Input/Output 2 Safe Output (Active LOW) VCAN Output 5VCAN CANH Output CAN High CAN high output CANL Output CAN Low CAN low output. Supply input for 5 VCAN regulator, V AUX regulator, I/O and LIN pins. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK 33903D and 33905D Output pin for the LIN2 master node termination resistor. or 33903P, 33903S, 33903D, 33904, 33905S and 33905D Configurable pin as an input or HS output, for connection to external circuitry (switched or small load). The input can be used as a programmable Wakeup input in (LP) mode. When used as a HS, no overtemperature protection is implemented. A basic short to GND protection function, based on switch drainsource overvoltage detection, is available D Output pin for the LIN1 master node termination resistor. or 33903P, 33903S, 33903D, 33904, 33905S and 33905D Configurable pin as an input or HS output, for connection to external circuitry (switched or small load). The input can be used as a programmable Wakeup input in (LP) mode. When used as a HS, no overtemperature protection is implemented. A basic short to GND protection function, based on switch drainsource overvoltage detection, is available. Output of the safe circuitry. The pin is asserted LOW if a fault event occurs (e.g.: software watchdog is not triggered, V DD low, issue on the pin, etc.). Open drain structure. Output voltage for the embedded CAN interface. A capacitor must be connected to this pin GNDCAN Ground GNDCAN Power GND of the embedded CAN interface SPLIT Output SPLIT Output Output pin for connection to the middle point of the split CAN termination NXP Semiconductors 13

14 PIN CONNECTIONS Table 4. pin definitions (continued) 54 Pin 33905D 32 Pin 33905S 32 Pin Pin Pin 33903D 32 Pin 33903S 32 Pin 33903P Pin Name Pin Function Formal Name Definition N/A N/A N/A N/A VBAUX Output VB Auxiliary N/A N/A N/A N/A VCAUX Output N/A N/A N/A N/A VAUX Output N/A MUXOUT Output I/O0 Input/ Output VCOLLECT OR Auxiliary VOUT Auxiliary Multiplex Output Input/Output DBG Input Debug 23 N/A N/A N/A 14 N/A N/A TXDL2 Input LIN Transmit Data 2 24,31 N/A N/A N/A 15, 18 15, 18 15, 18 GND Ground Ground Ground of the IC. 25 N/A N/A N/A 16 N/A N/A RXDL2 Output 26 N/A N/A N/A 17 N/A N/A LIN N/A N/A N/A N/A N/A N/A N/A N/A N/A 33903D/5D LIN S/5S LIN 33903D/5D TXDL S/5S TXDL 33903D/5D RXDL S/5S RXDL Input/ Output Input/ Output Input Output LIN Receive Data LIN bus LIN bus LIN Transmit Data LIN Receive Data N/A VSENSE Input Sense input N/A N/A N/A N/A I/O1 Input/ Output Input Output 1 Output pin for external path PNP transistor base Output pin for external path PNP transistor collector Output pin for the auxiliary voltage. Multiplexed output to be connected to an MCU A/D input. Selection of the analog parameter available at MUXOUT is done via the SPI. A switchable internal pulldown resistor is integrated for V DD current sense measurements. Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and via the MUX output pin. The input can be used as a programmable Wakeup input in LP mode. In LP, when used as an output, the Highside (HS) or Lowside (LS) can be activated for a cyclic sense function. Input to activate the Debug mode. In Debug mode, no watchdog refresh is necessary. Outside of Debug mode, connection of a resistor between DBG and GND allows the selection of Safe mode functionality. LIN bus transmit data input. Includes an internal pullup resistor to VDD. LIN bus receive data output. LIN bus input output connected to the LIN bus. LIN bus input output connected to the LIN bus. LIN bus transmit data input. Includes an internal pullup resistor to VDD. LIN bus receive data output. Direct battery voltage input sense. A serial resistor is required to limit the input current during high voltage transients. Configurable pin as an input or output, for connection to external circuitry (switched or small load). The voltage level can be read by the SPI and the MUX output pin. The input can be used as a programmable Wakeup input in (LP) mode. It can be used in association with I/O0 for a cyclic sense function in (LP) mode. 14 NXP Semiconductors

15 PIN CONNECTIONS Table 4. pin definitions (continued) 54 Pin 33905D 32 Pin 33905S 32 Pin Pin Pin 33903D 32 Pin 33903S 32 Pin 33903P Pin Name Pin Function Formal Name Definition Output Reset Output (Active LOW) This is the device reset output whose main function is to reset the MCU. This pin has an internal pullup to VDD. The reset input voltage is also monitored in order to detect external reset and safe conditions INT Output CS Input SCLK Input MOSI Input MISO Output VDD Output TXD Input Interrupt Output (Active LOW) Chip Select (Active LOW) Serial Data Clock Master Out / Slave In Master In / Slave Out Voltage Digital Drain Transmit Data This output is asserted low when an enabled interrupt condition occurs. This pin is an open drain structure with an internal pull up resistor to VDD. Chip select pin for the SPI. When the CS is low, the device is selected. In (LP) mode with V DD ON, a transition on CS is a Wakeup condition Clock input for the Serial Peripheral Interface (SPI) of the device SPI data received by the device SPI data sent to the MCU. When the CS is high, MISO is highimpedance 5.0 or 3.3 V output pin of the main regulator for the Microcontroller supply. CAN bus transmit data input. Internal pullup to VDD RXD Output Receive Data CAN bus receive data output N/A VE Voltage Emitter N/A VB Output Voltage Base EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD GND Ground Ground Ground Connection to the external PNP path transistor. This is an intermediate current supply source for the V DD regulator Base output pin for connection to the external PNP pass transistor NXP Semiconductors 15

16 ELECTRICAL CHARACTERISTICS 5 Electrical characteristics 5.1 Maximum ratings Table 5. Maximum ratings All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes Electrical ratings (11) V SUP1/2 V SUP1/2TR Supply Voltage at VSUP/1 and VSUP2 Normal Operation (DC) Transient Conditions (Load Dump) 0.3 to to 40 V V BUSLIN V BUSLINTR DC voltage on LIN/1 and LIN2 Normal Operation (DC) Transient Conditions (Load Dump) 28 to to 40 V V BUS V BUSTR DC voltage on CANL, CANH, SPLIT Normal Operation (DC) Transient Conditions (Load Dump) 28 to to 40 V V SAFE V SAFETR DC Voltage at SAFE Normal Operation (DC) Transient Conditions (Load Dump) 0.3 to to 40 V V I/O V I/OTR DC Voltage at I/O0, I/O1, I/O2, I/O3 (LINT Pins) Normal Operation (DC) Transient Conditions (Load Dump) 0.3 to to 40 V V DIGLIN DC voltage on TXDL, TXDL1 TXDL2, RXDL, RXDL1, RXDL2 0.3 to V DD +0.3 V V DIG DC voltage on TXD, RXD 0.3 to V DD +0.3 V (13) V INT DC Voltage at INT 0.3 to 10 V V DC Voltage at 0.3 to V DD +0.3 V V DC Voltage at MOSI, MSIO, SCLK and CS 0.3 to V DD +0.3 V V MUX DC Voltage at MUXOUT 0.3 to V DD +0.3 V V DBG DC Voltage at DBG 0.3 to 10 V ILH Continuous current on CANH and CANL 200 ma V REG DC voltage at VDD, 5VCAN, VAUX, VCAUX 0.3 to 5.5 V V REG DC voltage at VBASE and VBAUX 0.3 to 40 V VE DC voltage at VE 0.3 to 40 V (12) (13) V SENSE DC voltage at VSENSE 28 to 40 V Notes 11. The voltage on nonvsup pins should never exceed the V SUP voltage at any time or permanent damage to the device may occur. 12. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external V DD ballast current sharing functionality may be damaged. 13. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON. 16 NXP Semiconductors

17 ELECTRICAL CHARACTERISTICS Table 5. Maximum ratings (continued) All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes V ESD11 V ESD12 V ESD21 V ESD22 V ESD31 V ESD32 V ESD33 V ESD41 V ESD42 V ESD43 Thermal ratings ESD Capability AECQ100 (14) Human Body Model JESD22/A114 (C ZAP = 100 pf, R ZAP = 1500 Ω) CANH and CANL. LIN1 and LIN2, Pins versus all GND pins all other Pins including CANH and CANL Charge Device Model JESD22/C101 (C ZAP = 4.0 pf) Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 215, 1831) Tested per IEC (C ZAP = 150 pf, R ZAP = 330 Ω) Device unpowered, CANH and CANL pin without capacitor, versus GND Device unpowered, LIN, LIN1 and LIN2 pin, versus GND Device unpowered, VS1/VS2 (100 nf to GND), versus GND Tested per specific OEM EMC requirements for CAN and LIN with additional capacitor on VSUP/1/2 pins (See Typical applications on page 92) CANH, CANL without bus filter LIN, LIN1 and LIN2 with and without bus filter I/O with external components (22 k 10 nf) ±8000 ±2000 ±750 ±500 ±15000 ±15000 ±15000 ±9000 ±12000 ±7000 T J Junction temperature 150 C T A Ambient temperature 40 to 125 C T ST Storage temperature 50 to 150 C Thermal resistance R θja Thermal resistance junction to ambient 50 C/W (17) T PPRT Peak package reflow temperature during reflow Note 16 C (15), (16) Notes 14. ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pf, R ZAP = 1500 Ω), the Charge Device Model (CDM), and Robotic (C ZAP = 4.0 pf). 15. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 16. NXP s Package Reflow capability meets Pbfree requirements for JEDEC standard JSTD020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. 17. This parameter was measured according to Figure 13: V PCB 100mm x 100mm Top side, 300 sq. mm (20mmx15mm) Bottom side 20mm x 40mm Bottom view Figure 13. PCB with top and bottom layer dissipation area (dual layer) NXP Semiconductors 17

18 ELECTRICAL CHARACTERISTICS 5.2 Static electrical characteristics Table 6. Static electrical characteristics Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Power input V SUP1 /V SUP2 Nominal DC Voltage Range V (18) V SUP1 /V SUP2 Extended DC Low Voltage Range V (19) V S1_LOW Undervoltage Detector Thresholds, at the VSUP/1 pin, Low threshold (VSUP/1 ramp down) High threshold (VSUP/1 ramp up) Hysteresis Note: function not active in LP mode V V S2_LOW Undervoltage Detector Thresholds, at the VSUP2 pin: Low threshold (VSUP2 ramp down) High threshold (VSUP2 ramp up) Hysteresis Note: function not active in LP modes V V S_HIGH V SUP Overvoltage Detector Thresholds, at the VSUP/1 pin: Not active in LP modes V BATFAIL Battery loss detection threshold, at the VSUP/1 pin V V SUPTH1 VSUP/1 to turn V DD ON, VSUP/1 rising V V SUPTH1HYST VSUP/1 to turn V DD ON, hysteresis (Guaranteed by design) mv I SUP1 I SUP1+2 I LPM_OFF Supply current from VSUP/1 from VSUP2, (5VCAN V AUX, I/O OFF) Supply current, I SUP1 + I SUP2, Normal mode, V DD ON 5 VCAN OFF, V AUX OFF 5 VCAN ON, CAN interface in Sleep mode, V AUX OFF 5 VCAN OFF, Vaux ON 5 VCAN ON, CAN interface in TXD/RXD mode, V AUX OFF, I/Ox disabled LP mode V DD OFF. Wakeup from CAN, I/Ox inputs V SUP 18 V, 40 to 25 C V SUP 18 V, 125 C ma (20), (21) ma μa I LPM_ON LP mode V DD ON (5.0 V) with V DD undervoltage and V DD overcurrent monitoring, Wakeup from CAN, I/Ox inputs V SUP 18 V, 40 to 25 C, I DD = 1.0 μa V SUP 18 V, 40 to 25 C, I DD = 100 μa V SUP 18 V, 125 C, I DD = 100 μa μa I OSC LP mode, additional current for oscillator (used for: cyclic sense, forced Wakeup, and in LP V DD ON mode cyclic interruption and watchdog) V SUP 18 V, 40 to 125 C μa V DBG Debug mode DBG voltage range V Notes 18. All parameters in spec (ex: V DD regulator tolerance). 19. Device functional, some parameters could be out of spec. V DD is active, device is not in Reset mode if the lowest V DD undervoltage reset threshold is selected (approx. 3.4 V). CAN and I/Os are not operational. 20. In Run mode, CAN interface in Sleep mode, 5 VCAN and V AUX turned OFF. I OUT at V DD < 50 ma. Ballast: turned OFF or not connected. 21. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, I SUP1 and I SUP2 cannot be measured individually. 18 NXP Semiconductors

19 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes V DD Voltage regulator, VDD pin V OUT5.0 V OUT5.0EMC V OUT3.3 Output Voltage V DD = 5.0 V, V SUP 5.5 to 28 V, I OUT 0 to 150 ma V DD = 5.0 V, under EMC immunity test condition V DD = 3.3 V, V SUP 5.5 to 28 V, I OUT 0 to 150 ma V (22) V DROP Drop voltage without external PNP pass transistor V DD = 5.0 V, I OUT = 100 ma V DD = 5.0 V, I OUT = 150 ma mv (23) V DROPB Drop voltage with external transistor I OUT = 200 ma (I _BALLAST + I _INTERNAL ) mv (23) V SUP13.3 VSUP/1 to maintain V DD within V OUT3.3 specified voltage range V DD = 3.3 V, I OUT = 150 ma V DD = 3.3 V, I OUT = 200 ma, external transistor implemented V K External ballast versus internal current ratio (I _BALLAST = K x Internal current) I LIM Output Current limitation, without external transistor ma T PW Temperature prewarning (Guaranteed by design) 140 C T SD Thermal shutdown (Guaranteed by design) 160 C C EXT Range of decoupling capacitor (Guaranteed by design) μf (24) V DDLP LP mode V DD ON, I OUT 50 ma (time limited) V DD = 5.0 V, 5.6 V V SUP 28 V V DD = 3.3 V, 5.6 V V SUP 28 V LP mode V L DD ON, dynamic output current capability (Limited duration. PIOUTDC Ref. to device description). LP V DD ON mode: L PITH Overcurrent Wakeup threshold. Hysteresis LP mode V L DD ON, drop voltage, at I OUT = 30 ma (Limited duration. PVDROP Ref. to device description) LP mode V L DD ON, min V SUP operation (Below this value, a V DD, PMINVS undervoltage reset may occur) ma V ma mv (23) 5.5 V V DD_OFF V DD when V SUP < V SUPTH1, at I_V DD 10 μa (Guaranteed by design) 0.3 V V DD_START UP V DD when V SUP V SUPTH1, at I_V DD 40 ma (Guaranteed with parameter V SUPTH1 3.0 V Notes 22. Guaranteed by design. During immunity tests, according to IEC621324, with RF injection applied to CAN or LIN pins. No filter components on CAN or LIN pins. When immunity tests are performed with a CAN filter component (common mode choke) or LIN filter component (capacitor), the V DD specification is 5.0 V ±2%. 23. For 3.3 V V DD devices, the dropout voltage test condition leads to a V SUP below the min V SUP threshold (4.0 V). As a result, the dropout voltage parameter cannot be specified. 24. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance. NXP Semiconductors 19

20 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Voltage regulator for CAN interface supply, 5.0 VCAN pin 5V C OUT Output voltage, V SUP/2 = 5.5 to 40 V I OUT 0 to 160 ma V 5V C ILIM Output Current limitation ma (25) 5V C UV Undervoltage threshold V 5V CTS Thermal shutdown (Guaranteed by design) 160 C C EXTCAN External capacitance (Guaranteed by design) μf V auxiliary output, 5.0 and 3.3 V selectable pin VBAux, VCAux, Vaux V AUX VAUX output voltage V AUX = 5.0 V, V SUP = V SUP2 5.5 to 40 V, I OUT 0 to 150 ma V AUX = 3.3 V, V SUP = V SUP2 5.5 to 40 V, I OUT 0 to 150 ma V V AUXUVTH VAUX undervoltage detector (VAUX configured to 5.0 V) Low Threshold Hysteresis VAUX undervoltage detector (VAUX configured to 3.3 V, default value) V V AUXILIM VAUX overcurrent threshold detector V AUX set to 3.3 V V AUX set to 5.0 V ma V AUX CAP External capacitance (Guaranteed by design) μf Undervoltage reset and reset function, pin V DD undervoltage threshold down 90% V DD (V DD 5.0 V) V V DD undervoltage threshold up 90% V DD (V DD 5.0 V) TH1 V DD undervoltage threshold down 90% V DD (V DD 3.3 V) V DD undervoltage threshold up 90% V DD (V DD 3.3 V) V (26), (28) (26), (28) V TH25 V DD undervoltage reset threshold down 70% V DD (V DD 5.0 V) V (27), (28) V HYST Hysteresis for threshold 90% V DD, 5.0 V device for threshold 70% V DD, 5.0 V device mv Hysteresis 3.3 V V DD for threshold 90% V DD, 3.3 V device V LP V DD undervoltage reset threshold down LP V DD ON mode (Note: device change to Normal Request mode). V DD 5.0 V (Note: device change to Normal Request mode). V DD 3.3 V V V OL Reset V 1.5 ma, V SUP 5.5 to 28 V mv I RESET LOW Current limitation, Reset activated, V RESET = 0.9 x V DD ma R PULLUP Pullup resistor (to VDD pin) kω Notes 25. Current limitation will be reported by setting a flag. 26. Generate a Reset or an INT. SPI programmable 27. Generate a Reset 28. In NonLP modes 20 NXP Semiconductors

21 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Undervoltage reset and reset function, PIN (continued) V SUPL V SUP to guaranteed reset low level 2.5 V (29) V VTH Reset input threshold Low threshold, V DD = 5.0 V High threshold, V DD = 5.0 V Low threshold, V DD = 3.3 V High threshold, V DD = 3.3 V V HYST Reset input hysteresis V I/O pins when function selected is output V I/O0 HSDRP I/O0 HS switch I = 12 ma, V SUP = 10.5 V V V I/O23 HSDRP I/O2 and I/O3 HS switch I = 20 ma, V SUP = 10.5 V V V I/O1 HSDRP I/O1, HS switch I = 400 μa, V SUP = 10.5 V V V I/O01 LSDRP I/O0, I/O1 LS switch I = 400 μa, V SUP = 10.5 V V I I/O_LEAK Leakage current, I/Ox V SUP μa I/O pins when function selected is input V I/O_NTH Negative threshold V V I/O_PTH Positive threshold V V I/O_HYST Hysteresis V I I/O_IN Input current, I/O VSUP/ μa R I/OX VSENSE input V SENSE_TH R VSENSE Notes 29. Reset must be kept low I/O0 and I/O1 input resistor. I/O0 (or I/O1) selected in register, 2.0 V < V I/OX <16 V (Guaranteed by design). VSENSE undervoltage threshold (Not active in LP modes) Low Threshold High threshold Hysteresis Input resistor to GND. In all modes except in LP modes. (Guaranteed by design) kω kω V V NXP Semiconductors 21

22 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Analog MUX output V OUT_MAX Output Voltage Range, with external resistor to GND >2.0 kω 0.0 V DD 0.5 V R MI Internal pulldown resistor for regulator output current sense kω C MUX External capacitor at MUX OUTPUT (Guaranteed by design) 1.0 nf (30) TEMP COEFF Chip temperature sensor coefficient (Guaranteed by design and device characterization) V DD = 5.0 V V DD = 3.3 V mv/ C V TEMP Chip temperature: MUXOUT voltage V DD = 5.0 V, T A = 125 C V DD = 3.3 V, T A = 125 C V V TEMP(GD) Chip temperature: MUXOUT voltage (guaranteed by design and characterization) T A = 40 C, V DD = 5.0 V T A = 25 C, V DD = 5.0 V T A = 40 C, V DD = 3.3 V T A = 25 C, V DD = 3.3 V V V SENSE GAIN Gain for V SENSE, with external 1.0 k 1% resistor V DD = 5.0 V V DD = 3.3 V V SENSE OFFSET Offset for V SENSE, with external 1.0 k 1% resistor mv V SUP/1 RATIO Divider ratio for V SUP/1 V DD = 5.0 V V DD = 3.3 V VI/O RATIO Attenuation/Gain ratio for I/O0 and I/O1 actual voltage: V DD = 5.0 V, I/O = 16 V (Attenuation, MUXOUT register bit 3 set to 1) V DD = 5.0 V, (Gain, MUXOUT register bit 3 set to 0) V DD = 3.3 V, I/O = 16 V (Attenuation, MUXOUT register bit 3 set to 1) V DD = 3.3 V, (Gain, MUXOUT register bit 3 set to 0) V REF Internal reference voltage V DD = 5.0 V V DD = 3.3 V V I DD_RATIO Current ratio between VDD output & I OUT at MUXOUT (I OUT at MUXOUT = I DD out / I DD_RATIO ) At I OUT = 50 ma I _OUT from 25 to 150 ma SAFE output V OL SAFE low level, at I = 500 μa V I SAFEIN Safe leakage current (V DD low, or device unpowered). V SAFE 0 to 28 V. Notes 30. When C is higher than CMUX, a serial resistor must be inserted μa 22 NXP Semiconductors

23 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Interrupt V OL Output low voltage, I OUT = 1.5 ma V R PU Pullup resistor kω V OHLPVDDON Output high level in LP V DD ON mode (Guaranteed by design) V V MAX Leakage current INT voltage = 10 V (to allow highvoltage on MCU INT pin) μa I SINK Sink current, V INT > 5.0 V, INT low state ma MISO, MOSI, SCLK, CS pins V OL Output low voltage, I OUT = 1.5 ma (MISO) 1.0 V V OH Output high voltage, I OUT = 0.25 ma (MISO) V DD 0.9 V V IL Input low voltage (MOSI, SCLK,CS) 0.3 x V DD V V IH Input high voltage (MOSI, SCLK,CS) 0.7 x V DD V I HZ Tristate leakage current (MISO) μa I PU Pullup current (CS) μa CAN logic input pins (TXD) V IH High Level Input Voltage 0.7 x V DD V DD V V IL Low Level Input Voltage x V DD V I PDWN Pullup Current, TXD, V IN = 0 V V DD = 5.0 V V DD = 3.3 V CAN data output pins (RXD) VOUT LOW VOUT HIGH IOUT HIGH IOUT LOW Low Level Output Voltage I RXD = 5.0 ma x V DD V High Level Output Voltage I RX = 3.0 ma 0.7 x V DD V DD V High Level Output Current V RXD = V DD 0.4 V Low Level Input Current V RXD = 0.4 V µa ma ma NXP Semiconductors 23

24 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes CAN output pins (CANH, CANL) V COM Bus pins common mode voltage for full functionality V V CANHVCANL Differential input voltage threshold mv V DIFFHYST Differential input hysteresis 50 mv R IN Input resistance kω R INDIFF Differential input resistance kω R INMATCH Input resistance matching % CANH output voltage (45 Ω < R BUS < 65 Ω) V CANH TXD dominant state TXD recessive state CANL output voltage (45 Ω < R BUS < 65 Ω) V CANL TXD dominant state TXD recessive state Differential output voltage (45 Ω < R BUS < 65 Ω) V OH V OL TXD dominant state TXD recessive state I CANH CAN H output current capability Dominant state 30 ma I CANL CAN L output current capability Dominant state 30 ma I CANLOC CANL overcurrent detection Error reported in register ma I CANHOC CANH overcurrent detection Error reported in register ma R INSLEEP CANH, CANL input resistance to GND, device supplied, CAN in Sleep mode, V_CANH, V_CANL from 0 to 5.0 V kω V CANLP CANL, CANH output voltage in LP V DD OFF and LP V DD ON modes V I CANUN_SUP1 CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device unpowered (VSUP, VDD, 5VCAN: open) µa (31) I CANUN_SUP2 CANH, CANL input current, VCANH, VCANL = 2.0 to 7.0 V, device unpowered (VSUP, VDD, 5VCAN: open). 250 µa (31) V DIFFRLP Differential voltage for recessive bit detection in LP mode 0.4 V (32) V DIFFDLP Differential voltage for dominant bit detection in LP mode 1.15 V (32) CANH and CANL diagnostic information V LG CANL to GND detection threshold V V HG CANH to GND detection threshold V V LVB CANL to VBAT detection threshold, V SUP/1 and V SUP2 > 8.0 V V SUP 2.0 V V HVB CANH to VBAT detection threshold, V SUP/1 and V SUP2 > 8.0 V V SUP 2.0 V V L5 CANL to VDD detection threshold 4.0 V DD 0.43 V V H5 CANH to VDD detection threshold 4.0 V DD 0.43 V Notes 31. VSUP, VDD, 5VCAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization. 32. Guaranteed by design and device characterization. V V V 24 NXP Semiconductors

25 ELECTRICAL CHARACTERISTICS Table 6. Static electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. SPLIT Symbol Characteristic Min. Typ. Max. Unit Notes V SPLIT I LSPLIT Output voltage Loaded condition I SPLIT = ±500 µa Unloaded condition Rmeasure > 1.0 MΩ Leakage current 12 V < V SPLIT < +12 V 22 to 12 V < V SPLIT < +12 to +35 V 0.3 x V DD 0.5 x V DD 0.7 x V DD V 0.45 x V DD 0.5 x V DD 0.55 x V DD µa LIN terminals (LINT/1, LINT2) V LT_HSDRP LINT1, LINT2, HS switch I = 20 ma, V SUP > 10.5 V V LIN1 & LIN D/5D pin LIN 33903S/5S pin (parameters guaranteed for V SUP/1, V SUP2 7.0 V V SUP 18 V) V BAT Operating Voltage Range V V SUP Supply Voltage Range V I BUS_LIM I BUS_PAS_DOM Current Limitation for Driver Dominant State Driver ON, V BUS = 18 V Input Leakage Current at the receiver Driver off; V BUS = 0 V; V BAT = 12 V ma 1.0 ma I BUS_PAS_REC Leakage Output Current to GND Driver Off; 8.0 V < V BAT < 18 V; 8.0 V < V BUS < 18 V; V BUS V BAT 20 µa I BUS_NO_GND I BUSNO_BAT Control unit disconnected from ground (Loss of local ground must not affect communication in the residual network) GND DEVICE = V SUP ; V BAT = 12 V; 0 < V BUS < 18 V (Guaranteed by design) V BAT Disconnected; V SUP_DEVICE = GND; 0 < V BUS < 18 V (Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition). (Guaranteed by design) ma 100 µa V BUSDOM Receiver Dominant State 0.4 V SUP V BUSREC Receiver Recessive State 0.6 V SUP V BUS_CNT V HYS Receiver Threshold Center (V TH_DOM + V TH_REC )/2 Receiver Threshold Hysteresis (V TH_REC V TH_DOM ) V SUP V SUP V BUSWU LIN Wakeup threshold from LP V DD ON or LP V DD OFF mode V R SLAVE LIN Pullup Resistor to V SUP kω T LINSD Overtemperature Shutdown (Guaranteed by design) C T LINSD_HYS Overtemperature Shutdown Hysteresis (Guaranteed by design) 10 C NXP Semiconductors 25

26 ELECTRICAL CHARACTERISTICS 5.3 Dynamic electrical characteristics Table 7. Dynamic electrical characteristics Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. SPI timing Symbol Characteristic Min. Typ. Max. Unit Notes FREQ SPI Operation Frequency (MISO cap = 50 pf) MHz t PCLK SCLK Clock Period 250 N/A ns t WSCLKH SCLK Clock High Time 125 N/A ns t WSCLKL SCLK Clock Low Time 125 N/A ns t LEAD Falling Edge of CS to Rising Edge of SCLK C and D versions All others N/A N/A ns t LEAD Falling Edge of CS to Rising Edge of SCLK when CS_low flag is set to 1 C and D versions All others μs t LAG Falling Edge of SCLK to Rising Edge of CS 30 N/A ns t SISU MOSI to Falling Edge of SCLK 30 N/A ns t SIH Falling Edge of SCLK to MOSI 30 N/A ns t RSO MISO Rise Time (CL = 50 pf) 30 ns t FSO MISO Fall Time (CL = 50 pf) 30 ns t SOEN t SODIS Time from Falling to MISO Lowimpedance Time from Rising to MISO Highimpedance ns t VALID Time from Rising Edge of SCLK to MISO Data Valid 30 ns t CSLOW Delay between falling and rising edge on CS C and D versions All others N/A N/A μs t CSTO CS Chip Select Low Timeout Detection 2.0 ms Supply, voltage regulator, reset t VS_LOW1/2_DGLT V SUP undervoltage detector threshold deglitcher μs t RISEON Rise time at turn ON. V DD from 1.0 to 4.5 V. 2.2 μf at the VDD pin μs t DGLT Deglitcher time to set pin low μs Reset pulse duration t PULSE V DD undervoltage (SPI selectable) short, default at power on when BATFAIL bit set medium medium long long ms t WD Watchdog reset ms I/O input t IODT Deglitcher time (Guaranteed by design) μs VSENSE input t BFT Undervoltage deglitcher time μs 26 NXP Semiconductors

27 ELECTRICAL CHARACTERISTICS Table 7. Dynamic electrical characteristics (continued) Characteristics noted under conditions 5.5 V V SUP 28 V, 40 C T A 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 C under nominal conditions, unless otherwise noted. Interrupt Symbol Characteristic Min. Typ. Max. Unit Notes t INTPULSE INT pulse duration (refer to SPI for selection. Guaranteed by design) short (25 to 125 C) short (40 C) long (25 to 125 C) long (40 C) μs State diagram timings t D_NM t TIMINGACC Delay for SPI Timer A, Timer B or Timer C write command after entering Normal mode (No command should occur within t D_NM. t D_NM delay definition: from CS rising edge of Go to Normal mode (i.e. 0x5A00) command to CS falling edge of Timer write command) Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period and active time, Cyclic Interrupt period, LP mode overcurrent (unless otherwise noted) 60 μs % (36) CAN dynamic characteristics t DOUT TXD Dominant State Timeout µs t DOM Bus dominant clamping detection µs t LRD Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate) ns t TRD Propagation delay TXD to CAN, recessive to dominant ns t RRD Propagation delay CAN to RXD, recessive to dominant ns t LDR Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate) ns t TDR Propagation delay TXD to CAN, dominant to recessive ns t RDR Propagation delay CAN to RXD, dominant to recessive ns t LOOPMSL Loop time TXD to RXD, Medium Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive ns t LOOPSSL Loop time TXD to RXD, Slow Slew Rate (Selected by SPI) Recessive to Dominant Dominant to Recessive ns t CANWU1F CAN Wakeup filter time, single dominant pulse detection (See Figure 35) μs t CANWU3F CAN Wakeup filter time, 3 dominant pulses detection 300 ns (33) (34) t CANWU3TO CAN Wakeup filter time, 3 dominant pulses detection timeout (See Figure 36) 120 μs (35) Notes 33. No Wakeup for single pulse shorter than t CANWU1 min. Wakeup for single pulse longer than t CANWU1 max. 34. Each pulse should be greater than t CANWU3F min. Guaranteed by design, and device characterization. 35. The 3 pulses should occur within t CANWU3TO. Guaranteed by design, and device characterization. 36. Guaranteed by design. NXP Semiconductors 27