Overarching Theme for Today

Transcription

1 CS 6C: Great Ideas in Computer Architecture (Machine Structures) Virtual Management Instructors: Randy H. Katz David A. PaGerson hgp://inst.eecs.berkeley.edu/~cs6c/sp 4/8/ Spring - - Lecture #4 New- School Machine Structures Big Idea: Hierarchy Parallel Requests Assigned to computer e.g., Search Katz Parallel Threads Assigned to core e.g., Lookup, Ads So8ware Parallel InstrucYons > one Yme e.g., 5 pipelined instrucyons Parallel Data > data one Yme e.g., Add of 4 pairs of words Hardware descripyons All one Yme Harness Parallelism & Achieve High Performance Hardware Warehouse Scale Computer Virtual Core Input/Output InstrucYon Unit(s) Main Computer (Cache) Core Core FuncYonal Unit(s) A +B A +B A +B A +B Today s Lecture Smart Phone Logic Gates Overarching Theme for Today Any problem in computer science can be solved by an extra level of indireccon. Ofen agributed to Butler Lampson (Berkeley PhD and Professor, Turing Award Winner), who in turn, agributed it to David Wheeler, a BriYsh computer scienyst, who also Butler Lampson said except for the problem of too many layers of indireccon! 4 HW ProtecYon Virtual Another View of Virtual HW ProtecYon Virtual Another View of Virtual 5 6

2 Review: C Management ~ FFFF FFFF C has three pools of data hex (+ ) StaYc storage: global variable storage, basically permanent, enyre program run The Stack: local variable storage, parameters, return address The Heap (dynamic storage): malloc() grabs space from here, free() returns it Common (Dynamic) Problems Using uniniyalized values Accessing beyond your allocated region Improper use of free/realloc by messing with the pointer handle returned by malloc leaks: mismatched malloc/free pairs prevents accesses between and 7 (via virtual ) Simplest Model Only one program running on the computer es in the program are exactly the physical addresses Extensions to the simple model: What if less physical than full address space? What if we want to run mulyple programs at the same Yme? 8 Problem #: Physical Less Than the Full One architecture, many implementayons, with possibly different amounts of used to very expensive and physically bulky Where does the grow from then? Logical Virtual 9 Real Idea: Level of IndirecYon to Create Illusion of Large Physical Hi Order Bits of Virtual Map or Table Hi Order Bits of Physical Logical Virtual Physical Real Virtual Page Page Problem #: MulYple Programs Sharing the Machine s How can we run mulyple programs without accidentally stepping on same addresses? How can we protect programs from clobbering each other? ApplicaYon ApplicaYon Idea: Level of IndirecYon to Create Illusion of Separate s One table per running applicayon OR Real swap table contents when switching

3 Extension to the Simple Model MulYple programs sharing the same address space E.g., OperaYng system uses low end of address range shared with applicayon MulYple programs in shared (virtual) address space StaYc management: fixed paryyoning/allocayon of space Dynamic management: programs come and go, take different amount of Yme to execute, use different amounts of How can we protect programs from clobbering each other? How can we allocate to applicayons on demand? (4 GB - 64 MB) ~ hex ~ FFF FFFF hex 8 bytes (64 MB) StaYc Division of Shared ApplicaYon OperaYng System E.g., how to manage the carving up of the address space among and applicayons? Where does the end and the applicayon begin? Dynamic management, with protecyon, would be beger! 4 First Idea: Base + Bounds Registers for LocaYon Independence LocaYon- independent programs Programming and storage management ease: need for a base register ProtecYon Independent programs should not affect each other inadvertently: need for a bound register Historically, base + bounds registers were a very early idea in computer architecture Max addr addr prog prog 5 Physical Simple Base and Bound TranslaYon lw X Bound Register EffecYve Segment Length Base Register Base Physical Program Base and bounds registers are visible/accessible to programmer Trap to if bounds violayon detected ( seg fault / core dumped ) 6 + Bounds ViolaYon? Physical current segment Physical pgm pgm pgm K Programs Sharing pgms 4 & 5 arrive pgm pgm pgm 4 pgm pgm 5 8K K pgms & 5 leave Why do we want to run mulyple programs? Run others while waicng for I/O What prevents programs from accessing each other s data? pgm pgm 4 pgm 8K K free 7 RestricYon on Base + Bounds Regs Want only the OperaYng System to be able to change Base and Bound Registers Processors need different execuyon modes. User mode: can use Base and Bound Registers, but cannot change them. Supervisor mode: can use and change Base and Bound Registers Also need Mode Bit (=User, =Supervisor) to determine processor mode Also need way for program in User Mode to invoke operayng system in Supervisor Mode, and vice versa 8

4 pgm pgm pgm Programs Sharing K pgms 4 & 5 arrive pgm pgm pgm 4 pgm pgm 5 8K K pgms & 5 leave pgm pgm 4 pgm As programs come and go, the storage is fragmented. Therefore, at some stage programs have to be moved around to compact the storage. Easy way to do this? 8K K free HW ProtecYon Virtual Another View of Virtual 9 Administrivia Administrivia Extra Credit due 4/4 Fastest Matrix MulYply EC not limited to three fastest projects! You get EC for % improvement over your Project # Submit working if your Project # did not work FF Grading of Project #4 in Lab this week Final Review: Mon 5/, 5 8PM, 5 VLSB Final Exam: Mon 5/9, :- :PM, Haas Pavilion Designed for 9 minutes, you will have hours Comprehensive (parycularly problem areas on midterm), but focused on course since midterm: lecture, lab, hws, and projects are fair game 8 ½ inch x inch crib sheet like midterm hgp:// professor- meme// HW ProtecYon Virtual Another View of Virtual Idea #: s to Avoid FragmentaYon Divide address space into equal sized blocks, called pages TradiYonally 4 KB or 8 KB Use a level of indireccon to map program addresses into addresses One indirecyon mapping per address space page This table of mappings is called a page table 4 4

5 Paged Systems Processor- generated address is split into: Virtual page number bits bits Page table contains the physical address of the base of each page: Program consists of 4x 4K Byte pages or 684 Bytes (think of an array of base registers or pointers) Page tables make it possible to store the pages of a program non- concguously. - bit byte address 496 byte pages Physical 5 Pgm Pgm Pgm Separate per Program VA VA VA Each program has own page table Page table contains an entry for each program page pages free Physical 6 Paging Terminology Program addresses called virtual addresses of all virtual addresses called virtual addresses called physical addresses of all physical addresses called physical 7 Processes and Virtual Allow mulyple processes to simultaneously occupy and provide protecyon don t let one program read/write from another Each has own PC,, Like threads, except processes have separate address spaces space give each program the illusion that it has its own private Suppose starts at address x4. But different processes have different, both residing at the same (virtual) address. So each program has a different view of. 8 Combine Idea # and Idea #: ProtecYon via Access Rights checked on every access to see if allowed Read: can read, but not write page Read/Write: read or write data on page Execute: Can fetch instrucyons from page Valid = Valid page table entry 9 More Depth on s Virtual : Base Reg page no. bits index into page table... V A.R. P. P. A. Val - id Access Rights.... bits Physical Page located in physical + Physical 5

6 TranslaYon & ProtecYon Kernel/User Mode Read/Write ExcepYon? Virtual ProtecYon Check Physical Virtual Page No. (VPN) TranslaYon Physical Page No. (PPN) Every instrucyon and data access needs address translayon and protecyon checks PaGerson s Analogy Book Ytle like virtual address Library of Congress call number like physical address Card catalogue like page table, mapping from book Ytle to call # On card, available for - hour in library use (vs. - week checkout) like access rights Where Should s Reside? required by the page tables is proporyonal to the address space, number of users, requirement is large: e.g., byte address space, byte pages = table entries = 4 x 4 entries (per program!) How many bits per page table entry? Too expensive to keep in processor registers! Where Should s Reside? Idea: Keep page tables in the main One reference to retrieve the page base address from table in Second access to retrieve the data word Doubles the number of references! Why is this bad news? 4 VA s Can Be HUGE: Put Them In Physical User Virtual VA User Virtual PT User PT User Physical 5 Virtual Without Doubling Accesses Caches suggest that there is temporal and spayal locality of data Locality of data really means locality of addresses of that data What about locality of translayons of virtual page addresses into physical page addresses? For historical reasons, called TranslaCon Lookaside Buffer (TLB) More accurate name is Cache 6 6

7 HW ProtecYon Virtual Another View of Virtual TranslaYon Lookaside Buffers (TLB): Another Layer of IndirecYon! translayon is very expensive! Each reference becomes accesses SoluYon: Cache address translacons in TLB! TLB hit Single Cycle TranslaCon TLB miss Access Page- Table to refill V R W X tag hit? PPN virtual address VPN (VPN = virtual page number) (PPN = physical page number) physical address PPN 7 8 TLB Design Typically - 8 entries Usually fully associayve: why wouldn t direct mapped work? 9 Historical RetrospecYve: 96 versus used to be very expensive, and amount available to the processor was highly limited Now is c: approx $ per GByte in April Many apps data could not fit in main, e.g., payroll Paged system reduced fragmentayon but syll required whole program to be resident in the main For good performance, buy enough to hold your apps Programmers moved the data back and forth from the diskstore by overlaying it repeatedly on the primary store Programmers no longer need to worry about this level of detail anymore 4 Demand Paging in Atlas (96) A page from secondary storage is brought into the primary storage whenever it is (implicitly) demanded by the processor. Tom Kilburn Primary as a cache for secondary User sees x 6 x 5 words of storage Primary Pages 5 words/page Central Secondary (~disk) x6 pages Demand Paging Scheme On a page fault: Input transfer into a free page is iniyated If no free page available, a page is selected to be replaced (based on usage) Replaced page is wrigen on the disk To minimize disk latency effect, the first empty page on the disk was selected Page table is updated to point to the new locayon of the page on the disk 4 4 7

8 Notes on Solves the fragmentayon problem: all chunks same size, so any holes can be used must reserve Swap on disk for each process To grow a process, ask OperaYng System If unused pages available, uses them first If not, swaps some old pages to disk (Least Recently Used to pick pages to swap) How/Why grow a process? 44 Impact on TLB Keep track of whether page needs to be wrigen back to disk if its been modified Set Page Dirty Bit in TLB when any data in page is wrigen When TLB entry replaced, corresponding Page Dirty Bit is set in Entry 45 Hardware/Sofware Support for ProtecYon Different tasks can share parts of their virtual address spaces But need to protect against errant access Requires assistance Hardware support for protecyon Privileged supervisor mode (aka kernel mode) Privileged instrucyons Page tables and other state informayon only accessible in supervisor mode System call excepyon (e.g., syscall in MIPS) Modern Virtual Systems Illusion of a large, private, uniform store ProtecYon & Privacy Several users, each with their private address and one or more shared address spaces page table name space Demand Paging Provides ability to run programs larger than the primary Hides differences in machine configurayons Price is address translacon on each reference; But disk so slow that performance suffers if going to disk all the Cme ( thrashing ) Spring 4/8/ - - Lecture # user i Primary VA Mapping Swapping Store PA HW ProtecYon Virtual Another View of Virtual 4/8/ 48 Spring - - Lecture #4 49 8

9 HW ProtecYon Virtual Another View of Virtual Another View of Virtual : Just Another Part of Hierarchy Use main as a cache for secondary (disk) storage Managed jointly by CPU hardware and the operayng system () Programs share main Each gets a private virtual address space holding its frequently used and data Protected from other programs CPU and translate virtual addresses to physical addresses VM block is called a page VM translayon miss is called a page fault 5.4 Virtual 5 5 Just Another View of Hierarchy Virtual { Regs Instr. Operands Cache Blocks L Cache Blocks Pages Disk Files Tape Upper Level Faster Larger Lower Level Caching vs. Demand Paging 5 5 CPU cache primary CPU primary secondary Caching Demand paging cache entry page frame cache block (~ bytes) page (~4K bytes) cache miss rate (% to %) page miss rate (<.%) cache hit (~ cycle) page hit (~ cycles) cache miss (~ cycles) page miss (~5M cycles) a miss is handled a miss is handled in hardware mostly in so8ware TranslaYon: Pu~ng it all Together Restart instrucyon Page Fault ( loads page) Walk miss Virtual TLB Lookup Update TLB ProtecYon Check the page is denied permiged Physical (to cache) SEGFAULT 54 hit ProtecYon Fault hardware hardware or sofware sofware TranslaYon in CPU Pipeline PC Inst TLB TLB miss? Page Fault? ProtecCon violacon? Inst. Cache D De E + M Data TLB Data Cache Sofware handlers need restartable excepyon on TLB fault Handling a TLB miss needs a hardware or so8ware mechanism to refill TLB Need mechanisms to cope with the addiyonal latency of a TLB: Slow down the clock Pipeline the TLB and cache access Virtual address caches (indexed with virtual addresses) Parallel TLB/cache access TLB miss? Page Fault? ProtecCon violacon? W 55 9

10 VA PA Concurrent Access to TLB & Cache VPN L b PPN Tag TLB Physical Tag hit? Index L is available without consulyng the TLB cache and TLB accesses can begin simultaneously Tag comparison is made afer both accesses are completed Cases: L + b = k L + b < k L + b > k Page Offset Direct- map Cache L blocks b - byte block 56 k = Virtual Index Data Impact of Paging on AMAT Parameters: L cache hit = clock cycles, hit 95% of accesses L cache hit = clock cycles, hit 6% of L misses DRAM = clock cycles (~ nanoseconds) Disk =,, clock cycles (~ milliseconds) Average Access Time (with no paging): + 5%* + 5%*4%* = 5.5 clock cycles Average Access Time (with paging) = AMAT (with no paging) +? 5.5 +? 57 Modern Management Slowdown too great to run much bigger programs than Called Thrashing Buy more or run program on bigger computer or reduce size of problem Paging system today syll used for TranslaCon (mapping of virtual address to physical address) ProtecCon (permission to access word in ) Sharing of between independent tasks Impact of TLBs on Performance Each TLB miss to ~ L Cache miss Page sizes are 4 KB to 8 KB (4 KB on x86) TLB has typically 8 entries Set AssociaYve or Fully AssociaYve TLB Reach: Size of largest virtual address space that can be simultaneously mapped by TLB: 8 * 4 KB = 5 KB =.5 MB! What can you do to have becer performance? 59 6 Nehalem Virtual Details 48- bit virtual address space, 4- bit physical address space Two- level TLB: L + L I- TLB (L) has shared 8 entries 4- way associayve for 4KB pages, plus 7 dedicated fully- associayve entries per SMT thread for large page (/4MB) entries D- TLB (L) has 64 entries for 4KB pages and entries for /4MB pages, both 4- way associayve, dynamically shared between SMT threads Unified L TLB has 5 entries for 4KB pages only, also 4- way associayve Data TLB Reach (4 KB only) L: 64*4 KB =.5 MB, L:5*4 KB= MB (superpages) L: *- 4 MB = 64-8 MB Using Large Pages from ApplicaYon? Difficulty is communicayng from applicayon to operayng system that want to use large pages Linux: Huge pages via a library file system and mapping; beyond 6C See hgp://lwn.net/arycles/7596/ hgp:// display/linuxp/libhuge+short+and+simple Max X: no support for applicayons to do this ( decides if should use or not) 4/8/ Spring Lecture #4 6

11 TranslaYon & ProtecYon Kernel/User Mode Read/Write Excep<on? Virtual ProtecYon Check Physical Virtual Page No. (VPN) TranslaYon Physical Page No. (PPN) Every instruccon and data access needs address translayon and protecyon checks Good VM design needs to be fast (~ one cycle) and space efficient And in Conclusion, Separate Management into orthogonal funcyons: TranslaCon (mapping of virtual address to physical address) ProtecCon (permission to access word in ) But most modern systems provide support for all funcyons with single page- based system All desktops/servers have full demand- paged virtual Portability between machines with different sizes ProtecYon between mulyple users or mulyple tasks Share small physical among acyve tasks Simplifies implementayon of some features Hardware support: User/Supervisor Mode, invoke Supervisor Mode, TLB, Register 64 65