CS 61C: Great Ideas in Computer Architecture (Machine Structures) Traps, Excep,ons, Virtual Machines

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1 // CS C: Great Ideas in Computer Architecture (Machine Structures) Traps, Excep,ons, Virtual Machines Instructors: Randy H. Katz David A. PaGerson hgp://inst.eecs.berkeley.edu/~csc/sp // Spring - - Lecture # // Spring - - Lecture # New- School Machine Structures Big Idea: Memory Hierarchy Parallel Requests Assigned to computer e.g., Search Katz Parallel Threads Assigned to core e.g., Lookup, Ads So?ware Parallel s > one Yme e.g., pipelined instrucyons Parallel Data > data one Yme e.g., Add of pairs of words Hardware descripyons All one Yme Harness Parallelism & Achieve High Performance Hardware Warehouse Scale Computer Virtual Memory Memory Input/Output Unit(s) Main Memory Computer (Cache) FuncYonal Unit(s) A +B A +B A +B A +B Today s Lecture Smart Phone Logic Gates // Spring - - Lecture # New- School Machine Structures Parallel Requests Assigned to computer e.g., Search Katz Parallel Threads Assigned to core e.g., Lookup, Ads So?ware Parallel s > one Yme e.g., pipelined instrucyons Parallel Data > data one Yme e.g., Add of pairs of words Hardware descripyons All one Yme Harness Parallelism & Achieve High Performance Hardware Warehouse Scale Computer Virtual Machines Traps Memory Input/Output Unit(s) Main Memory Computer (Cache) FuncYonal Unit(s) A +B A +B A +B A +B Today s Lecture Smart Phone Logic Gates // Spring - - Lecture # Revisted Revisted // Spring - - Lecture # // Spring - - Lecture #

2 // Virtual Address Space Virtual Address Space ~ hex ApplicaYon Physical Memory ~ hex ApplicaYon ~ hex ApplicaYon Stack Heap StaYc Code Physical Memory ~ hex ApplicaYon // Spring - - Lecture # // Spring - - Lecture # 8 Virtual Address Space Dynamic Memory AllocaYon ~ hex ApplicaYon Stack Heap StaYc Code Stack Heap StaYc Code Physical Memory ~ hex ApplicaYon ~ hex ApplicaYon malloc(9) Heap Stack Heap StaYc Code Stack Heap StaYc Code Physical Memory ~ hex ApplicaYon // Spring - - Lecture # 9 // Spring - - Lecture # Dynamic Memory AllocaYon Controlled Sharing ~ hex ApplicaYon malloc(9) Stack Heap Stack Heap StaYc Code Stack Heap StaYc Code Physical Memory ApplicaYon // Spring - - Lecture # ~ hex Recursive func,on call Stack Heap StaYc ~ hex Stack ~ hex Heap ApplicaYon StaYc ApplicaYon Code Physical Memory Shared Code X Protecon Bit // Spring - - Lecture #

3 // Controlled Sharing Stack Heap ~ hex Stack ~ hex Heap ApplicaYon Stac Code Shared Globals Physical Memory Shared Code RW Protecon Bits X Protecon Bit // Spring - - Lecture # ApplicaYon () Address No Cache, No // Spring - - Lecture # () Address () Address (PPN, Offset) Hit PTBR Base Register + VPN (@ Entry) (PPN, Offset) No Cache,, Hit Very Fast! If locality works, this is the most common case! // Spring - - Lecture # No Cache,,, Access NOTE: implemented before caches // Spring - - Lecture # () Address () Address PTBR Base Register + VPN (@ Entry) D$ (PPN, Offset) Hit PTBR Base Register + VPN (@ Entry) D$ Physical Data Cache,,, Access VA caches are possible, but it s complicated: see CS // Spring - - Lecture # (PPN, Offset) (@ Entry) Physical Data Cache,,, Access VA caches are possible, but it s complicated: see CS Spring - - Lecture # 8 //

4 // PTBR Base Register + () Address VPN (@ Entry) (@ Entry) D$ (PPN, Offset) Physical Data & Cache,,, Access VA caches are possible, but it s complicated: see CS // Spring - - Lecture # 9 I$ Hit PTBR Base Register + () Address VPN (@ Entry) (@ Entry) D$ (PPN, Offset) Day in the life of a data access is not too different Physical Data & Cache,,, Access // Spring - - Lecture # I$ Revisted Administrivia Extra Credit due / Fastest Matrix MulYply FF Grading of Project in Lab this week Final Review: Mon /, 8PM, VLSB Final Exam: Mon /9, :- :PM, Haas Pavilion Designed for 9 minutes, you will have hours Comprehensive (parycularly problem areas on midterm), but focused on course since midterm: lecture, lab, hws, and projects are fair game 8 ½ inch x inch crib sheet like midterm // Spring - - Lecture # // Spring - - Lecture # CSc in the News! President FB Yesterday! NVIDIA Tegra Processor with GHz Dual- core ARM Processor 8p MPEG- /H. Recording and Playback HDMI mirroring - inch WVGA screen 8- megapixel rear camera /.- megapixel front camera. muly- channel virtual surround sound 8GB memory microsd memory expandability (up to GB) Micro- USB connecyvity, mah bagery Supports Adobe Flash Player. LG OpYmus X Smart Phone Theater- quality entertainment on a mobile device It s Game Over for Single- core Smartphones. // Spring - - Lecture # // Spring - - Lecture # hgp:// facebook- program- dramaycally- cut- agencys- cos,9/

5 // Revisted // Spring - - Lecture # Historical RetrospecYve: 9 versus Memory used to be very expensive, and amount available to the processor was highly limited Now memory is c: approx $ per GByte in April Many apps data could not fit in main memory, e.g., payroll d memory system reduced fragmentayon but syll required whole program to be resident in the main memory For good performance, buy enough memory to hold your apps Programmers moved the data back and forth from the diskstore by overlaying it repeatedly on the primary store Programmers no longer need to worry about this level of detail anymore // Spring - - Lecture # Demand Paging in Atlas (9) Demand Paging Scheme A page from secondary storage is brought into the primary storage whenever it is (implicitly) demanded by the processor. Tom Kilburn Primary memory as a cache for secondary memory User sees x x words of storage Primary s words/page Central Memory Secondary (~disk) x pages On a page fault: Input transfer into a free page is iniyated If no free page available, a page is selected to be replaced (based on usage) Replaced page is wrigen on the disk To minimize disk latency effect, the first empty page on the disk was selected table is updated to point to the new locayon of the page on the disk // Spring - - Lecture # // Spring - - Lecture # 8 Impact on Keep track of whether page needs to be wrigen back to disk if it has been modified Set Dirty Bit in when any data in page is wrigen When entry replaced, corresponding Dirty Bit is set in Entry Address TranslaYon: Puxng it all Together Restart instrucyon Walk miss Virtual Address Lookup hit ProtecYon Check hardware hardware or soyware soyware the page is Memory memory denied permiged Fault (OS loads page) Update ProtecYon Fault Physical Address (to cache) // Spring - - Lecture # 9 // Spring - - Lecture # SEGFAULT

6 // Address TranslaYon in CPU Pipeline Inst miss? Fault? Protec,on viola,on? Inst. Cache D De E + M Data Data Cache Soyware handlers need restartable excepyon on fault Handling a miss needs a hardware or so?ware mechanism to refill Need mechanisms to cope with the addiyonal latency of a : Slow down the clock Pipeline the and cache access Virtual address caches (indexed with virtual addresses) Parallel /cache access // Spring - - Lecture # miss? Fault? Protec,on viola,on? W VA Concurrent Access to & Cache VPN L b PPN Tag Physical Tag hit? Index L is available without consulyng the cache and accesses can begin simultaneously Tag comparison is made ayer both accesses are completed Cases: L + b = k L + b < k L + b > k Offset Direct- map Cache L blocks b - byte block // Spring - - Lecture # k = Virtual Index Data Impact of Paging on AMAT Memory Parameters: L cache hit = clock cycles, hit 9% of accesses L cache hit = clock cycles, hit % of L misses DRAM = clock cycles (~ nanoseconds) Disk =,, clock cycles (~ milliseconds) Average Memory Access Time (with no paging): + %* + %*%* =. clock cycles Average Memory Access Time (with paging) = AMAT (with no paging) +?. +? // Spring - - Lecture # Student RouleGe? Impact of Paging on AMAT Memory Parameters: L cache hit = clock cycles, hit 9% of accesses L cache hit = clock cycles, hit % of L misses DRAM = clock cycles (~ nanoseconds) Disk =,, clock cycles (~ milliseconds) Average Memory Access Time (with paging) =. + %*%*(- HitMemory)*,, AMAT if HitMemory = 99.9%?. +. *. *,, =. AMAT if HitMemory = %. +. *. *,, =.9 // Spring - - Lecture # Revisted ExcepYons and Interrupts Unexpected events requiring change in flow of control Different ISAs use the terms differently ExcepYon Arises within the CPU e.g., Undefined op, overflow, syscall, Interrupt From an external I/O controller Dealing with them without sacrificing performance is difficult.9 ExcepYons // Spring - - Lecture # // Spring - - Lecture #

7 // Handling ExcepYons In MIPS, excepyons managed by a System Control Coprocessor (CP) Save of offending (or interrupted) instrucyon In MIPS: save in special register called Excep,on Program Counter (E) Save indicayon of the problem In MIPS: saved in special register called Cause register We ll assume - bit for undefined op, for overflow Jump to excepyon handler at address 8 8 hex ExcepYon ProperYes Restartable excepyons Pipeline can flush the instrucyon Handler executes, then returns to the instrucyon Refetched and executed from scratch saved in E register IdenYfies causing instrucyon Actually + is saved because of pipelined implementayon Handler must adjust to get right address // Spring - - Lecture # // Spring - - Lecture # 8 Handler AcYons Read Cause register, and transfer to relevant handler Determine acyon required If restartable excepyon Take correcyve acyon use E to return to program Otherwise Terminate program Report error using E, cause, ExcepYons in a Pipeline Another kind of control hazard Consider overflow on add in EX stage add $, $, $ Prevent $ from being clobbered Complete previous instrucyons Flush add and subsequent instrucyons Set Cause and E register values Transfer control to handler Similar to mispredicted branch Use much of the same hardware // Spring - - Lecture # 9 // Spring - - Lecture # ExcepYon Example ExcepYon on add in sub $, $, $ and $, $, $ 8 or $, $, $ C add $, $, $ slt $, $, $ lw $, ($) 8 lui $, Handler 88 sw $, ($) 88 sw $, ($) I n s t r. O r d e r and or add slt lw lui ExcepYon Example Time (clock cycles) I$ Reg D$ Reg // Spring - - Lecture # // Spring - - Lecture #

8 // I and n s or Flush t add, slt, lw r. (bubble) O r d e r (bubble) (bubble) sw ExcepYon Example Time (clock cycles) I$ st instruc,on of handler Save + into E Reg D$ Reg MulYple ExcepYons Pipelining overlaps mulyple instrucyons Could have mulyple excepyons at once E.g., fault in LW same clock cycle as Overflow of following instrucyon ADD Simple approach: deal with excepyon from earliest instrucyon, e.g., LW excepyon serviced st Flush subsequent instrucyons Called Precise excepyons In complex pipelines: MulYple instrucyons issued per cycle Out- of- order compleyon Maintaining precise excepyons is difficult! // Spring - - Lecture # // Spring - - Lecture # Imprecise ExcepYons Just stop pipeline and save state Including excepyon cause(s) Let the soyware handler work out Which instrucyon(s) had excepyons Which to complete or flush May require manual compleyon Simplifies hardware, but more complex handler soyware Not feasible for complex mulyple- issue out- of- order pipelines to always get exact instrucyon All computers today offer precise excepyons affects performance though Revisted // Spring - - Lecture # // Spring - - Lecture # Revisted // Spring - - Lecture # // Spring - - Lecture # 8 8

9 // Beyond Even greater protecyon than virtual memory E.g., Amazon Web Services allows independent tasks run on same computer Can a small operayng system simulate the hardware of some machine, so that Another operayng system can run in that simulated hardware? More than one instance of that operayng system run on the same hardware at the same Yme? More than one different operayng system can share the same hardware at the same Yme? Answer: Yes SoluYon Virtual Machine A virtual machine provides interface iden,cal to underlying bare hardware I.e., all devices, interrupts, memory, page tables, etc. VirtualizaYon has some performance impact Feasible with modern high- performance computers Examples IBM VM/ (9s technology!) VMWare Xen (used by AWS) Microsoy Virtual // Spring - - Lecture # 9 // Spring - - Lecture # Randy s Personal Experience VM/, circa 9 Summer CoNY Dept Welfare Service VM/: allows programmer to write channel programs, basically machine instrucyons (CCW channel control words) to directly control I/O devices Let s try to ring the computer s console bell Terminal log prints out the following:!!!!rrrr...ring...gggg!!!! Virtual Machines Host Opera,ng System: OS actually running on the hardware Together with virtualiza,on layer, it simulates environment for Guest Opera,ng System: OS running in the simulated environment The resources of the physical computer are shared to create the virtual machines Processor scheduling by OS can create the appearance that each user has own processor Disk paryyoned to provide virtual disks // Spring - - Lecture # // Spring - - Lecture # Virtual Machine Monitor Maps virtual resources to physical resources Memory, I/O devices, CPUs Guest runs on nayve machine in user mode Traps to VMM on privileged instrucyons and access to protected resources Guest OS may be different from host OS VMM handles real I/O devices Emulates generic virtual I/O devices for guest Example: Timer VirtualizaYon In nayve machine, on Ymer interrupt OS suspends current process, handles interrupt, selects and resumes next process With Virtual Machine Monitor VMM suspends current VM, handles interrupt, selects and resumes next VM If a VM requires Ymer interrupts VMM emulates a virtual Ymer Emulates interrupt for VM when physical Ymer interrupt occurs // Spring - - Lecture # // Spring - - Lecture # 9

10 // Virtual Machine Set Support Similar to what need for User and System modes Privileged instrucyons only available in system mode Trap to system if executed in user mode All physical resources only accessible using privileged instrucyons Including page tables, interrupt controls, I/O registers Renaissance of virtualizayon support Current ISAs (e.g., x8) adapyng, following IBM s path Revisted Spring - - Lecture # // // Spring - - Lecture # And in Conclusion,, Paging really used for ProtecYon, TranslaYon, Some OS opymizayons Not really rouynely paging to disk Can think of as another level of memory hierarchy, but not really used like caches as even greater level of protecyon to allow greater level of sharing Enables fine control, allocayon, pricing of Cloud CompuYng // Spring - - Lecture # Peer : Match the Phrase Match the memory hierarchy element on the ley with the closest phrase on the right:. L cache a. A cache for page table entries. L cache b. A cache for a main memory. Main memory c. A cache for disks. d. A cache for a cache RED) a, b, c, d ORG) a, b, d, c GRN) b, d, a, c PINK) b, d, c, a BLU) d, b, a, c PUR) d, a, b, c TEAL) d, c, b, a // Spring - - Lecture # 8 Peer : Match the Phrase Match the memory hierarchy element on the ley with the closest phrase on the right:. L cache a. A cache for page table entries. L cache b. A cache for a main memory. Main memory c. A cache for disks. d. A cache for a cache A) a, b, c, d E) b, d, c, a B) a, b, d, c F) d, b, a, c C) b, d, a, c G) d, a, b, c H) d, c, b, a // Spring - - Lecture # 9 Peer : True or False A program tries to load a word X that causes a miss but not a page fault. Which are True or False:. A miss means that the page table does not contain a valid mapping for virtual page corresponding to the address X. There is no need to look up in the page table because there is no page fault. The word that the program is trying to load is present in physical memory. RED) F, F, F ORG) F, F, T GRN) F, T, F PNK) T, F, F BLU) T, F, T PUR) T, T, F TEL) T, T, T // Spring - - Lecture #

11 // Peer : True or False A program tries to load a word X that causes a miss but not a page fault or protecyon violayons. Which are True or False:. A miss means that the page table does not contain a valid mapping for virtual page corresponding to the address X. There is no need to look up the page table because there is no page fault. The word that the program is trying to load is present in physical memory. A) F, F, F E) T, F, F B) F, F, T F) T, F, T C) F, T, F G) T, T, F H) T, T, T // Spring - - Lecture # Peer : True or False s entries have valid bits and dirty bits. Data caches have them also. A. The valid bit means the same in both: if valid =, it must miss in both s and Caches. B. The valid bit has different meanings. For caches, it means this entry is valid if the address requested matches the tag. For s, it determines whether there is a page fault (valid=) or not (valid=). C. The dirty bit means the same in both: the data in this block in the or Cache has been changed. D. The dirty bit has different meanings. For caches, it means the data block has been changed. For s, it means that the page corresponding to this entry has been changed. Red) F, T, F, T Org) F, T, T, F Grn) T, F, F, T // Spring - - Lecture # Peer : True or False s entries have valid bits and dirty bits. Data caches have them also. A. The valid bit means the same in both: if valid =, it must miss in both s and Caches. B. The valid bit has different meanings. For caches, it means this entry is valid if the address requested matches the tag. For s, it determines whether there is a page fault (valid=) or not (valid=). C. The dirty bit means the same in both: the data in this block in the or Cache has been changed. D. The dirty bit has different meanings. For caches, it means the data block has been changed. For s, it means that the page corresponding to this entry has been changed. A) F, T, F, T B) F, T, T, F C) T, F, F, T // Spring - - Lecture #