PCI Express Compiler. PCI Express Compiler Version Issues

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1 January 2007, Compiler Version Errata Sheet This document addresses known errata and documentation issues for the PCI Express Compiler version Errata are functional defects or errors, which may cause the PCI Express Compiler to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents. f For the most up-to-date errata for this release, refer to the errata page on the Altera website: PCI Express Compiler Version Issues Altera has identified the following issues that affect the PCI Express Compiler version in the following ways: Functional Issues: a defect or design issue that needs an enhancement or will be fixed in a future release Usage Issues: a process change or parameter you need to specify Documentation Issues: an addition, correction, clarification, or change to the documentation: Table 1. PCI Express Compiler v2.0.0 Issues (Part 1 of 2) Category Issue Page Functional Issues Timing Issues for PIPE Control Signals Interfacing to TI PHY 1 Reversed Polarity on Lanes Incurs Reinitialization Delay on PCI Express Link 2 More Than One PCI Express Core per Device Causes a Quartus II Fitter Error 3 VC1-3 InitFC DLLPs Sent Too Quickly Reduce Throughput 4 Expiration of replay_timer in x8 MegaCore Function Can Cause Replay Buffer 5 Overflow Stratix GX Devices Not Detected by Some PCI Express Devices 6 Example Design Using the Stratix II GX PHY Does Not Work When Compiled 7 with the Quartus II v6.1 Software x8 MegaCore Function Ignores app_msi_num and app_msi_tc Input Signals 8 Altera Corporation 1 ES-PCI

2 Table 1. PCI Express Compiler v2.0.0 Issues (Part 2 of 2) Category Issue Page Usage Issues x8 PCI MegaCore Function Supports Only Stratix II GX Devices 9 PCI Express Simulation Example Requires Testbench Code Changes to 10 Compile Successfully Multiple PCI Express MegaCore Functions Must Be the Same Width 10 Modify Rx Buffer Settings for Maximum Throughput 11 Disable Auto Configure Retry Buffer Size for Small Maximum Payload Sizes 12 Incorrect is_request Function Designation Causes Testbench Compilation 13 Failure With NCSim Compiling a VHDL Design With Multiple MegaCore Functions in Quartus II 14 Requires Each MegaCore Function Reside in a Separate Directory Add PCI Express Wrapper File When PCI Express MegaCore Resides in a 16 Directory Other Than the Quartus II Project Compilation Issues Using the ModelSim runtb.do Script 17 Packet Format Field for the Request Headers Incorrectly Documented in the 19 Documentation Issues PCI Express Compiler User Guide PCI Express User Guide Global Signal Reset Clarification 20 Lane Reversal Is Not Supported in PCI Express MegaCore Functions 22 Functional Issues This section contains functional issues which can include defects or design issues that require an enhancement or will be fixed in a future release. Timing Issues for PIPE Control Signals Interfacing to TI PHY Altera recommends that you use the 16-bit SDR 125 MHz TI PHY interface for your design. Using the 8-bit DDR 125 MHz TI PHY interface is not recommended until the next release due to the complexity of setting constraints and placing logic to meet timing requirements. This issue affects any design using the 8-bit DDR 125 MHz TI PHY interface. Timing requirements for designs using the 8-bit DDR125 MHz TI PHY interface are very difficult to meet. 2 Altera Corporation

3 Functional Issues Do not use the 8-bit DDR 125 MHz TI PHY interface until the next release of the PCI Express Compiler. Use the 16-bit SDR 125 MHz TI PHY interface for your designs. The 8-bit DDR 125 MHz TI PHY interface will be fixed in the next release of the PCI Express Compiler. Reversed Polarity on Lanes Incurs Reinitialization Delay on PCI Express Link If the serial interface has reversed polarity on the differential Rx input pins on one or more lanes and the PCI Express link is reinitialized without a link reset being applied, which is what occurs during a Recovery, then the link will not reinitialize immediately. The polarity inversion is not done correctly in the LTSSM POLLING.CONFIG state. The link reinitializes correctly after a 12ms timeout in the DETECT.QUIET. Any configuration with reversed polarity on one or more lanes is subject to this delay when reinitializing the link. Reinitializing the PCI Express link encounters an additional 12ms delay. This delay usually has little impact on the actual system operation. However, the delay can significantly extend simulation run times. Avoid using reversed polarity inputs if the reinitialization delay impacts your system design or simulation. This issue will be fixed in the next release of the PCI Express Compiler. Altera Corporation 3

4 More Than One PCI Express Core per Device Causes a Quartus II Fitter Error A Quartus II Fitter error occurs if you place two or more PCI Express cores or more than one of any other core that uses ALT2GXB in the same Stratix II GX device. This Quartus II Fitter error occurs whenever any design places two or more PCI Express or other MegaCore functions that use ALT2GXB in a Stratix II GX device in the same design. In most cases you cannot use more than one MegaCore function that uses ALT2GXB in the same Stratix II GX device. If possible, connect clk125_in on all x1 and x4 PCI Express MegaCore functions or clk250_in for x8 PCI Express MegaCore functions and the cal_blk_clk input of any other ALT2GXB instances to the same source in the design. Contact Altera if it is not possible to connect to the same clock. This issue will be fixed in the next release of the PCI Express Compiler. VC1-3 InitFC DLLPs Sent Too Quickly Reduce Throughput During initialization of virtual channels (VCs) 1-3, InitFC1 and InitFC2 DLLPs are sent back-to-back, which starves transmission of traffic for other already initialized VCs while VCs 1-3 are being initialized. Applications are affected during initialization of VCs 1-3. Throughput is greatly reduced during initialization of VCs Altera Corporation

5 Functional Issues Currently, there is no workaround. This issue will be fixed in the next release of the PCI Express Compiler. Expiration of replay_timer in x8 MegaCore Function Can Cause Replay Buffer Overflow If the replay buffer's replay_timer expires and a new packet is received on the application layer interface with specific timing and replay buffer utilization, the replay buffer can overflow and the data it contains can become corrupted. The replay_timer expires with the replay buffer full enough to cause this problem only when multiple ACKs or NAKs have not been successfully received to reset the replay_timer. The ACKs or NAKs are either not being sent by the attached port because of a malfunction, or they are all being corrupted on the link. This situation is rare. The affected configuration is a x8 MegaCore function that encounters a replay_timer expiration. The design impact is that the replay buffer overflows and becomescorrupted leading to incorrect packets being replayed. There is no workaround for this issue. This issue will be fixed in a future release of the PCI Express Compiler. Altera Corporation 5

6 Stratix GX Devices Not Detected by Some PCI Express Devices Some PCI Express devices cannot detect the Stratix GX receiver during the PCI Express receiver detection sequence. In this case the other device remains in the LTSSM Detect state and the Stratix GX device remains in the Compliance state, which prevents the link from being initialized. This occurs because Stratix GX devices do not exhibit the correct receiver impedance characteristics when the receiver input is at electrical idle. Stratix GX devices were designed before the PCI Express specification was developed. Although the Stratix II GX devices were designed to meet the PCI Express protocol and do not have this issue, Stratix II GX is one of the PCI Express devices that is unable to detect Stratix GX. This issue affects all Stratix GX PCI Express designs. Stratix GX does not interoperate with some PCI Express devices. Although there is no workaround that can fix this issue, you can use one of the following options: If possible force the other PCI Express device to ignore the results of the Rx Detect protocol and try to train the link anyway. Migrate your Stratix GX PCI Express design to use a Stratix II GX device. This issue cannot be fixed because the device was designed before the PCI Express specifications were available. However, you can migrate your Stratix GX design to a Stratix II GX device. 6 Altera Corporation

7 Functional Issues Example Design Using the Stratix II GX PHY Does Not Work When Compiled with the Quartus II v6.1 Software Example designs created with PCI Express Compiler version and using the Stratix II GX PHY do not work when they are compiled with the Quartus II version 6.1 software due to an incorrect setting of the reconfig_togxb input to the PCI Express MegaCore function. The Stratix II GX PHY (alt2gxb) fails to operate correctly and prevents the PCI Express link from initializing in hardware and in simulation when the serial interface is simulated. This issues affects any example design created with PCI Express Compiler either version or using the Stratix II GX PHY. Additionally, application layer designs derived from the provided example may be affected. The PCI Express Link fails to initialize. The workaround is to upgrade to PCI Express Compiler version 6.1 when you upgrade to Quartus II version 6.1 Software. If you need to make the PCI Express Compiler version or version example design operate with Quartus II version 6.1, the example design needs to be modified to drive the reconfig_togxb PCI Express variation input with a constant 010 bit string instead of the 000 bit string. This issue is fixed in PCI Express Compiler v6.1 Altera Corporation 7

8 x8 MegaCore Function Ignores app_msi_num and app_msi_tc Input Signals When the application layer logic requests a Message Signal Interrupt (MSI) to be generated, the x8 MegaCore function ignores the app_msi_num and app_msi_tc input signals. The MSI data is always sent with zeros in the low order bits and traffic class 0 is always used. This issue only affects a x8 MegaCore function that uses the MSI feature. This issue allows only a single MSI to be used and it will be sent on traffic class 0. To workaround this issue, use the IP Toolbench to parameterize the x8 MegaCore function and specify an MSI messages requested value of 1. By specifying this value during parameterization, you can workaround the MSI data bits being 0. No workaround exists if you send the MSI on a traffic class other than 0. This issue will be fixed in a future release of the PCI Express Compiler. 8 Altera Corporation

9 Usage Issues Usage Issues This section contains usage issues which can include process changes or parameters that you need to specify. x8 PCI MegaCore Function Supports Only Stratix II GX Devices Although the PCI Express compiler x1 and x4 MegaCore functions support several device families, the PCI Express x8 MegaCore function supports only Stratix II GX devices. If you specify any other device for the x8 MegaCore function when running the Quartus II software, although the Quartus II software tries to compile the design, the compilation fails and returns an error message referencing the instantiation of the ALT2GXB megafunction. The information in the error message varies based on the device selected. This issue occurs whenever you use a x8 MegaCore function and specify a device other than Stratix II GX in the Quartus II software. There is no design impact. Either specify a Stratix II GX device whenever you use a x8 PCI Express MegaCore function, or if using other devices, select a x1 or x4 PCI Express MegaCore function with a PHY appropriate for the device family that you select. A future release of the PCI Express Compiler will display a more explicit error message when the x8 MegaCore function is compiled for an unsupported device family. Altera Corporation 9

10 PCI Express Simulation Example Requires Testbench Code Changes to Compile Successfully Differences in compiling the PCI Express MegaCore function when you use simulators other than Modelsim can result in the omission of some include files during compilation, which causes compilation failure. For example, a testbench with define statements that are global for the entire VCS compilation can result in include files being omitted and compilation failure. This issue affects testbench files compiled in a simulator other than Modelsim. There is no design impact. For more information, file a service request using Altera's mysupport website at Click Create New Service Request. Choose the Product Related Request form. This issue will be fixed in the next release of the PCI Express Compiler. Multiple PCI Express MegaCore Functions Must Be the Same Width You cannot specify multiple PCI Express MegaCore functions that are different widths in the same design. All PCI Express MegaCore functions in a design must be the same width. For example, your design cannot have both x1 and x4 PCI Express MegaCore functions. In this example, the MegaCore functions must be either all x1 or all x4 MegaCore functions. This issue affects any design specifying multiple PCI Express MegaCore functions that are different widths. 10 Altera Corporation

11 Usage Issues Using multiple width PCI Express MegaCore functions in the same design is not currently supported. To avoid this issue, ensure all PCI Express MegaCore functions in a design are the same width. This issue will be fixed in the next release of the PCI Express Compiler. Modify Rx Buffer Settings for Maximum Throughput For certain maximum payload sizes, you may need to set nonstandard values on the Buffer Setup page to ensure good throughput. In some cases, selecting Deep instead of Default for the Rx Buffer Size improves performance. Other cases may require that you select a larger Maximum Payload Size than what your design will actually use. A larger Maximum Payload Size adds just a few LEs to the overall design size and still works correctly with devices that have a smaller Maximum Payload Size because the configuration software sets up the correct runtime maximum payload size. In the following situations, using the standard settings on the Buffer Setup page will not provide the expected Rx throughput performance: Configurations with a 128-byte Maximum Payload Size. Configurations with a 256-byte Maximum Payload Size that need more Rx buffering than what the Default Rx Buffer Size setting provides. Configurations with a 512-byte Maximum Payload Size. The throughput of packets on the PCI Express receive link may be less than desired when you use the standard settings on the Buffer Setup page. Altera Corporation 11

12 Increase the Maximum Payload Size and buffer selection. For the 128-byte Maximum Payload Size, neither the Default or Deep buffer setting selects a large enough buffer to maintain maximum throughput. Increase the Maximum Payload Size to the 256-byte Maximum Payload Size and select the Default Rx Buffer Size. For a 256-byte Maximum Payload Size, the Deep buffer offers worse throughput than the Default buffer. Therefore, use the Default buffer to achieve the best throughput for this Maximum Payload Size. The 256- byte Maximum Payload Size Default buffer setting can be sufficient if the Rx Buffer packets are drained as quickly as possible. However, if the Default buffer is not sufficient for the design, then select a 512-byte Maximum Payload Size and a Deep Rx Buffer Size. For a 512-byte Maximum Payload Size, the Default buffer is not deep enough to maintain good performance; select the 512-byte Deep Rx Buffer Size. This issue will be fixed in the next release of the PCI Express Compiler. Disable Auto Configure Retry Buffer Size for Small Maximum Payload Sizes The Auto Configure Retry Buffer Size for either the 128-byte or 256-byte Maximum Payload Size is not large enough to provide high throughput for transmitted data. The Retry Buffer cannot hold enough Transmitted (Tx) packets to keep the Transaction link busy until the ACKs are received from the other end of the link freeing retry buffer space. For these Maximum Payload Sizes, the Retry Buffer Size should be set to 2 Kbytes. This issue affects designs in which the Maximum Payload Size is either 128 or 256 bytes and the Auto Configured Retry Buffer Size is set. Transmitted data throughput may be less than desired. 12 Altera Corporation

13 Usage Issues Uncheck the Auto Configure Retry Buffer Size box and set the Retry Buffer Size manually to 2 Kbytes. This issue will be fixed in the next release of the PCI Express Compiler. Incorrect is_request Function Designation Causes Testbench Compilation Failure With NCSim The testbench fails to compile during elaboration with NCSim because the is_request function (line 111) in the altpcietb_bfm_vc_intf.vhd file is incorrectly designated as pure when it should be designated as impure. This issue occurs when you compile the testbench with NCSim. The testbench fails to compile with NCSim. You can successfully compile the testbench with NCSim by changing the designation of the is_request function (line111) in the altpcietb_bfm_vc_intf.vhd file as follows: Change: function is_request ( To: impure function is_request ( The IP Toolbench creates the altpcietb_bfm_vc_intf.vhd file in the testbench/<variation_name> directory. This issue will be fixed in the next release of the PCI Express Compiler. Altera Corporation 13

14 Compiling a VHDL Design With Multiple MegaCore Functions in Quartus II Requires Each MegaCore Function Reside in a Separate Directory When compiling a VHDL design with one or more of the MegaCore functions listed below, each MegaCore function must reside in a separate directory. ÅPCI Express Compiler DDR/DDR2 SDRAM Controller ÅRLDRAM II Controller ÅQDR II Controller When a Quartus II project contains more than one of any of the listed MegaCore functions, each MegaCore function must reside in a separate directory. Compilation of the design fails if the each MegaCore function does not reside in a separate directory when the design contains a combination of the previously specified MegaCore functions. When a Quartus II project contains more than one of any of the listed MegaCore functions, you must ensure the following: Each MegaCore function must reside in a separate directory The Quartus II project contains only one copy of the following file: altera_vhdl_support.vhd 1 For PCI Express designs, the Quartus II project must contain one wrapper file for each PCI Express MegaCore function residing in a directory other than the Quartus II project. For more details, refer to the following issue in this errata sheet: Documentation Issues To ensure successful compilation of a Quartus II project, MegaCore functions must reside in separate directories when the Quartus II project contains a combination of the following MegaCore functions: 14 Altera Corporation

15 Usage Issues PCI Express Compiler DDR/DDR2 SDRAM Controller RLDRAM II Controller QDR II Controller When a Quartus II project contains multiple instances of the above MegaCore functions in separate directories, multiple instances of the VHDL package file, altera_vhdl_support.vhd, are generated, one for each MegaCore function in each directory. To successfully compile the design, the Quartus II project file can use only one of these files.therefore, before compiling a design containing a combination of these MegaCore functions, you must manually remove any additional altera_vhdl_support.vhd files from the Quartus II project until the Quartus II project contains only one altera_vhdl_support.vhd file. For example, in Figure 1, remove the second altera_vhdl_support.vhd file listed in the Quartus II project. Figure 1. Quartus II Project Containing Multiple altera_vhdl_support.vhd Files Altera Corporation 15

16 To ensure your project only includes one instance of the altera_vhdl_support.vhd file, follow these steps: 1. Choose Add/Remove Files in Project (Project menu). 2. Choose all instances of altera_vhdl_support.vhd except the first instance. 3. Click Remove. This issue will be fixed in a future release of the PCI Express Compiler. Add PCI Express Wrapper File When PCI Express MegaCore Resides in a Directory Other Than the Quartus II Project When a PCI Express MegaCore function resides in a directory other than the Quartus II project directory and you are using the <variation_name>_wrapper_pipen1b entity or module in your design hierarchy, you must manually add one PCI Express wrapper file to the Quartus II project for each PCI Express MegaCore function that is not in the Quartus II project. Based on whether the design is VHDL or Verilog HDL, the Quartus II project must contain one of these wrapper files for each PCI Express MegaCore function not in the Quartus II project: <PCI Express directory>\<variation_name>_wrapper_pipen1b.vhd <PCI Express directory>\<variation_name>_wrapper_pipen1b.v This issues affects any Quartus II project containing a PCI Express MegaCore function using the <variation_name>_wrapper_pipen1b entity or module in the design hierarchy that resides in a directory other than the Quartus II project. This includes <variation_name>_example_top designs created by the IP toolbench MegaWizard GUI. Compilation of the design fails if the PCI Express MegaCore function wrapper file is not added to the Quartus II project. Based on the design, add to the Quartus II project one of the following VHDL or Verilog HDL PCI Express wrapper files from each PCI Express MegaCore function directory to the Quartus II project for each PCI Express MegaCore function not residing in the Quartus II project: 16 Altera Corporation

17 Usage Issues <PCI Express directory>\<variation_name>_wrapper_pipen1b.vhd <PCI Express directory>\<variation_name>_wrapper_pipen1b.v Figure 2 shows an example of adding a PCI Express MegaCore function wrapper file to a Quartus II project. Figure 2. Adding PCI Express Compiler Wrapper File to Quartus Project II Project This issue will be fixed in a future release of the PCI Express Compiler. Compilation Issues Using the ModelSim runtb.do Script When you use the Quartus II 6.0 software to create a PCI Express Compiler v2.0.0 variation in VHDL, the testbench provided with PCI Express v2.0.0 does not compile and run the runtb.do script with the ModelSim software. Altera Corporation 17

18 Affected Confirguration This issue affects variations created with PCI Express Compiler v2.0.0 and that are running on Quartus II software 6.0, and will use the runtb.do script to simulate the variation in ModelSim. The variation will not compile and run the runtb.do script with ModelSim simulation software. You can either upgrade to PCI Express Compiler v2.1.0, or edit the testbench/<variation_name>/runtb.do file as outlined below. Replace these lines in the script: # Map the support library from the example_top file vmap altera_vhdl_support work With these lines: # Map the support library from the example_top file vlib altera vmap altera work vcom -work altera $env(quartus_rootdir)/libraries/vhdl/altera/altera _europa_support_lib.vhd If you rerun IP Toolbench for PCI Express Compiler v2.0.0 it generates a new incorrect version of the above runtb.do script. Therefore, save the modified script in another location before rerunning IP Toolbench. The runtb.do script in PCI Compiler v2.1.0 resolves this issue. 18 Altera Corporation

19 Documentation Issues Documentation Issues This section contains documentation issues which can include additions, corrections, clarifications, or changes to the documentation. Packet Format Field for the Request Headers Incorrectly Documented in the PCI Express Compiler User Guide The packet format for the DMA request headers is incorrectly documented in Table 4-3. Example Design Control Registers on page 4-9 of the PCI Express Compiler User Guide. The incorrect documentation affects the request header packet format field on page 4-9 of the PCI Express Compiler User Guide, version This issue has no design impact. Instead of using the Description section of the 6:5 Bit Field in Table 4-3 on page 4-9 of the PCI Express User Guide, use the following description of the 6:5 Bit Field: Table 4-3. Example Design Control Registers Register Byte Address (offset from Bar2, 3) Bit Field Description 6:5 Sets the value of the Packet Format Field in all PCI Express request headers generated by this DMA channel operation. The encoding is as follows: 00b Memory read (3DW w/o data) 01b Memory read (4DW w/o data) 10b Memory write (3DW w/data) 11b Memory write (4DW w/data) This documentation error will be fixed in the next release of the PCI Express Compiler User Guide. Altera Corporation 19

20 PCI Express User Guide Global Signal Reset Clarification In the PCI Express Compiler User Guide, Figure Global Reset Signals for x1 and x4 MegaCore Functions requires replacement to clarify global signal reset sources and conditions. A new figure also is required to illustrate how x8 global reset signals work in MegaCore functions. This issue is in the section of the PCI Express Compiler User Guide version that describes global signal reset for x1, x4, and x8 MegaCore functions. There is no design impact. Refer to the replacement text and figures below and the reference design. PCI Express Compiler User Guide Replacement Text & Figure for Figure Global Reset x1 and x4 MegaCore Functions The srst signal is a synchronous reset of the data path state machines. The crst signal is a synchronous reset of the nonsticky configuration space registers. Whenever the l2_exit, hotrst_exit, dlup_exit or other power-on-reset signals are asserted, srst and crst should be asserted for one cycle or more. When the perst# signal is asserted, srst and crst should be asserted for a longer period of time to ensure that the root complex is stable and ready for link training. 20 Altera Corporation

21 Documentation Issues Figure 3. Replacement for PCI Express User Guide Figure Global Reset Signals for x1 and x4 MegaCore Functions Other Power On Reset perst# npor a b a: Asserts Reset for 1024 cycles b: Asserts Reset for 1 cycles PCI Express x1 or x4 MegaCore Function srst crst l2_exit hotrst_exit dlup_exit Explanatory Text and Illustration Describes How x8 Global Reset Signals Work in MegaCore Functions The x8 MegaCore function has two reset inputs, npor and rstn. The npor reset is used internally for all sticky registers that may not be reset in L2 low power mode or by the fundamental reset. npor is typically generated by a logical OR of the power-on-reset generator and the perst# signal as specified in the PCI Express Card Electromechanical Specification. The rstn signal is an asynchronous reset of the data path state machines and the nonsticky configuration space registers. Whenever the l2_exit, hotrst_exit, dlup_exit or other poweron-reset signals are asserted, rstn should be asserted for one cycle or more. When the perst# signal is asserted, rstn should be asserted for a longer period of time to ensure that the root complex is stable and ready for link training. Altera Corporation 21

22 Figure 4. New PCI Express User Guide Figure Global Reset Signals for x8 MegaCore Functions Other Power On Reset perst# npor a b PCI Express x8 MegaCore Function rstn a: Asserts Reset for 1024 cycles b: Asserts Reset for 1 cycles l2_exit hotrst_exit dlup_exit This issue will be fixed in the next release of the PCI Express Compiler User Guide. Lane Reversal Is Not Supported in PCI Express MegaCore Functions The PCI Express Compiler User Guide incorrectly describes support for lane reversal in the x4 MegaCore function. The x4 MegaCore function does not have the optional support for reversing the lanes internally. However, the x4 MegaCore function will operate correctly when the lanes are reversed if the port at the other end of the PCI Express link can do the lane reversal function. This issue affects PCI Express x4 MegaCore functions that have their numbered physical lanes connected in a reverse configuration and the other end of the link cannot do the lane reversal function. The numbered physical lanes cannot be connected in a reverse configuration unless the other end of the link is capable of the lane reversal function. This means in applications conforming to the PCI 22 Altera Corporation

23 Contact Information Express Card Electromechanical Specification that the physical lanes of the PHY must be connected to like numbered pins on the connector. They must be connected so that the numbered physical lanes match. Connect matching numbered lanes together. The PCI Express Compiler User Guide will be updated in a future release of the PCI Express Compiler. Contact Information Revision History For more information, contact Altera's mysupport website at and click Create New Service Request. Choose the Product Related Request form. Table 2 shows the revision history for the PCI Express Compiler v2.0.0 Errata Sheet. Table 2. PCI Express Compiler v2.0.0 Errata Sheet Revision History (Part 1 of 2) Version Date Errata Summary 1.4 January 2007 The following errata are outlined: Stratix GX Devices Not Detected by Some PCI Express Devices Example Design Using the Stratix II GX PHY Does Not Work When Compiled with the Quartus II v6.1 Software x8 MegaCore Function Ignores app_msi_num and app_msi_tc Input Signals 1.3 April 2006 Lane Reversal Is Not Supported in PCI Express MegaCore Functions 1.2 January 2006 The following errata are outlined: Compiling a VHDL Design With Multiple MegaCore Functions in Quartus II Requires Each MegaCore Function Reside in a Separate Directory Documentation Issues Packet Format Field for the Request Headers Incorrectly Documented in the PCI Express Compiler User Guide Altera Corporation 23

24 Table 2. PCI Express Compiler v2.0.0 Errata Sheet Revision History (Part 2 of 2) Version Date Errata Summary 1.1 January 2006 The following errata are outlined: Timing Issues for PIPE Control Signals Interfacing to TI PHY Reversed Polarity on Lanes Incurs Reinitialization Delay on PCI Express Link x8 PCI MegaCore Function Supports Only Stratix II GX Devices More Than One PCI Express Core per Device Causes a Quartus II Fitter Error PCI Express Simulation Example Requires Testbench Code Changes to Compile Successfully PCI Express User Guide Global Signal Reset Clarification Modify Rx Buffer Settings for Maximum Throughput Disable Auto Configure Retry Buffer Size for Small Maximum Payload Sizes Incorrect is_request Function Designation Causes Testbench Compilation Failure With NCSim PCI Express User Guide Global Signal Reset Clarification VC1-3 InitFC DLLPs Sent Too Quickly Reduce Throughput 1.0 October 2005 No errata exist at this time. 24 Altera Corporation