POS-PHY Level 2 & 3 Compiler

Transcription

1 POS-PHY Level 2 & 3 Compiler User Guide 101 Innovation Drive San Jose, CA (408) Core Version: Document Version: rev1 Document Date: July 2003

2 Copyright 2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. ii UG-POSPHY2_3-1.4 Altera Corporation

3 About this User Guide This user guide provides comprehensive information about the Altera POS-PHY Compiler, which configures the following four MegaCore functions: POS-PHY level 2 link-layer POS-PHY level 2 PHY-layer POS-PHY level 3 link-layer POS-PHY level 3 PHY-layer Table 1 shows the user guide revision history. f Go to the following sources for more information: See New in Version on page 10 for a complete list of the core features, including new features in this release Refer to the readme file for late-breaking information that is not available in this user guide Table 1. Revision History Date July 2003 March 2003 June 2002 April 2002 April 2001 Description Quartus II version 3.0 information added. Device family support table added. IP Toolbench information added. Quartus II integrated synthesis information added. Stratix device information added. Updates to the user guide. First release. How to Find Information The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box. Bookmarks serve as an additional table of contents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, allow you to jump to related information. Altera Corporation iii

4 About this User Guide How to Contact Altera For the most up-to-date information about Altera products, go to the Altera world-wide web site at For additional information about Altera products, consult the sources shown in Table 2. Table 2. How to Contact Altera Information Type Access USA & Canada All Other Locations Altera Literature Services Non-technical customer service Technical support General product information Electronic mail (1) (1) Telephone hotline (800) SOS-EPLD (408) (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) (408) Telephone hotline (800) 800-EPLD (6:00 a.m. to 6:00 p.m. Pacific Time) Note: (1) You can also contact your local Altera sales office or sales representative. (408) (1) (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) (408) (1) Web site FTP site ftp.altera.com ftp.altera.com Telephone (408) (408) (1) Web site iv Altera Corporation

5 About this User Guide Typographic Conventions The uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: f MAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Italic type Internal timing parameters and variables are shown in italic type. Examples: t PIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Initial Capital Letters Subheading Title Courier type Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: Typographic Conventions. Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Altera Corporation v

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7 Contents About this User Guide... iii How to Find Information... iii How to Contact Altera... iv Typographic Conventions... v About this Core...9 Release Information...9 Device Family Support...9 Introduction...10 New in Version Features...10 General Description...11 Atlantic...13 Performance...14 Getting Started...17 Software Requirements...17 Design Flow...17 Obtain & Install the Function...17 Obtain MegaCore Functions...17 Install the MegaCore Files...18 MegaCore Directory Structure...18 Set Up Licensing...19 POS-PHY Level 2 and 3 Compiler Walkthrough...21 Create a New Quartus II Project...21 Launch the IP Toolbench...22 Step 1: Parameterize...23 Step 2: Generate...39 Simulate with the Models...41 Using the VHDL Testbenches...42 Visual IP Models...43 Synthesis, Compilation & Place & Route...43 Using Third-Party EDA Tools for Synthesis...44 Using the Quartus II Development Tool for Compilation & Place & Route...44 Licensing for Configuration...45 Performing Post-Routing Simulation Functional Description...47 Example Configurations...48 Altera Corporation vii

8 Contents Example Implementations...50 Internal Architecture...51 Signals...54 Core Verification...74 viii Altera Corporation

9 About this Core 1 Release Information Table 4 provides information about this release of the POS-PHY Level 2 and 3 Compiler. About this Core Device Family Support Table 4. POS-PHY Level 2 and 3 Compiler Release Information Item Description Version Release Date July 2003 Ordering Code (Product IDs) IP-POSPHY/P2 ( ) IP-POSPHY/L2 ( ) IP-POSPHY/P3 ( ) IP-POSPHY/L3 ( ) Vendor ID 6AF7 Every Altera MegaCore function offers a specific level of support to each of the Altera device families. The following list describes the three levels of support: Full The core meets all functional and timing requirements for the device family and may be used in production designs Preliminary The core meets all functional requirements, but may still be undergoing timing analysis for the device family; may be used in production designs. No support The core has no support for device family and cannot be compiled for the device family in the Quartus II software. Altera Corporation 9

10 About this Core Table 5 shows the level of support offered by the POS-PHY Level 2 and 3 Compiler to each of the Altera device families. Table 5. Device Family Support Device Family Stratix GX Cyclone Stratix Mercury Excalibur HardCopy APEX II APEX 20KE & APEX 20KC APEX 20K Other device families Full Full Full Full Full Full Full Full Full No support Support Introduction New in Version The POS-PHY Level 2 and 3 Compiler generates MegaCore functions for use in link-layer or physical (PHY) layer devices that transfer data to and from packet over SONET/SDH (POS) devices using the standard POS- PHY bus. Support for Quartus II version 3.0 Features Conforms to POS-PHY level 2 and level 3 specifications Link-layer or PHY-layer POS-PHY interfaces Creates bridges between different POS-PHY interfaces Supports traffic up to a rate of 3.2 gigabits per second (Gbps) (POS- PHY level 3) or 832 megabits per second (Mbps) (POS-PHY level 2), such as SONET OC-48 Single-PHY (SPHY) or up to 8-channel multi-phy (MPHY) operation with polled and direct packet available options Up to 104-MHz operation, allowing interconnection of different rate streams Atlantic interface that allows a consistent interface between all Altera cell and packet MegaCore functions Selectable POS-PHY interface bus widths (8/16/32 bit) and Atlantic interface bus widths (8/16/32/64 bit) allowing translation between different bus types Parity generation/detection Configurable first-in first-out (FIFO) options: selectable FIFO width, depth, and fill thresholds. 10 Altera Corporation

11 About this Core Easy-to-use IP Toolbench generates parameterized MegaCore functions Includes simulation models OpenCore feature allows designers to instantiate and simulate designs in the Quartus II software prior to purchase POS-PHY level 3 compliant with the POS-PHY Level 3 Specification, Issue 4, June 2000; POS-PHY level 2 compliant with the POS-PHY Level 2 Specification, Issue 5, December About this Core 1 The IP Toolbench is a toolbar from which you can quickly and easily view documentation, specify core parameters, set up third-party tools, and generate all files necessary for integrating the parameterized core into your design. General Description The POS-PHY Level 2 and 3 Compiler comprises separately configurable modules, which can be easily combined via the IP Toolbench to generate a highly parameterized module, allowing POS-PHY compliant interfaces (and non-standard interfaces) to be included in custom designs. The compiler supports POS-PHY level 3 operating at up to 3.2 Gbps, and level 2 operating at up to 832 Mbps. The POS-PHY Level 2 and 3 Compiler is compliant with all applicable standards, including: POS-PHY Level 3 Specification, Issue 4, June 2000 POS-PHY Level 2 Specification, Issue 5, December 1998 Optical Internet working Forum (OIF), System Packet Level 3 (SPI-3) Altera Corporation, Atlantic Specification This allows efficient translation between the different formats, including mapping between different bus speeds and bus widths, as well as customizable FIFO buffer parameters. The compiler allows configurations such as PHY-PHY, link-link bridges, or packet multiplexing cores, and SPHY and MPHY applications. Figure 1 shows the possible interfaces. Figure 2 shows the possible bridges. Altera Corporation 11

12 About this Core Figure 1. s PHY Core Atlantic User Logic SPHY SPHY Link Core Atlantic User Logic SPHY SPHY Core Atlantic User Logic PHY/Link Atlantic User Logic MPHY SPHY Atlantic User Logic 12 Altera Corporation

13 About this Core Figure 2. Bridges SPHY Level 2/3 Link Level 2/3 PHY Core Core Level 2/3 Link Level 2/3 PHY SPHY 1 About this Core SPHY SPHY Level 2/3 Link Core Level 2/3 PHY SPHY SPHY Core Level 2/3 PHY/Link Level 2/3 PHY/Link Level 2/3 PHY/Link MPHY Level 2/3 PHY/Link SPHY Atlantic The Atlantic interface allows a consistent interface between all Altera cell and packet MegaCore functions. The Atlantic interface supports a pointto-point connection. f For more information on the Atlantic interface, refer to the Atlantic Functional Specification. Altera Corporation 13

14 About this Core Performance Tables 6 to 9 show typical expected performance for SPHY and 4-port POS-PHY cores for Cyclone and Stratix devices. Results were generated using the Quartus II software version 2.2. All results are push-button performance and use a FIFO size of 512 bytes. Table 6. Performance POS-PHY Level 2 Link Layer Core Cyclone (1) Stratix (2) LEs Memory (3) a_clk (MHz) LEs Memory (3) a_clk (MHz) SPHY receive SPHY transmit port receive 1, , port transmit 1, , Note: (1) EP1C6F256C6 device for SPHY cores; EP1C12F324C6 device for 4-port cores. (2) EP1S10F484C5 device. (3) M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices. Table 7. Performance POS-PHY Level 2 PHY Layer Core Cyclone (1) Stratix (2) LEs Memory (3) a_clk (MHz) LEs Memory (3) a_clk (MHz) SPHY receive SPHY transmit port receive 1, , port transmit 1, , Note: (1) EP1C6F256C6 device for SPHY cores; EP1C12F324C6 device for 4-port cores. (2) EP1S10F484C5 device. (3) M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices 14 Altera Corporation

15 About this Core. Table 8. Performance POS-PHY Level 3 Link Layer Core Cyclone (1) Stratix (2) LEs Memory (3) a_clk (MHz) LEs Memory (3) a_clk (MHz) SPHY receive SPHY transmit port receive 1, , port transmit 1, , About this Core Note: (1) EP1C6F256C6 device for SPHY cores; EP1C12F324C6 device for 4-port cores. (2) EP1S10F484C5 device. (3) M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices. Table 9. Performance POS-PHY Level 3 PHY Layer Core Cyclone (1) Stratix (2) LEs Memory (3) a_clk (MHz) LEs Memory (3) a_clk (MHz) SPHY receive SPHY transmit port receive 1, , port transmit 1, , Note: (1) EP1C6F256C6 device for SPHY cores; EP1C12F324C6 device for 4-port cores. (2) EP1S10F484C5 device. (3) M4K RAM blocks for Cyclone devices; (M512 + M4K) RAM blocks for Stratix devices. Altera Corporation 15

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17 Getting Started Software Requirements Design Flow Obtain & Install the Function This section requires the following software: Quartus II, version 3.0 (or higher) 1 This getting started assumes that you are using a PC with the Windows operating system. However, you can also use the POS- PHY Level 2 and 3 Compiler on UNIX platforms. This POS-PHY Level 2 and 3 Compiler design flow involves the following steps: 1. Obtain and install the POS-PHY Level 2 and 3 Compiler. 2. Set-up the licensing 3. Generate a custom MegaCore function using the IP Toolbench. 4. Implement your system using AHDL, VHDL, or Verilog HDL. 5. Compile your design. 6. Simulate your design to confirm the operation of your system. 7. License the POS-PHY Level 2 and 3 Compiler and configure the devices. Before you can start using Altera MegaCore functions, you must obtain the MegaCore files and install them on your PC. The following instructions describe this process. Obtain MegaCore Functions If you have Internet access, you can download the POS-PHY Level 2 and 3 Compiler from the Altera web site at Follow the instructions below to obtain the POS-PHY Level 2 and 3 Compiler via the Internet. If you do not have Internet access, you can obtain the POS-PHY Level 2 and 3 Compiler from your local Altera representative. 1. Point your web browser at 2 Getting Started Altera Corporation 17

18 Getting Started 2. In the IP MegaSearch keyword field, type POS-PHY. 3. Click the appropriate link for your desired MegaCore function. 4. Click the link for the download icon. 5. Follow the online instructions to download the function and save it to your hard disk. Install the MegaCore Files For Windows, follow the instructions below: 1. Click Run (Start menu). 2. Type <path name>\<filename>, where <path name> is the location of the downloaded MegaCore function and <filename> is the filename of the function. Click OK. 3. The MegaCore Installer dialog box appears. Follow the on-line instructions to finish installation. 4. After you have finished installing the MegaCore files, you must specify the relevant MegaCore function s library (lib\) directory as a user library in the Quartus II software, respectively. Search for User Libraries in the Quartus II Help for instructions on how to add a library. MegaCore Directory Structure Altera MegaCore function files are organized into several directories; the top-level directory is \posphy_l2_l3-<version> (see Figure 3). The MegaCore directory structure may contain several MegaCore products. Additionally, Altera updates MegaCore files from time-to-time. Therefore, Altera recommends that you do not save your project-specific files in the MegaCore directory structure. 18 Altera Corporation

19 GettingGetting Started Figure 3. Directory Structure MegaCore pos_phy_l2_l3-<version> Contains the POS-PHY Level 2 and 3 Compiler MegaCore function files and documentation. doc Contains the documentation for the core. lib Contains encrypted lower-level design files. After installing the MegaCore function, you should set a user library in the Quartus II software that points to this directory. This library allows you to access all the necessary MegaCore files. sim_lib Contains the simulation models provided with the core. native Contains the precompiled library directories. vhdl Contains the VHDL precompiled libraries and the VHDL testbenches. modelsim Contains the precompiled libraries and the testbenches for the ModelSim simulation tool. 2 Getting Started testbench Contains the testbench directories vhdl Contains two example VHDL wrapper files and testbenches. verilog Contains two example Verilog HDL wrapper files and testbenches. vip_models Contains the precompiled libraries for the Visual IP software. Set Up Licensing You can use the Altera OpenCore feature to compile and simulate the POS-PHY Level 2 and 3 Compiler, allowing you to evaluate it before purchasing a license. You can simulate your POS-PHY level 2 and 3 design in the Quartus II software using the OpenCore feature. However, you must obtain a license from Altera before you can generate programming files or EDIF, VHDL, or Verilog HDL gate-level netlist files for simulation in third-party EDA tools. After you purchase a license for POS-PHY Level 2 and 3 Compiler, you can request a license file from the Altera web site at and install it on your PC. When you request a license file, Altera s you a license.dat file. To install your license, perform the following steps. 1 Before you set up licensing for the POS-PHY level 2 and 3 Compiler, you must already have the Quartus II software installed on your PC with licensing set up. Altera Corporation 19

20 Getting Started 1. Close the following software if it is running on your PC: Quartus II MAX+PLUS II LeonardoSpectrum Synplify ModelSim 2. Open the POS-PHY Level 2 and 3 Compiler license file in a text editor. The file should contain one FEATURE line, spanning 2 lines. 3. Open your Quartus II license.dat file in a text editor. 4. Copy the FEATURE line from the POS-PHY Level 2 and 3 Compiler license file and paste it into the Quartus II license file. 1 Do not delete any FEATURE lines from the Quartus II license file. 5. Save the Quartus II license file. When using editors such as Microsoft Word or Notepad, ensure that the file does not have extra extensions appended to it after you save (e.g., license.dat.txt or license.dat.doc). Verify the filename in a DOS box or at a command prompt. 20 Altera Corporation

21 GettingGetting Started POS-PHY Level 2 and 3 Compiler Walkthrough This walkthrough explains how to create a custom core using the Altera POS-PHY Level 2 and 3 Compiler IP Toolbench and the Quartus II software. As you go through the IP Toolbench, each page is described in detail. When you are finished generating a custom core, you can incorporate it into your overall project. 1 The IP Toolbench only allows you to select legal combinations of parameters, and warns you of any invalid configurations. Press F1 at anytime for on-line help. This walkthrough consists of the following steps: Create a New Quartus II Project on page 21 Launch the IP Toolbench on page 22 Step 1: Parameterize on page 23 Step 2: Generate on page 39 Create a New Quartus II Project Before you begin creating a POS-PHY core, you must create a new Quartus II project. With the New Project wizard, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity. You will also specify the POS-PHY Level 2 and 3 Compiler user library. To create a new project, perform the following steps: 1. Choose Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. You can also use the Quartus II Web Edition software if you prefer. 2. Choose New Project Wizard (File menu). 3. Click Next in the introduction (the introduction will not display if you turned it off previously). 4. Specify the working directory for your project. 5. Specify the name of the project. 6. Click Next. 7. Click User Library Pathnames. 8. Type <path>\posphy_l2_l3-<version>\lib\ into the Library name box, where <path> is the directory in which you installed the POS-PHY Level 2 and 3 Compiler. The default installation directory is c:\megacore. 2 Getting Started Altera Corporation 21

22 Getting Started 9. Click Add. 10. Click OK. 11. Click Next. 12. Click Finish. You are finished creating your new Quartus II project. Launch the IP Toolbench The MegaWizard Plug-In Manager allows you to run a wizard that helps you easily specify options for the POS-PHY Level 2 and 3 Compiler. To launch the wizard, perform the following steps: 1. Start the MegaWizard Plug-In Manager by choosing the MegaWizard Plug-In Manager command (Tools menu). The MegaWizard Plug-In Manager dialog box is displayed. 1 Refer to the Quartus II Help for more information on how to use the MegaWizard Plug-In Manager. 2. Specify that you want to create a new custom megafunction and click Next. 3. Select posphy_l2_l3-<version> in the Communications/POS-PHY directory. 4. Choose the output file type for your design; the wizard supports AHDL, VHDL, and Verilog HDL. 5. Specify a directory, <directory name> and name for the output file, <variation name>. Figure 4 shows the wizard after you have made these settings. 1 <variation name> and <directory name> must be the same name and the same directory that your Quartus II project use. 22 Altera Corporation

23 GettingGetting Started Figure 4. Select the MegaCore Function 2 Getting Started Step 1: Parameterize To parameterize your core, perform the following steps: 1. Click Step 1: Parameterize in the IP Toolbench (see Figure 5). Altera Corporation 23

24 Getting Started Figure 5. IP Toolbench 2. Select the architecture options (see Architecture Options on page 24). 3. Select the interface types (see Types on page 25). 4. Choose the interface settings (see Settings on page 26). 5. Select the parity settings (see Parity Settings on page 28). 6. Choose the FIFO buffer settings (see FIFO Buffer Settings on page 30). 7. Choose the address and packet availabe settings (see Address & Packet Available Settings on page 36). Architecture Options Select your architecture options where the POS-PHY A interface is a data source or sink (see Figure 6), and click Next. 24 Altera Corporation

25 GettingGetting Started Figure 6. Select the A Direction 2 1 Source indicates that interface A is an output from the core. Sink indicates that interface A is an input to the core. Getting Started In a MPHY architecture there is a B interface for each supported channel (maximum eight). Select the number of supported channels that you require. To create a design that supports source and sink data directions, you must run the MegaWizard Plug-In twice, to create the source and sink designs separately. Types Select your interface types (see Figure 7), and click Next. Altera Corporation 25

26 Getting Started Figure 7. Select the Types Select interface A using the radio buttons. Choose B interfaces using the drop-down menus. Settings Choose the interface settings (see Figure 8), and click Next. 26 Altera Corporation

27 GettingGetting Started Figure 8. Choose the Settings 2 POS-PHY Level 3 Specification, Issue 4, June 2000 supports an 8- or 32-bit interface. Additionally this core supports a 16-bit interface for POS-PHY level 3. Getting Started POS-PHY Level 2 Specification, Issue 5, December 1998 supports a 16 bit interface. Additionally, this core supports 8- and 32-bit interfaces for POS- PHY level 2. The Atlantic interface can be 8-, 16-, 32-, or 64-bits wide. FIFO Buffer & Clock Selector Options The following interface B FIFO buffer and clock selector options are available: A Clock (No FIFO) only available if the B interface is an Atlantic master, and the B interface bus width the A interface bus width. The relevant B interface does not use an internal FIFO buffer, and is clocked by the A interface clock pin. This is recommended only if you connect B interfaces directly to another core with an Atlantic slave interface A Clock the corresponding B interface uses an internal single clock FIFO buffer, and is clocked by the A interface clock pin B Clock the corresponding B interface uses an internal dual clock FIFO buffer, and is clocked by the corresponding B interface clock pin The FIFO width is the greater of the A bus width and the associated B bus width. Altera Corporation 27

28 Getting Started Common B Clock With MPHY configurations there is more than one B interface in the core. Select this option to use a common clock and reset pins for all the B interfaces that use the B clock option. If you select this option, the B interface clock and reset pins are labeled b_clk and b_reset_n. Parity Settings Select the parity settings of the interfaces (see Figure 9), and click Next. Figure 9. Select the Parity Settings 1 If parity is used the polarity setting must be the same for all interfaces. Pass Through Mode In pass through mode any detected data parity errors on a sink interface are regenerated on the source interface, even when there is a bus width change. 1 If a parity error is detected on a sink interface port that has a wider data width than its corresponding source interface port, the parity error is generated on all output words that correspond to the input word with an error. 28 Altera Corporation

29 GettingGetting Started Table 10 shows the number of errors generated per input error. Table 10. Number of Errors Generated Data Width In Data Width Out Number of Errors Generated per Input Error Getting Started If you are using the parity bit and the parity does not match the data, the core always detects the parity error. For a source Atlantic interface, the par pin is an output that indicates the sink interface has received parity errors. For a sink Atlantic interface, the par pin is an input that sees either a one or a zero depending on the incoming data s parity value If a parity error is detected on a sink interface port, which has a wider data width than its corresponding source interface port, the parity output is high on all output words that correspond to the input word with an error (see Table 10). When a parity error is detected (as the data comes in), but the data width changes (increases), there are two options pass through or error. Pass through the word that goes out, which contains the erroneous word and a good word, is flagged with an incorrect parity. Error the par signal functionality changes. It does not show parity, but goes high only when there is an error with the word, i.e., it goes high to show where the error is. Altera Corporation 29

30 Getting Started ParErr On Error Pin When you check this option, the err signal is created, which looks for parity errors in the entire packet. The err signal can go high at anytime, but is valid only at the end of the packet (in accordance with the POS-PHY specifications). A high indicates a parity error somewhere in the packet. A parity error detected on a sink interface is signalled by setting the err pin at the end of the affected packet on the source interface. FIFO Buffer Settings Choose the FIFO buffer settings (see Figure 10), and click Next. Figure 10. Choose the FIFO Buffer Settings Table 11 shows the effect of the FIFO settings for POS-PHY level 3 interfaces. 30 Altera Corporation

31 GettingGetting Started 1 All FIFO parameters are shown in bytes. Table 11. POS-PHY Level 3 FIFO Settings (Page 1 of 2) (Direction) Link Transmit (Source) Link Receive (Sink) PHY Transmit (Sink) FIFO Threshold FIFO Burst FIFO Remote Burst When each FIFO buffer overflows the FIFO threshold level, or contains a packet or packet fragment with an EOP, it triggers its not empty flag. The interface then tries to empty each of the FIFO buffers containing data, as soon as it detects the PHY transmit interface has indicated it has space. When operating in polled mode, this is indicated using the PTPA and STPA inputs. When operating in direct status mode, this is indicated using the DTPA inputs. The interface indicates, by asserting low the RENB output, that it is not full when it has more than or equal to FIFO threshold spaces for bytes in all of its FIFO buffers (1 FIFO per channel). The interface indicates, by deasserting high the RENB output, that it is full when it has no more spaces for bytes in any of its FIFO buffers (1 FIFO per channel). When there is more than or equal to FIFO threshold spaces for bytes in any of its FIFO buffers (1 FIFO per channel), the interface indicates this on a per channel basis to the link transmit interface. When operating in polled mode, this is indicated by asserting PTPA and STPA outputs. When operating in direct status mode, this is indicated by asserting the DTPA outputs. Indicates the maximum number of bytes the interface transfers in each FIFO burst. In MPHY mode, at the end of each FIFO burst the core re-arbitrates for a new channel in a round-robin fashion. Set FIFO burst <= FIFO threshold. Not applicable in SPHY mode. This should be set to the minimum value allowed. When there is less than FIFO burst spaces for bytes in any of its FIFOs (1 FIFO per channel), the interface indicates this on a per channel basis to the link transmit interface. When operating in polled mode, this is indicated by deasserting the PTPA and STPA outputs. When operating in direct status mode, this is indicated by deasserting the DTPA outputs. Prevents the PHY transmit interface from overflowing. Must be compatible with the PHY transmit interface FIFO burst setting. When the interface is in the process of transferring data and the PHY transmit interface indicates it is almost full, link transmit interface transfers up to FIFO remote burst more bytes before stopping. When operating in polled mode, this is indicated using the PTPA and STPA inputs. When operating in direct status mode, this is indicated using the DTPA inputs. N/A N/A 2 Getting Started Altera Corporation 31

32 Getting Started Table 11. POS-PHY Level 3 FIFO Settings (Page 2 of 2) (Direction) FIFO Threshold FIFO Burst FIFO Remote Burst PHY Receive (Source) When each FIFO fills to above the FIFO threshold level, or contains a packet or packet fragment with an EOP, it triggers its not empty flag. The interface then tries to empty each of the FIFO buffers with data, as soon as it detects the link receive interface has asserted low the RENB input. Indicates the maximum number of bytes the interface transfers in each FIFO burst. In MPHY mode, at the end of each FIFO burst the core re-arbitrates for a new channel in a round-robin fashion. Set FIFO burst <= FIFO threshold. In SPHY mode, this should be set to the minimum value allowed. N/A Table 12 shows the effect of the FIFO settings for POS-PHY level 2 interfaces. Table 12. POS-PHY Level 2 FIFO Settings (Page 1 of 2) (Direction) Link Transmit (Source) Link Receive (Sink) FIFO Threshold FIFO Burst FIFO Remote Burst When each FIFO fills to above the FIFO threshold level, or contains a packet or packet fragment with an EOP, it triggers its not empty flag. The interface then tries to empty each of the FIFO buffers containing data, as soon as it detects the PHY transmit interface has indicated it has space. When operating in polled mode, this is detected using the PTPA and STPA inputs. When operating in direct status mode, this is detected using the DTPA inputs. When there is more than or equal to FIFO threshold spaces for bytes in any of its FIFO buffers (1 FIFO per channel), the internal FIFO full flag is deasserted. This allows the interface to start transfering data, as soon as it detects the PHY receive interface has indicated it has data. When operating in polled mode, this is detected using the PRPA input. When operating in direct status mode, this is detected using the DRPA inputs. Indicates the maximum number of bytes the interface will transfer in each FIFO burst. In MPHY mode, at the end of each FIFO burst the core re-arbitrates for a new channel in a round-robin fashion. Set FIFO burst <= FIFO threshold. Not applicable in SPHY mode. Indicates the maximum number of bytes the interface will transfer in each FIFO burst. When there is less than FIFO burst spaces in the FIFO, the internal FIFO full flag is asserted. In MPHY mode, at the end of each FIFO burst the core re-arbitrates for a new channel in a round-robin fashion. Set FIFO burst <= FIFO threshold. In SPHY mode, this should be set to the minimum value allowed. When the interface is in the process of transferring data and the PHY transmit interface indicates it is almost full, the link transmit interface transfers up to FIFO remote burst more bytes before stopping. When operating in polled mode, this is detected using the PTPA and STPA inputs. When operating in direct status mode, this is detected using the DTPA inputs. N/A 32 Altera Corporation

33 GettingGetting Started Table 12. POS-PHY Level 2 FIFO Settings (Page 2 of 2) (Direction) FIFO Threshold FIFO Burst FIFO Remote Burst PHY Transmit (Sink) PHY Receive (Source) When there is more than or equal to FIFO threshold spaces for bytes in any of its FIFO buffers (1 FIFO per channel), the interface indicates this on a per channel basis to the link transmit interface. When operating in polled mode, this is indicated by asserting PTPA and STPA outputs. When operating in direct status mode, this is indicated by asserting the DTPA outputs. When there are more than FIFO threshold bytes in any of its FIFO buffers (1 FIFO per channel), the interface indicates this on a per channel basis to the link receive interface. When operating in polled mode, this is indicated by asserting the PRPA output. When operating in direct status mode, this is indicated by asserting the DRPA outputs. When there is less than FIFO burst spaces for bytes in any of its FIFOs (1 FIFO per channel) the interface indicates this on a per channel basis to the link transmit interface. When operating in polled mode, this is indicated by deasserting the PTPA output. When operating in direct status mode, this is indicated by deasserting the DTPA outputs. When there are less than or equal to FIFO burst bytes in any of its FIFOs (1 FIFO per channel), the interface indicates this on a per channel basis to the link receive interface. When operating in polled mode, this is indicated by deasserting the PRPA output. When operating in direct status mode, this is indicated by deasserting the DRPA outputs. N/A N/A 2 Getting Started Atlantic FIFO Settings Table 12 shows the effect of the FIFO settings for Atlantic interfaces, which control the dav signal. Table 13. Atlantic FIFO Settings (Page 1 of 2) Atlantic Master Source Behavior of the dav Signal The dav signal is an input. The slave indicates to the master that it has space by asserting dav. The master then tries to fill the slave FIFO buffer. Figure 11 shows the behavior of the dav signal. (1) FIFO burst is not applicable. FIFO remote burst when the slave deasserts dav, the master can transfer up to FIFO remote burst more bytes of data before stopping; or can stop immediately if FIFO remote burst is zero. Altera Corporation 33

34 Getting Started Table 13. Atlantic FIFO Settings (Page 2 of 2) Atlantic Master Sink Behavior of the dav Signal The dav signal is an input. The slave indicates to the master that it has data by asserting dav. The master then tries to empty the slave FIFO buffer. Figure 12 shows the behavior of the dav signal. (1) FIFO burst is not applicable. Atlantic Slave Sink Atlantic Slave Source FIFO remote burst is not applicable. The dav signal is an output. The dav signal high indicates that there is space for more data. When the FIFO buffer is below full threshold, dav is high. When the FIFO buffer is filling, dav remains high until the FIFO buffer reaches burst threshold. When the FIFO buffer is emptying, dav remains low until the FIFO buffer reaches full threshold. Figure 13 shows the behavior of the dav signal. FIFO remote burst is not applicable. The dav signal is an output. When dav is high, there is data to send. When the FIFO buffer is above the empty threshold, dav is high. When the FIFO buffer is filling, dav remains low until the FIFO buffer reaches empty threshold. When the FIFO buffer is emptying, dav remains high until the FIFO buffer reaches burst threshold. Figure 14 shows the behavior of the dav signal. FIFO remote burst is not applicable. Note: (1) The slave asserts dav high for two reasons: it has passed its threshold, or an EOP has occurred. 34 Altera Corporation

35 GettingGetting Started Figure 11. Behavior of the dav Signal as an input to the Atlantic Master Source Slave has space 1 dav 0 Slave has no space 2 Figure 12. Behavior of the dav Signal as an input to the Atlantic Master Sink Slave has data Getting Started 1 dav 0 Slave has no data Figure 13. Behavior of the dav Signal Atlantic Slave Sink 1 dav 0 Full threshold Burst threshold Altera Corporation 35

36 Getting Started Figure 14. Behavior of the dav Signal Atlantic Slave Source 1 dav 0 Burst threshold Empty threshold FIFO Buffer Size The FIFO buffer size is automatically set to be as wide as the widest of the input and the output port. Each word in the FIFO buffer can only contain at most one packet. Where the FIFO width is N bytes, packets of 1 to N bytes in length occupy 1 FIFO word. So a FIFO buffer of (M words N bytes) can only hold M packets with a length of 1 to N bytes. Address & Packet Available Settings Choose the address and packet available settings in page 8 of the wizard (see Figure 15), and click Next. Figure 15. Choose the Address and Packet Available Settings The Atlantic interface always operates in direct (no addressing) mode. 36 Altera Corporation

37 GettingGetting Started POS-PHY Level 3 s The POS-PHY level 3 interfaces can be multi- or single-channel. Table 14 shows the multi-channel packet available mode options. Table 14. Multi-Channel Packet Available Mode Options (POS-PHY Level 3) Option Direct Polled Polled (Ignore stpa) Description In the POS-PHY transmit direction the core uses one dtpa pin per supported channel. In the POS-PHY receive direction the core uses renb and rval to support all channels. In the POS-PHY transmit direction the core uses tadr, ptpa, and stpa, to support all channels. In the POS-PHY transmit direction the core uses tadr and ptpa to support all channels. For compatibility with some POS-PHY interfaces that do not support the functionality of the stpa pin, the stpa signal is ignored and removed from the core. 2 Getting Started Table 15 shows the multi-channel packet available mode options. Table 15. Single-Channel Packet Available Mode Options (POS-PHY Level 3) Direct Option Direct (No Addressing) Description In the POS-PHY transmit direction the core uses one dtpa pin, and uses a tsx pin. In the POS-PHY receive direction the core uses renb and rval, and uses an rsx pin. In the POS-PHY transmit direction the core uses one dtpa pin, and does not use a tsx pin. In the POS-PHY receive direction the core uses renb and rval, and does not use an rsx pin. 1 B interfaces always operate in direct mode. Altera Corporation 37

38 Getting Started POS-PHY Level 2 s The POS-PHY level 2 interfaces can be multi- or single-channel. Table 16 shows the multi-channel packet available mode options. Table 16. Multi- & Single-Channel Packet Available Mode Options (POS-PHY Level 2) Option Description Direct In the POS-PHY transmit direction the core uses one dtpa pin per supported channel. In the POS-PHY receive direction the core uses one drpa pin per supported channel. Polled In the POS-PHY transmit direction the core uses tadr, ptpa, and stpa to support all channels. In the POS-PHY receive direction the core uses radr and prpa to support all channels. Polled (Ignore stpa) In the POS-PHY transmit direction the core uses tadr and ptpa pins to support all channels. - The stpa signal is removed from the core. Direct (No Addressing) mode does not include address matching or bus tri-stating (currently not supported). Base Address Base address is only supported in POS-PHY level 2 mode. It configures the base address of the POS-PHY port. For a single channel interface ( A or B ), the interface responds to only the configured base address. For a multi-channel interface ( A only), the interface responds to addresses between base address and base address + number of B interfaces. SX Always SX always is only valid for POS-PHY level 3 link transmit (multi-channel) or PHY receive (source) interfaces. You can set the SX output behavior to one of the following conditions: Normal generates an SX cycle only when changing channels Always an SX cycle is generated for every burst and at the end of packets 1 For POS-PHY level 3 sink interfaces, the core supports either behavior transparently. 38 Altera Corporation

39 GettingGetting Started Step 2: Generate To generate your core, perform the following steps: 1. Note the order code and click Finish (see Figure 16). Figure 16. Order Code 2 Getting Started 2. Click Step 2: Generate in the IP Toolbench (see Figure 17). Figure 17. IP Toolbench Generate Altera Corporation 39

40 Getting Started 3. IP Toolbench list the settings for your IP block (see Figure 16). Click Continue. Figure 18. Summary Page 4. The generation report lists the design files that the IP Toolbench creates (see Figure 19). Click Exit IP Toolbench. 40 Altera Corporation

41 GettingGetting Started Figure 19. IP Toolbench-Generated Files 2 Getting Started When you have created your custom megafunction, you can integrate it into your system design and compile. 1 The symbol file created is not intended for use in block/schematic mode. Simulate with the Models Altera provides a VHDL model that you can use to simulate the MegaCore function in your system. Altera also provides Visual IP models, which you can use with the Visual IP software and are supported by other simulators. The VHDL model is supplied as pre-compiled libraries for the ModelSim simulation tool and is installed in the sim_lib\native\vhdl\modelsim directory. You can integrate this model into your system, speeding the simulation process. The following instructions describe how to set up your system and how to simulate the VHDL model using the ModelSim simulation tool. Within the sim_lib\native\vhdl\modelsim directory is a precompiled library, auk_pac_lib, which is required. 1. Run the ModelSim simulation tool and create a logical map called auk_pac_lib to the directory containing the compiled library by typing the following command in the ModelSim software: vmap auk_pac_lib <Drive:>/<MegaCore Path> /sim_lib/native/vhdl/modelsim/auk_pac_libr Altera Corporation 41

42 Getting Started 1 You can also use the ModelSim graphical user interface (GUI) to create a logical map. Refer to the ModelSim online help for details. 2. You must refresh the compiled library by typing the command: vcom -work auk_pac_lib -refreshr Using the VHDL Testbenches In addition to the model, Altera provides sample VHDL testbenches (in the sim_lib\testbench\vhdl\ directory). These VHDL testbenches let you easily simulate the function. To use the models, you must first instantiate them in your system. To compile these files in the ModelSim software, follow the steps below: 1 To use the sample VHDL testbenches, the VHDL models must be available and both setup for ModelSim as described earlier. 1. Open the ModelSim simulation tool. Choose Change Directory (File menu) and change the directory to sim_lib\native\vhdl\modelsim. 2. Select Create a New Library (Design Menu). Select a new library and a logical mapping to it. In the Library Box type work. 3. Select Compile (Design menu), in the Compile HDL Source Files dialog box, select the library auk_pac_lib in the Library drop-down list box. Also select the \sim_lib\native\vhdl directory in the Look In drop-down list box. For a POS-PHY level 3 link-layer transmitter, select the IP Toolbench wrapper, auk_pac_mtx_pl3_link, and click Compile. 4. Select the library work in the Library drop-down list box, select the testbench auk_pac_mtx_ref_tb and click Compile. 1 For a POS-PHY 3 link-layer receiver, repeat step 3 but use auk_pac_mrx_pl3_link and auk_pac_mrx_ref_tb. 5. When the compilation finishes, click Done. You are now ready to run the simulation. 1 The testbench works with the included IP Toolbench wrapper; you must amend the testbench, if different IP Toolbench options are selected. 42 Altera Corporation

43 GettingGetting Started Visual IP Models Follow the instructions below to obtain the Visual IP software via the Internet. If you do not have Internet access, you can obtain the Visual IP software from your local Altera representative. 1. Point your web browser at 2. Follow the online instructions to download the software and save it to your hard disk. To use the Visual IP model, perform the following steps: 1. Set up your system to use the Visual IP software, as detailed in the Visual IP documentation (Simulating Visual IP Models with the ModelSim Simulator for PCs White Paper, Simulating the Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators White Paper). 2 Getting Started 2. Compile the wrapper for the core model into the auk_pac_lib library. The Verilog version of the wrapper is in the $VIP_MODELS_DIR\<model_name>\interface\pli directory; the corresponding VHDL version is in the $VIP_MODELS_DIR \<model_name>\interface\mti directory. 1 <model_name> is auk_pac_mrx_mw for the receive cores and auk_pac_mtx_mw for the transmit cores. 3. Compile the wrapper for the testbench model, auk_pac_mtx_ref_tb. 4. Compile the IP Toolbench wrapper, auk_pac_mtx_pl3_link. 1 For a POS-PHY 3 link-layer receiver, repeat steps 3 and 4 but use auk_pac_mrx_ref_tb and auk_pac_mrx_pl3_link. The Visual IP model is now ready for use in your simulator. Synthesis, Compilation & Place & Route After you have verified that your design is functionally correct, you are ready to perform synthesis and place-and-route. Synthesis can be performed by the Quartus II development tool, or by a third-party synthesis tool. The Quartus II software works seamlessly with tools from many EDA vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. Altera Corporation 43

44 Getting Started Using Third-Party EDA Tools for Synthesis To synthesize your design in a third-party EDA tool, perform the following steps: 1. Create your custom design instantiating a POS-PHY MegaCore function. 2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the POS-PHY MegaCore function instantiation as a black box by either setting attributes or ignoring the instantiation. 3. After compilation, generate a netlist file in your third-party EDA tool. Using the Quartus II Development Tool for Compilation & Place & Route To use the Quartus II software to compile and place-and-route your design, perform the following steps: 1. Select Compile mode (Processing menu). 2. Specify the Compiler settings in the Compiler Settings dialog box (Assignments menu) or use the Compiler Settings wizard. 3. Specify the input settings for the project. Choose EDA Tool Settings (Assignments menu). Select Custom EDIF in the Design entry/synthesis tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list. 4. Add your third-party EDA tool-generated netlist file to your project. 5. Add any.tdf,.vhd, or.v files not synthesized in the third-party tool. 6. Add the pre-synthesized and encrypted.edf file from your working directory, created by the MegaWizard Plug-In Manager. 7. Constrain your design as needed. 8. Compile your design. The Quartus II compiler synthesizes and performs place-and-route on your design. 1 Refer to Quartus II Help for further instructions on performing compilation. 44 Altera Corporation

45 GettingGetting Started Licensing for Configuration Performing Post-Routing Simulation After you have compiled and analyzed your design, you are ready to configure your targeted Altera FPGA. If you are evaluating the POS-PHY Level 2 and 3 Compiler with the OpenCore feature, you must license the function before you can generate programming files. To obtain licenses contact your local Altera sales representative. After you have licensed the core, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-routing simulation of your design. 1. Open your existing Quartus II project. 2. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu). 3. Compile your design with the Quartus II software, see Using the Quartus II Development Tool for Compilation & Place & Route on page 44. The Quartus II software generates output and programing files. 4. You can now import your Quartus II software-generated output files (.edo,.vho,.vo, or.sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation. 2 Getting Started Altera Corporation 45

46 Getting Started 46 Altera Corporation

47 Functional Description The POS-PHY Level 2 and 3 Compiler has two interfaces an A interface and one or many B interfaces. Table 17 shows the possible interfaces. Table 17. Possible s A PHY level 3 (SPHY or MPHY) PHY level 2 (SPHY or MPHY) Link level 3 (SPHY or MPHY) Link level 2 (SPHY or MPHY) Figures 20 and 21 show example interfaces. B PHY level 3 (SPHY only) PHY level 2 (SPHY only) Link level 3 (SPHY only) Link level 2 (SPHY only) Atlantic master (SPHY only) Atlantic slave (SPHY only) 1 Core data flow direction is from source to sink, e.g., data flows from a PHY receive source to a link receive sink. A core must have a minimum of one source and one sink interface. 3 Figure 20. Example Core s Core FIFO 'B1' Source 'A' Sink FIFO 'B2' Source FIFO 'B3' Source FIFO 'Bn'' Source Altera Corporation 47