FFT MegaCore Function

Transcription

1 FFT MegaCore Function March 2007, MegaCore Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the FFT MegaCore function version 6.1. Errata are functional defects or errors, which may cause the FFT MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents. Table 1 shows the issues that affect the FFT MegaCore function v6.1. Table 1. FFT MegaCore function v6.1 Issues Issue Page Variable Streaming FFT Outputs Invalid Data 1 Incorrect Inverse Functionality for Variable Streaming FFT 2 Simulation Errors Synopsys VCS 6 Simulation Errors Incorrect Results 6 Simulation Errors MATLAB Model Mismatch 7 Gate-Level Simulations 8 f For the most up-to-date errata for this release, refer the errata sheet on the Altera website: FFT MegaCore Function v6.1 Issues This section describes the FFT MegaCore function v6.1 issues. Variable Streaming FFT Outputs Invalid Data The variable streaming architecture of the FFT may produce invalid data when the clock enable is taken high, after it is taken low without taking valid and ready low simultaneously. This issue affects the variable streaming architecture FFT. Altera Corporation 1 ES-FFT

2 The design compiles, but can give wrong results. When the clock enable is taken low, the input signals ready and valid must also be taken low. This situation can be achieved by ANDing these input signals with the global clock enable. Alternatively, you can just take ready and valid low, and tie the global clock enable high. This combination also disables the MegaCore function, and can lead to an improved f MAX. Solution status This issue will be fixed in the next release of the FFT MegaCore function. Incorrect Inverse Functionality for Variable Streaming FFT The variable streaming FFT architecture allows you to change the functionality from FFT or inverse FFT, by changing the value of the inverse signal (0 for FFT; 1 for IFFT). The inverse signal should have the same timing characteristics as sink_sop. When sink_sop is asserted and sink_valid and sink_ready are asserted, the value of the inverse port is sampled by the FFT. When inverse is toggled while fftpts remains constant, you will see incorrect output results. If inverse is kept constant, correct inverse functionality is observed. This issue affects all configurations. The design compiles but gives incorrect results. For applications that require dynamic inverse functionality (changing from FFT to IFFT functionality between blocks), you must provide a wrapper to the FFT that implements the inverse functionality. You must change the size of the following signals to suit your configuration. The size of the signals must be the same as the equivalent signals in the toplevel design file, <project name>.vhd. fftpts : in std_logic_vector (10 downto 0); 2 Altera Corporation

3 sink_real : in std_logic_vector (15 downto 0); sink_imag : in std_logic_vector (15 downto 0); source_real : out std_logic_vector (28 downto 0); source_imag : out std_logic_vector (28 downto 0) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity inverse_workaround is port ( clk : in std_logic; reset_n : in std_logic; fftpts : in std_logic_vector (10 downto 0); inverse : in std_logic; sink_valid : in std_logic; sink_sop : in std_logic; sink_eop : in std_logic; sink_real : in std_logic_vector (15 downto 0); sink_imag : in std_logic_vector (15 downto 0); sink_error : in std_logic_vector (1 downto 0); source_ready : in std_logic; sink_ready : out std_logic; source_error : out std_logic_vector (1 downto 0); source_sop : out std_logic; source_eop : out std_logic; source_valid : out std_logic; source_real : out std_logic_vector (28 downto 0); source_imag : out std_logic_vector (28 downto 0) ); end entity inverse_workaround; architecture rtl of inverse_workaround is -- this value is calcuted as ceil(latency/max_fftpts) -- where MAX_FFTPTS = maximum transform size that will be used. -- LATENCY = the latency through the core for MAX_FFTPTS -- this can be established through a simulation for the chosen MAX_FFTPTS -- as the time from sink_eop assertion to the corresponding source_sop -- assertion on the output of the FFT. constant MAX_ADDR_c : natural := 1; -- signals to flag updates to the inverse port on the input and output -- of the FFT signal inverse_d : std_logic_vector(max_addr_c downto 0); signal in_inverse : std_logic; signal in_inverse_reg : std_logic; signal out_inverse : std_logic; -- signals to read the output ports Altera Corporation 3

4 signal sink_ready_s : std_logic; signal source_eop_s : std_logic; signal source_valid_s : std_logic; -- input data after applying the inverse operation signal sink_real_inv : std_logic_vector (sink_real'length - 1 downto 0); signal sink_imag_inv : std_logic_vector (sink_imag'length - 1 downto 0); signal source_real_inv : std_logic_vector (source_real'length - 1 downto 0); signal source_imag_inv : std_logic_vector (source_imag'length - 1 downto 0); -- Megacore FFT component declaration component fft is port ( clk : in std_logic; reset_n : in std_logic; fftpts : in std_logic_vector (10 downto 0); inverse : in std_logic; sink_valid : in std_logic; sink_sop : in std_logic; sink_eop : in std_logic; sink_real : in std_logic_vector (sink_real'length - 1 downto 0); sink_imag : in std_logic_vector (sink_imag'length - 1 downto 0); sink_error : in std_logic_vector (1 downto 0); source_ready : in std_logic; sink_ready : out std_logic; source_error : out std_logic_vector (1 downto 0); source_sop : out std_logic; source_eop : out std_logic; source_valid : out std_logic; source_real : out std_logic_vector (source_real'length - 1 downto 0); source_imag : out std_logic_vector (source_imag'length - 1 downto 0)); end component fft; begin -- update output ports. sink_ready <= sink_ready_s; source_valid <= source_valid_s; source_eop <= source_eop_s; -- if IFFT, swap real/imaginary on input sink_real_inv <= sink_real when in_inverse = '0' else sink_imag; sink_imag_inv <= sink_imag when in_inverse = '0' else sink_real; -- if IFFT, swap real/imaginary on output source_real <= source_real_inv when out_inverse = '0' else source_imag_inv; source_imag <= source_imag_inv when out_inverse = '0' else 4 Altera Corporation

5 source_real_inv; -- FFT top level fft_inst : fft port map ( clk => clk, reset_n => reset_n, fftpts => fftpts, inverse => '0', sink_valid => sink_valid, sink_sop => sink_sop, sink_eop => sink_eop, sink_real => sink_real_inv, sink_imag => sink_imag_inv, sink_error => sink_error, source_ready => source_ready, sink_ready => sink_ready_s, source_error => source_error, source_sop => source_sop, source_eop => source_eop_s, source_valid => source_valid_s, source_real => source_real_inv, source_imag => source_imag_inv); -- Updates the inverse on the top level inverse port in_inverse <= inverse or in_inverse_reg; in_inv_p : process (clk, reset_n) begin if reset_n = '0' then inverse_d <= (others => '0'); in_inverse_reg <= '0'; elsif rising_edge(clk) then if sink_sop = '1' and sink_valid = '1' and sink_ready_s = '1' then inverse_d <= inverse_d(max_addr_c - 1 downto 0) & inverse; in_inverse_reg <= inverse; if sink_eop = '1' and sink_valid = '1' and sink_ready_s = '1' then in_inverse_reg <= inverse; end process in_inv_p; -- updates the inverse flag on the output of the fft. out_inv_p : process (clk, reset_n) begin if reset_n = '0' then out_inverse <= '0'; elsif rising_edge(clk) then if source_eop_s = '1' and source_valid_s = '1' and source_ready = '1' then out_inverse <= inverse_d(max_addr_c); Altera Corporation 5

6 end process out_inv_p; end architecture rtl; Solution status This issue will be fixed in the next release of the FFT MegaCore function. Simulation Errors Synopsys VCS When you use NativeLink to perform an RTL simulation using the generated Verilog HDL testbench in the VCS simulator, you see the following error: Error: VCS: Error-[V2KS] Verilog 2000 IEEE syntax used. Please compile with +v2k Error: VCS: to support this construct Error: VCS: operator '**'. This issue affects all Verilog HDL configurations. There is no design impact; the design compiles correctly. In the Verilog HDL testbench <variation name>_tb.v, replace the power of operator '**' with the calculated value. Alternatively, compile with the +v2k option in the VCS simulator. Solution Status This issue will be fixed in a future version of the FFT MegaCore function. Simulation Errors Incorrect Results When the input is defined as N bit wide, the permissible input range is from 2 N to 2 N 1 1. If the input contains the value 2 N 1, the HDL output is incorrect, and does not match the MATLAB simulation result. 6 Altera Corporation

7 This issue affects all configurations. The design compiles but gives incorrect results. If you expect your input signal to contain the value 2 N 1, you should add a block in front of the FFT, which maps the value 2 N 1 to 2 N Solution Status This issue will be fixed in a future version of the FFT MegaCore function. Simulation Errors MATLAB Model Mismatch For one particular FFT parameter combination, the HDL output does not match the MATLAB simulation results (for some frames of data). HDL simulation results are scaled down by a factor of two compared to the MATLAB simulation results. The exponent value produced by the HDL simulation is one less than the output of the MATLAB simulations. When the exponent is taken into account, the MATLAB and the HDL version may differ by one least significant bit (LSB). This issue affects the following parameter combination: Transform length: 64 I/O data flow: burst architecture FFT engine architecture: quad output Number of parallel engines: 2 There is no design impact, the design compiles and operates correctly. This issue has no workaround. Altera Corporation 7

8 Contact Information Solution Status This issue will be fixed in a future version of the FFT MegaCore function. Gate-Level Simulations The testbench provided with the FFT MegaCore function is not suitable for gate-level simulations. The testbench assumes zero delays in postfitting simulation models. Therefore, running gate-level simulations using the testbench may produce incorrect simulation results. This issue affects all configurations. There is no design impact; the design compiles correctly. Provide appropriate input and output constraints using the Quartus II Assignments Editor and create a testbench that matches these requirements. Solution Status This issue will be fixed in a future version of the FFT MegaCore function. Contact Information For more information, contact Altera's mysupport website at and click Create New Service Request. Choose the Product Related Request form. Revision History Table 2 shows the revision history for FFT MegaCore function version 6.1. Table 2. Revision History Version Date Errata Summary 1.2 March 2007 Added Variable Streaming FFT Outputs Invalid Data issue. 1.1 February 2007 Added Incorrect Inverse Functionality for Variable Streaming FFT issue. 1.0 December 2006 First release. 8 Altera Corporation

9 Revision History 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation 9