RapidIO MegaCore Function

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1 March 2007, MegaCore Function Version Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version Errata are functional defects or errors, which may cause the RapidIO MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents. f For the most up-to-date errata for this release, refer to the errata sheet on the Altera website: RapidIO MegaCore Function Version Issues Altera has identified the issues in Table 1 that affect the RapidIO MegaCore function v3.1.0 in the following ways: Functional Issues: a defect or design issue that needs an enhancement or will be fixed in a future release Usage Issues: a process change or parameter you need to specify Documentation Issues: an addition, correction, clarification, or change to the documentation. Table 1. v3.1.0 Issues (Part 1 of 2) Category Issue Page Functional Issues A Scheduled Transmission Packet Can Be Dropped by the Physical Layer 2 Invalid MegaCore Generated When a Baud Rate of 1.25 Gbaud or Lower Is Selected for Stratix II GX Devices 3 Port Writes Are Not Supported 4 Output Signals io_s_rd_readdatavalid and io_s_rd_readerror Undefined for 4 One Clock Cycle I/O Write Request Writes Corrupted Data 5 Timeout and Interrupt Occur When Transport Layer Processes an Odd 6 Number of Consecutive 64-bit Packets Input-Output Avalon Master Returns Incorrect Read Data 7 Invalid Data Read From RXSYM Register If RXCTRL Register Bit Zero Not 7 Set Read Response Can Be Lost 8 Altera Corporation 1 ES-RPD_

2 Table 1. v3.1.0 Issues (Part 2 of 2) Functional Issues Usage Issues Category Issue Page Control Symbol Transmit Queue Not Cleared Properly When MegaCore Function Is Reset IP Toolbench Fails When Generating IP Functional Simulation Models for HardCopy Stratix Devices IP Toolbench Allows Invalid Data Path Widths 10 A Transport Layer Variation Requires at Least One Logical Layer Module or 11 Generic Port Some Serial Variations Cause Compilation Errors Documentation Issues IO Slave Window n Control Register Table Changes in RapidIO User Guide 12 Output Port txclk Description Functional Issues This section contains functional issues which can include defects or design issues that require an enhancement or will be fixed in a future release. A Scheduled Transmission Packet Can Be Dropped by the Physical Layer A packet scheduled for transmission can be dropped by the Physical layer. This issues affects all x4 Serial RapidIO variations that use large interpacket gaps. The RapidIO specification requires the transmission of a control symbol containing the buf_status field, at least every 1024 transmitted code groups. If normal traffic does not cause the transmission of a control symbol containing the buf_status field within that time, the RapidIO MegaCore function forces a Status control symbol to be issued. If the forced Status control symbol coincides with the start of the transmission of a packet, the packet can be lost. 2 Altera Corporation

3 Functional Issues To avoid this issue, do one of the following: Upgrade to release 6.1 or later of the RapidIO MegaCore function. Avoid large interpacket gaps and use reliable traffic packet types for packets that must not be lost. This issue is fixed in release 6.1 of the RapidIO MegaCore function. Invalid MegaCore Generated When a Baud Rate of 1.25 Gbaud or Lower Is Selected for Stratix II GX Devices Although Stratix II GX devices are only characterized for RapidIO at Gbaud, the MegaWizard lets you generate a variation running at a lower baud rate. Variations with baud rates of 1.25 Gbaud or lower are incorrectly generated. Variations with baud rates higher than 1.25 Gbaud should operate correctly, but have not been characterized yet. Affected Configuration Affected configurations includes an serial RapidIO variation in Stratix II GX devices with baud rates other than Gbaud. Quartus II software fails to compile variations with baud rates lower than 1.25 Gbaud. Work around You can use the following workarounds to avoid this issue: Use a baud rate of Gbaud when using Stratix II GX devices. Use Stratix GX devices or an external serdes for baud rates of 1.25 Gbaud or lower. Upgrade to release 6.1 or later of the RapidIO MegaCore function. Support for 1.25 Gbaud has been added to the RapidIO MegaCore function in the 6.1 release. Altera Corporation 3

4 Port Writes Are Not Supported This release of the RapidIO MegaCore function does not support port writes. Any configuration requiring port writes is not supported. Port writes are not supported. Upgrade to version 6.1 of the Rapidio MegaCore function. This issue is fixed in version 6.1 of the RapidIO MegaCore function. Output Signals io_s_rd_readdatavalid and io_s_rd_readerror Undefined for One Clock Cycle When simulating read transfers on the Input/Output slave module's Avalon-Memory Management read slave interface with the IP Functional model, the io_s_rd_readdatavalid and io_s_rd_readerror signals are undefined (value =x) for one clock cycle shortly after the read transfer is initiated. This has been observed only with burst counts with a value of 1, 2, or 3. All variations that include an Input/Output Avalon-MM Slave logical layer module. When the burst count is 1, 2, or 3, the io_s_rd_readdatavalid and io_s_rd_readerror signals are undefined for one clock cycle shortly after the read transfer is initiated. Therefore, read transactions with burstcounts of 1, 2, or 3 cannot be used reliably. Specify burst counts larger than 3. 4 Altera Corporation

5 Functional Issues This issue is fixed in RapidIO MegaCore function version I/O Write Request Writes Corrupted Data If an invalid combination of burstcount, byteenable, and address is applied to the datapath write Avalon slave interface, the RapidIO I/O Logical Layer module sometimes generates an incorrect write request packet. Examples of invalid combinations of burstcount, byteenable, and address are listed below: If io_s_wr_address[2] is a not zero or a burstcount has an odd value for an address that maps to an SWRITE transfer in a 32-bit wide variation If a byteenable does not translate into a valid wrsize and wdptr pair, for example byteenable set to 0xAA If a byteenable a value other than 0xFF for an address that maps to an SWRITE transfer in a 64-bit wide variation This issue affects all 32-bit (and possibly 64-bit) variations that include an I/O Logical Layer module. The Avalon Slave interface may send an incorrect write request packet. Avoid invalid burstcount, byteenable and address combinations. This issue has been fixed in release 6.1 of the RapidIO MegaCore function. Altera Corporation 5

6 Timeout and Interrupt Occur When Transport Layer Processes an Odd Number of Consecutive 64-bit Packets When an odd number of consecutive 64-bit packets from the same upper layer module is sent, the Transport layer misses the end-of-packet signal of a 64-bit packet and processing stalls, which results in a port response timeout and the RapidIO MegaCore function issues an interrupt. The duration of a port response timeout can vary between approximately 3.5 seconds and a few clock cycles, depending on the value of the Port Response Time Out Control CSR (PRTCTRL) register. This issue affects all configurations that include the Maintenance or Input/Output Logical layer modules and that have a 64-bit data width. This issue causes a port response timeout in the Maintenance or Input/Output Logical layer modules. A port response timeout occurs when a request packet that requires a response is sent but no response packet is received within the duration specified by the Port Response Time-out Control CSR (PRTCTRL) register. The timeout is not fatal, an interrupt is issued, and the application software needs to handle the interrupt appropriately. The workaround for this issue is to shorten the port response timeout by specifying a smaller value in the PRTCTRL register and ensure that the application software handles the timeout interrupts appropriately when they occur. This issue will be fixed in the next release. 6 Altera Corporation

7 Functional Issues Input-Output Avalon Master Returns Incorrect Read Data If the io_m_rd_readdatavalid signal is toggled within an Avalon read burst transfer, the Input-Output Avalon master module will sometimes return incorrect data in the read response packet. This issue affects all RapidIO MegaCore functions with a 32-bit wide Input-Output Avalon master read datapath interface. Design impact The design impact for this issue can be incorrect returned read data. Work around A workaround for this issue is to use single word transfers or ensure the io_m_rd_readatavalid signal is asserted continuously for the entire duration of the burst. For example, do not deassert io_m_rd_readdatavalid within a burst transfer after assertion of the io_m_rd_readdatavalid signal has begun. Solution status This issue will be fixed in next release. Invalid Data Read From RXSYM Register If RXCTRL Register Bit Zero Not Set Invalid data is read from the RXSYM register (address 'h10028) if bit 0 of the RXCTRL (address 'h10020) register is not set. All parallel RapidIO MegaCore functions are affected by this issue. Data read from the RXSYM register will be invalid unless you set bit 0 of the RXCTRL register before reading the RXSYM register. Set bit 0 of the RXCTRL register before reading the RXSYM register. Altera Corporation 7

8 This issue will be fixed in next release. Read Response Can Be Lost If a read response is received by the Input/Output Avalon Slave module at the same time it issues a request, the read response can be lost. This issue affects all RapidIO MegaCore functions that include the Input- Output Avalon slave module. The loss of the read response packet causes a port-response timeout to occur, which causes the read transaction to fail, the io_s_rd_readerror signal is asserted, and normal operation then resumes. You can work around this issue by using one of the following options: Issue only one read request at a time and wait for the response before issuing the next request, thus using a nonpipelined operation. Reduce the duration of the port link timeout as much as possible and have the application software manage the read error. This issue will be fixed in the next release. 8 Altera Corporation

9 Functional Issues Control Symbol Transmit Queue Not Cleared Properly When MegaCore Function Is Reset The control symbol transmit queue is not cleared properly when the MegaCore function is reset. If both end points of a link come out of reset at the same time but not all the received packets had been acknowledged before the reset, one of the end points can transmit an unexpected packet-accepted control symbol immediately after the reset. Transmission of this unexpected packetaccepted causes the other end point to enter an input-error-stopped state. If these events occur before the link end point that is in the input-errorstopped state has received seven status control symbols, this link end point cannot send the required link-request input-status control symbol. The link end point sits in the input-error-stopped state waiting for a link response until it eventually times out, which invokes normal error recovery and normal operation should resume. A link timeout can occur after reset. This issue can affect all RapidIO MegaCore functions To work around this issue, use one of these two options: Avoid resetting both link ends close together before all packets have been acknowledged. Allow sufficient time for the two end points to recover from reset to ensure that the receiving end point has received seven status control symbols before the transmitting end point sends an unexpected packet-accepted control symbol. Set the port link timeout to a sufficiently short value to ensure it does not adversely impact the time required to come out of reset. If the timeout is short enough when this error occurs, the recovery cycle will be minimal. This issue will be fixed in the next release of the RapidIO MegaCore function. Altera Corporation 9

10 Usage Issues This section contains usage issues which can include process changes or parameters that you need to specify. IP Toolbench Fails When Generating IP Functional Simulation Models for HardCopy Stratix Devices If you select HardCopy Stratix in the MegaWizard Plug-In Manager and you turn on Generate Simulation Model and Generate a MegaCore function variation, IP Toolbench fails with an error. This issue affects all configurations. You cannot generate an IP functional simulation model. Select the Stratix family in the MegaWizard Plug-In Manager. This issue will be fixed in a future release of the Quartus II software. IP Toolbench Allows Invalid Data Path Widths IP Toolbench allows you to choose a 32-bit data path width instead of the required 64 bits for 4 Serial RapidIO MegaCore function variations where the baud rate is above 1,250 Mbaud, and as a result generates an illegal variation. This issue affects all 4 Serial RapidIO MegaCore function variations that use a baud rate above 1,250 Mbaud. The invalid variations will fail in compilation or simulation. Ensure that you select 64-bit wide data paths for 4 serial variations that use baud rates above 1,250 Mbaud. 10 Altera Corporation

11 Usage Issues This issue will be fixed in a future release of the RapidIO MegaCore function. A Transport Layer Variation Requires at Least One Logical Layer Module or Generic Port If you generate a variation that has a Transport Layer but no Logical Layer module and no generic port, this variation will have no Avalon or Atlantic interfaces. This issue affects configurations that use the Transport Layer but no Logical Layer modules. Your MegaCore function will have no access to the transmit or receive data streams. In IP Toolbench, regenerate the variation and ensure that you select at least one Logical Layer module or the generic port. This issue will be fixed in a future release of the RapidIO MegaCore function. Some Serial Variations Cause Compilation Errors Some 4 Serial RapidIO MegaCore function variations do not compile in the Quartus II software. This issue affects variations that use the Stratix II GX device family and transceiver, a 32-bit Atlantic data path width, and a baud rate of 3,125 Mbaud. Altera Corporation 11

12 The Quartus II software exits with an error. Select a 64-bit Atlantic data path width. This issue will be fixed in a future release of the RapidIO MegaCore function. Documentation Issues This section contains documentation issues which can include additions, corrections, clarifications, or changes to the documentation. IO Slave Window n Control Register Table Changes in RapidIO User Guide In the current Rapid IO MegaCore Function User Guide, Table IO Slave Window n Control requires the following changes: The range for field RSRV should be 5:2. NWRITE_R_ENABLE, bit 0, should be the last entry in the table. The corrected table is below. Table 2 1. IO Slave Window n Control Offset: 'h1040c, 'h1041c, 'h1042c, 'h1043c, 'h1044c, 'h1045c, 'h1046c, 'h1047c, 'h1048c, 'h1049c, 'h104ac, 'h104bc, 'h104cc, 'h104dc, 'h104ec, 'h104fc Field Bit Access Function Default RSRV 31:24 RO Reserved. 8 MSB for 16-bit DestinationID 8'h0 DESTINATION_ID 23:16 RW 8 least significant bits of DestinationID 8'h0 RSRV 15:8 RO Reserved 8'h0 PRIORITY 7:6 RW Packet priority 2'h0 RSRV 5:2 RO Reserved 4'h0 SWRITE_ENABLE 1 RW SWRITE enable. Set to one to generate 1'b0 SWRITE request packets. (1) NWRITE_R_ENABLE 0 RW NWRITE_R enable (1) 1'b0 Note to Table 2 1: (1) Bits 0 and 1 (NWRITE_R_ENABLE and SWRITE_ENABLE) are mutually exclusive. If ones are written to both of these fields at the same time, these values will be ignored and the register will retain its previous value. 12 Altera Corporation

13 Documentation Issues This issue affects any configuration for which this information is used. There is no design impact. Use the information in the table supplied. These corrections will be made in the next User Guide revision. Output Port txclk Description The description of the output port txclk is not sufficient in the current User Guide. The output port txclk is an internal system clock on the physical layer, which is derived by dividing the reference clk by one, two, or four depending on the MegaCore function s configuration. A flip-flop based circuit does the division of the reference clk required to derive the txclk. The circuitry required to do the division does not require a dedicated PLL. This documentation issue affects all MegaCore functions that require this information. This issue has no design impact.. Read the description above to obtain the needed information about the txclk.. This information will be in the next revision of the RapidIO MegaCore Function User Guide. Altera Corporation 13

14 Contact Information Revision History For more information, contact Altera's mysupport website at and click Create New Service Request. Choose the Product Related Request form. Table 3 shows the revision history for the v3.1.0 Errata Sheet. Table 3. v3.1.0 Errata Sheet Revision History Version Date Errata Summary 1.2 March 2007 The following errata have been added: A Scheduled Transmission Packet Can Be Dropped by the Physical Layer Invalid MegaCore Generated When a Baud Rate of 1.25 Gbaud or Lower Is Selected for Stratix II GX Devices Port Writes Are Not Supported Output Signals io_s_rd_readdatavalid and io_s_rd_readerror Undefined for One Clock Cycle erratum was added to this update. 1.1 June 2006 The following errata have been added: Input-Output Avalon Master Returns Incorrect Read Data Invalid Data Read From RXSYM Register If RXCTRL Register Bit Zero Not Set Read Response Can Be Lost Control Symbol Transmit Queue Not Cleared Properly When MegaCore Function Is Reset IO Slave Window n Control Register Table Changes in RapidIO User Guide Output Port txclk Description 1.0 April 2006 First release. 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Literature Services: literature@altera.com Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 14 Altera Corporation

RapidIO MegaCore Function

March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects