ispdownload Cable Reference Manual

Transcription

1 ispdownload Cable Reference Manual Version 3.0 Technical Support Line: LATTICE or (408) pds4102-dl-um Rev 3.0.2

2 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor. Information in this document is subject to change without notice. The distribution and sale of this product are intended for the use of the original purchaser only and for use only on the computer system specified. Unauthorized copying, duplicating, selling or otherwise distributing this product is a violation of the law. Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation: Generic Array Logic, ISP, ispate, ispcode, ispdcd, ispdownload, ispds, ispds+, ispgds, ispgdx, isphdl, ispjtag, ispstarter, ispstream, ispta, isptest, ispturbo, ispvector, ispverilog, ispvhdl, Latch-Lock, LHDL, pds+, RAL, RFT, and Total ISP, TwinGLB are trademarks of Lattice Semiconductor Corporation. E 2 CMOS, GAL, ispgal, isplsi, pds, plsi, Silicon Forest, and UltraMOS are registered trademarks of Lattice Semiconductor Corporation. AMP is a registered trademark of AMP, Inc. Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, OR (503) November 1997 ispdownload Cable Reference Manual 2

3 Limited Warranty Lattice Semiconductor, Inc., warrants the original purchaser that the ispdownload Cable shall be free from defects in material and workmanship for a period of 90 days from the date of purchase. If a defect covered by this limited warranty occurs during this 90-day warranty period, Lattice Semiconductor will repair or replace the component part, at its option, free of charge. This limited warranty does not apply if the defects have been caused by negligence, accident, unreasonable or unintended use, modification, or any causes not related to defective materials or workmanship. To receive service during the 90-day warranty period, contact Lattice Semiconductor Corporation at: Phone: LATTICE Fax: 1 (408) applications@latticesemi.com If Lattice Semiconductor support personnel are unable to solve your problem over the phone, we will provide you with instructions on returning your defective ispdownload Cable to us. The cost of returning the product to the Lattice Semiconductor Service Center shall be paid by the purchaser. Limitations on Warranty Any applicable implied warranties, including warranties of merchantability and fitness for a particular purpose, are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein. In no event shall Lattice Semiconductor, Inc., be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties. Purchaser s sole remedy for any cause whatsoever, regardless of the form of action, shall be limited to the price paid to Lattice Semiconductor for the ispdownload Cable. The provisions of this limited warranty are valid in the United States only. Some states do not allow limitations on how long an implied warranty lasts, or exclusion of consequential or incidental damages, so the above limitation or exclusion may not apply to you. This warranty provides you with specific legal rights. You may have other rights which vary from state to state. ispdownload Cable Reference Manual 3

4 Table of Contents Download Overview Hardware Programming Tools ispdownload Cable isp Engineering Kit Model Programming Software Tools ISP Daisy Chain Download ispcode ISP Programming Times Lattice ISP Design Flow ISP Device Interfaces ispjtag Programming ispen Function Lattice ISP Daisy Chain Details Similarities and Differences Between Devices ISP Programming for Mixed Lattice ISP interface and ispjtag interface Systems Board Layout Considerations ispdownload Cable Connecting the ispdownload Cable ispdownload Cable Reference Manual 4

5 Download Overview Download Overview This document describes how to assemble and use the Lattice Semiconductor Corporation (LSC) ispdownload Cable to perform in-system programming of LSC in-system programmable (ISP ) devices. The ispdownload Cable, in conjunction with included software utilities ispdaisy Chain Download (ispdcd ), ispate, ispcode, and ispgds facilitates in-system programming of ISP devices from the parallel port of a PC. The ispdownload cable is designed for engineering purposes only and is not intended for production use. It is not intended for high volume programming environments. Users are strongly urged to insure proper cable operation (e.g. no bent pins, continuity, etc.) before initiation of device programming. The following sections describe the ISP programming hardware and software, ISP design flow, ISP device hardware interface basics, daisy chain configurations and interfaces, board layout considerations, and cable components and connections. See the ISP Daisy Chain Download Reference Manual for detailed instructions on programming devices. All ISP programming specifications such as the programming cycle and data retention are guaranteed when programming ISP devices over the commercial temperature range (0 to 70 0 C). It is critical that the programming and bulk erase pulse width specifications are met by the programming platform to insure proper insystem programming. The details of device programming are transparent to the user if Lattice ISP programming hardware and software are used. Hardware Programming Tools ispdownload Cable The ispdownload cable is designed to facilitate in-system programming of all LSC ISP devices on a printed circuit board directly from the parallel port of a PC. After completion of the logic design and creation of a JEDEC file by the ispds, ispds+, ispgdx, or ispgds compiler software, LSC s ISP Daisy Chain Download software programs devices on the end-product printed circuit board by generating programming signals directly from the parallel port of a PC, which then pass through the ispdownload cable to the device. With this cable and a connector on the board, no additional components are required to program a device. ispdownload Cable Reference Manual 5

6 Download Overview Hardware design considerations for new boards include whether the hardware designer will be using boundary-scan test operations or low voltage (3.3V) devices. In a system using 3.3V ISP devices, the ispdownload cable version 2.0 must be used. In addition, mixed Lattice ISP and ispjtag chains require version 2.0. The cable operates with either a 3.3V or 5V Vcc source from the target board. Lattice Semiconductor s ISP Daisy Chain Download software makes the ISP software interface to 3.3V and mixed-voltage systems transparent to the user. isp Engineering Kit Model 100 The isp Engineering Kit Model 100 provides designers with a quick and inexpensive means of programming and verifying fuse data patterns on single unmounted Lattice isplsi devices. This kit is designed for engineering purposes only and is not intended for production use. During the development phase of an isplsi design project, the ability to reprogram isplsi devices and move them between different hardware platforms can be provided by using the Model 100. In addition, the ispdownload cable, which is provided as an integral part of this kit, allows the user to implement the full power of Lattice Semiconductor s ISP feature when ISP devices are daisy chained on a target system board. The Model 100 can be used with all versions of Lattice s PC based ISP Daisy Chain Download software. All the functions of ISP programming operations are easily implemented on this user friendly programming tool. The Model 100 is provided with the items shown in Figure 1. You must purchase the specific programming socket adapter boards for the devices that will be used. Socket adapter boards are available for all Lattice Semiconductor ISP devices. NOTE For 3.3V operation, a 3.3V programming socket adapter board is required. Programming Software Tools Once the JEDEC file has been generated for a given design, the design information is ready to be downloaded onto the proper device. The download method depends on the hardware available and the design stage. For example, the designer might program the system with ISP devices during prototyping using a PC. Then, when the system goes to full production, an ATE can be used for programming. Finally, if field updates are necessary, the system s embedded microprocessor can reprogram the ISP devices. ispdownload Cable Reference Manual 6

7 3 25-pin parallel port adapter Place adapter on parallel port behind security key RJ-45 connector eight positions RJ-45 connector eight positions 1 - Programming Module 2 - Power Supply Converter (9VDC) 3-25-pin Parallel Port Adapter 5 isp Engineering Kit Components 4-6 Universal Programming Module Cable 5-6 System Download Cable with Modular AMP Connector 4 AMP connector.100 center-spacing, eight positions Front view AMP Connector pinout RJ-45 connector eight positions VCC SDO/TDO SDI/TDI ispen/bscan Plug MODE/TMS From Board GND From Board.01 µf SCLK/TCK capacitor Note: Capacitor required between ispen and GND pins. Locate capacitor as close as possible to ISP device. Note: Capacitor requirement is not necessary for ispgds and ispgal22v DC Power Plug Universal Programming Module - Socket Adapter (purchased separately) Power Supply Converter 200 ma Positive or Negative +/- 5.5 mm 2.1 mm - Sample Device Figure 1. isp Engineering Kit Model 100

8 Download Overview ISP Daisy Chain Download ISP Daisy Chain Download (ispdcd) software supports programming of all Lattice Semiconductor ISP devices through a serial daisy chain programming configuration in a PC environment. The ispdcd software is built around a graphical user interface. Device chains can be scanned automatically. Any required JEDEC files are selected by browsing with a built-in file manager. This software supports both serial and parallel (turbo) programming of both LSC ISP interface and ispjtag interface daisy chains. ispdcd software versions 5.0 and higher, in conjunction with ispdownload cable version 2.0, support mixed Lattice ISP interface and ispjtag interface daisy chains, and mixed 3.3V and 5V daisy chains. The ability to edit the UES in a JEDEC file in either HEX or ASCII format is built into the software. In addition, the UES of all the Lattice devices can be read and displayed. The software also includes LSC s ispate test-vector creation utility that facilitates programming of Lattice ISP devices on HP, Teradyne, Marconi, and GenRad testers. ispate converts a standard JEDEC file into a programming vector template that can be easily incorporated into a product s printed circuit board functional test program. A generic ASCII vector format is generated to help support any ATE not directly supported. The programming vectors can also be driven through the ispdownload cable from the ispdcd software. ispcode ispcode is an ANSI C-source code that facilitates in-system programming of LSC ISP devices from UNIX systems, PCs, testers, and embedded systems. The ispcode software supplies extensively commented code for incorporation into userapplication programs. In addition, compiled DOS command-line versions of this code are included with this package. The C-source code is the best place to start for anyone writing customized code. It illustrates the programming algorithm and has been thoroughly tested. ISP Programming Times To minimize the total programming time of a daisy chain of ISP devices, a programming method called ispturbo Download can be used with the ISP Daisy Chain Download software to program all the ISP devices in the chain concurrently. ispturbo Download allows programming of up to 100 ISP devices in the time it takes to program the largest LSC device in the chain. ispturbo Download is supported in ispcode as well. For example, a chain of three devices with programming times of ten, seven, and seven seconds can be programmed with ispturbo Download in a total of ten seconds (the time it takes to program the largest device). Serially, the programming time would be 24 seconds for all three devices. This valuable feature of LSC s proprietary UltraMOS E 2 CMOS technology is not available with any other ISP CPLD device technologies. ispdownload Cable Reference Manual 8

9 Lattice ISP Design Flow Lattice ISP Design Flow As with other Programmable Logic Devices (PLDs), the basic ISP design flow includes design entry, compiling and fitting the design, generating a JEDEC standard fuse map file and programming the device (Figure 2). Hardware Description Language (HDL) synthesis and simulation are optional. Design Entry Pre-Route Simulation HDL Synthesis Compilation and Device Fitting Post-Route Simulation JEDEC Fuse Map File Programming Figure 2. ISP Design Flow After the conceptual stage of the logic or system design, a software design entry tool for implementing the logic functions, state machine, or schematic design must be selected. Lattice Semiconductor Corporation supports proprietary and various thirdparty software tools that allow users a choice of design entry methods. These include Boolean equation entry, state machine, hardware description language (such as VHDL and Verilog), and/or schematic entry. The goal is to consolidate the logic functions into a reduced set of equations that can be compiled for a given device. Once device fitting is accomplished and the JEDEC file has been created, the device is ready to be programmed. Programming consists of converting the JEDEC fuse map file into a serial data format and shifting it into the device. Lattice Semiconductor has various methods for supporting programming on a variety of platforms. ispdownload Cable Reference Manual 9

10 ISP Device Interfaces Lattice ISP Design Flow Once the fuse map is complete, the data can be serially shifted into the device along with the appropriate addresses and commands. Traditionally, programmable logic devices have been programmed on PLD/PROM programmers which require that all programming signals and algorithms be generated by the programmer. The programmer also generates the external super voltage required by non-isp devices (typically volts). This super voltage requirement is one of the reasons that dedicated programmers are used to program conventional PLDs. With ISP devices, the ISP programming super voltage is generated within the device from the 3.3V or 5V power supply. Lattice Semiconductor ISP devices use nonvolatile E 2 CMOS technology and require only 3.3V or 5V TTL-level programming signals. An integrated state machine controls the sequence of programming operations such as identifying the ISP device, shifting in the appropriate data and commands, and controlling internal signals to program and erase the E 2 cells in the device. Programming consists of serially shifting the logic implementation, stored in a JEDEC file, into the device along with appropriate address and commands, programming the data into the E 2 CMOS logic elements, and shifting the data from the logic array out for device programming verification. The programming interface to Lattice ISP devices is controlled by either the original proprietary Lattice ISP protocol or the ispjtag protocol based on IEEE Standard Boundary-Scan Test Access Port (TAP). The Lattice ISP interface controls an optimized three-state programming state machine while the ispjtag interface controls programming through an IEEE specified 16-state state machine. LSC s isplsi 1000/E and 2000 families, and the ispgds and ispgal families, are all programmed exclusively through the Lattice ISP interface. The isplsi 2000V family is programmed exclusively through the ispjtag interface. The ispgdx, and isplsi 3000 and 6000 families can be programmed through either interface. ispdownload Cable Reference Manual 10

11 Lattice ISP Design Flow The basic elements of the Lattice ISP interface are the mode control (MODE), serial data in (SDI), serial data out (SDO), and serial clock (SCLK) signals (Figure 3). The internal three-state state machine, which determines whether the device is in the normal operation state or the programming states, is controlled by the four ISP programming pins. MODE and SDI furnish control inputs to the state machine, SDI and SDO make up the programming data inputs and outputs to and from the internal shift register, and SCLK provides the clock. SDO SDI MODE SCLK ispen 5-Wire ISP Interface isplsi ispgal ispgds isplsi 1000/E 22V Figure 3. ISP Programming Interface ispdownload Cable Reference Manual 11

12 ispjtag Programming Lattice ISP Design Flow Lattice Semiconductor offers more JTAG in-system programmable and testable CPLDs than any other manufacturer. As specified in the IEEE Standard , the TAP controller interface must include the Test Mode Select (TMS), Test Data In (TDI), Test Data Out (TDO) and Test Clock (TCK) signals (Figure 4). These signals perform similar duty for state machine control as the Lattice ISP interface connections MODE, SDI, SDO, and SCLK respectively. However, the TAP controller state machine is exclusively controlled by the TMS signal and TDI is used only for shifting in data and instructions. An optional Test Reset (TRST) pin is included on some devices to asynchronously reset the TAP controller. TDO TDI TMS 5-Wire ispjtag Interface TCK ispen/bscan isplsi isplsi isplsi isplsi 2128V 2128V 2032V 2032V ispen Function Figure 4. ispjtag Interface The isplsi 1000/E and 2000 families use a fifth programming pin, ispen, to multiplex the functions of the SDI, SDO, SCLK, and MODE pins between ISP functions during programming and user-defined logic functions during normal PLD operations. The isplsi 2000V family uses ispen to multiplex the functions of the TDI, TDO, TCK, and TMS pins between TAP controller functions and user-defined logic functions. The isplsi 3000 and 6000 families use a fifth pin, ispen/bscan, to select either the Lattice ISP interface or the ispjtag interface. ispdownload Cable Reference Manual 12

13 Lattice ISP Daisy Chain Details Lattice ISP Design Flow This section provides a detailed look at the issues associated with daisy chain programming. Before examining the details, the reader should understand the differences between Lattice ISP devices. This section describes those differences and the unique programming features of each Lattice ISP device. Similarities and Differences Between Devices For the purpose of cascading, Lattice ISP devices can be categorized into five device groups: the ispgds and ispgal families; the isplsi 1000/E and 2000 families; the isplsi 3000 and 6000 families; the ispgdx family; and the isplsi 2000V family of devices. Table 1 compares these device groups. Table 1. ISP Device Daisy Chain Comparison ispgds and ispgal Families isplsi1000/e and 2000 Families isplsi 3000 and 6000 Families ispgdx Family isplsi 2000V Family ISP Interface Yes Yes Yes Yes No ispjtag Interface Boundary Scan Test No No Yes Yes Yes No No Yes Yes No Device ID 8-Bit ISP ID 8-Bit ISP ID 8-Bit ISP ID 8-Bit ISP ID and 32-Bit Boundary Scan IDCODE 32-Bit Boundary Scan IDCODE The ispgds and ispgal families use only the Lattice ISP interface. The I/Os of ispgds and ispgal devices are put into a high impedance state when the programming state machine goes into the Command Shift State. The ispgds and ispgal devices do not use a dedicated ispen pin for this function. The isplsi 1000/E and isplsi 2000 families are programmed exclusively through the Lattice ISP interface but also use the dedicated ispen pin to enable the programming mode; by driving ispen low, all of the device I/Os are put into a high-impedance state and the programming functions for SDI, SDO, MODE and SCLK are enabled. ispdownload Cable Reference Manual 13

14 Lattice ISP Design Flow The isplsi 3000 and isplsi 6000 families are programmable through either the Lattice ISP interface or the ispjtag interface. By driving ispen/bscan to low, all the device I/Os are put into the high-impedance state, the programming functions for SDI, SDO, MODE and SCLK are enabled, and the device enters the programming mode. When ispen/bscan is high, the TAP controller is active and the functions for TDI, TDO, TMS, and TCK are enabled. With the TAP controller active, the device I/Os can also be put into the high-impedance state by loading and executing the Program Enable (ProgEN) instruction. To put the devices into the programming mode, the ProgEN instruction is loaded and executed three times in succession. When the TAP controller is active, boundary-scan test operations are available for the isplsi 3000 and isplsi 6000 families of devices. In summary, if ispen/bscan is not connected to Vcc, the active pull-up will activate the ispjtag. To program using the Lattice ISP interface, ispen/bscan needs to be brought out to the interface connector. The ISP pins on the ispgdx family function only as part of the Lattice ISP or ispjtag interface. ispen/bscan functions the same as in the isplsi 3000 and isplsi 6000 families to select which interface is active. The isplsi 2000V family of devices is programmed exclusively through the boundaryscan TAP controller. A dedicated ispen pin multiplexes the functionality of the programming pins. When ispen is held low, the TAP controller is active and the functions for TDI, TDO, TMS, and TCK are enabled. The device enters the programming mode after the Program Enable instruction is loaded and executed three times in succession. Device I/Os go to the high-impedance state after the first ProgEN instruction is loaded. When ispen is high, the dual-function mode of the ISP pins is available to the functional logic. Unless the extra dedicated inputs are required by the functional logic, ispen can be connected to ground. If devices that use the same interface for programming are put in a serial daisy chain, it is possible to program multiple ISP devices by operating all the state machines in parallel. This synchronizes all the devices within the daisy chain to a known state. However, having all ISP devices in the same state does not mean that all devices are executing the same instruction. The ability of each device in the daisy chain to execute a different instruction makes it possible to selectively program one or multiple ISP devices at a time (Figure 5). ispdownload Cable Reference Manual 14

15 Lattice ISP Design Flow TDO TDI TMS TCK 4-Wire ispjtag Interface VCC ispen/bscan VCC ispen/bscan VCC ispen/bscan isplsi isplsi isplsi 2000V ispgdx ispen Figure 5. ispjtag Programming Interface The internal device layout is the same for all isplsi devices regardless of programming interface used. The isplsi devices have separate address and data shift commands. The row(s) are selected by the address that is shifted-in prior to each programming command. The data can then be shifted with the data-shift instruction. With ispgds and ispgal devices, both address and data are shifted-in with a single shift command (the address is part of the data shift register). When executing commands that only require a row address, a dummy data stream or no data can be shifted in place of the data stream. ispdownload Cable Reference Manual 15

16 Lattice ISP Design Flow ISP Programming for Mixed Lattice ISP interface and ispjtag interface Systems This section discusses the hardware interface when Lattice ISP interface devices are mixed with ispjtag interface devices on the same board. Following a few simple procedures will result in first time success for programming all ISP devices. Described here are the most typical configurations for system design based on common ISP and testability goals. In general, most of the signals from the Lattice ISP interface can be common with the corresponding ispjtag interface signals. This includes SDI and TDI, MODE and TMS, SDO and TDO, and SCLK and TCK. A parallel programming configuration can be used where the Lattice ISP interface devices and the ispjtag interface devices are in two separate chains, both fed by SDI/TDI and combining SDO/TDO at the end of the chains (Figure 6). The ispen pin can be used to disable the Lattice ISP interface chain. When these devices are not in programming mode, the ISP pins are in a high impedance state and will not affect the programming of ispjtag devices. When programming the Lattice ISP interface devices, the TDO pin from ispjtag devices needs to be in the high-impedance state so programming of the Lattice ISP interface daisy chain will not be affected. Using the appropriate hardware and software from Lattice Semiconductor will remove this programming challenge. SDO/TDO SDI/TDI MODE/TMS 5-Wire ISP and ispjtag Mixed Interface SCLK/TCK ispen VCC or NC ispen isplsi isplsi isplsi isplsi 1000/E 1000/E V ispen NC = no connect Figure 6. Mixed ISP and ispjtag Programming Interface ispdownload Cable Reference Manual 16

17 Board Layout Considerations Lattice ISP Design Flow All ISP devices are shipped from Lattice with a fuse pattern that will put all I/O pins into the high impedance state prior to programming. This configuration prevents the ISP devices from driving unwanted signals to other devices in the system before they can be properly programmed. The isplsi 3000, isplsi 6000, and ispgdx families can exist in either a boundaryscan or a Lattice ISP interface serial daisy chain for test and programming purposes. The configuration choice for these devices depends on the boundary-scan test operations needed, programming requirements, and device combinations. For both boundary-scan test operations and programming through the ispjtag interface, these devices may be put in a chain including non-lattice boundary-scan devices. If a mixed chain programming configuration is used, these devices need to be in ispjtag interface mode. In addition to using good PCB layout practices, including the use of decoupling capacitors between Vcc and ground on each ISP device and minimizing trace lengths wherever possible (Figure 7), additional care must be taken to ensure programming interface signal integrity. A filtering capacitor (.01 µf) must be provided between the ispen signal and ground. This filtering capacitor must be located as close as possible to the ispen pin of the isplsi device that is closest to the ISP connector on the PC board to filter out any noise during programming. During programming, the ispen signal is driven low. Without the capacitor, noise can couple into the ispen signal during programming and corrupt the programming sequence. When long serial daisy chains of devices are used, special consideration must be placed on the MODE/TMS, SCLK/TCK, and ispen signals. These signals are connected in parallel to all devices and may require buffers to be used. No buffer is necessary on the SDI/TDI line since only the first device in the chain is driven. SDI/TDI for each subsequent device is driven from SDO/TDO of the previous device. High speed CMOS (MCMOS) or TTL (AS, ALS) devices may be used as additional buffers. The additional buffers should be placed in parallel in order minimize the timing skew between the programming signals. With additional buffers, it is recommended that a filtering capacitor (.01 µf) be added on the output side of the buffers for the ispen signal along with the filtering capacitor (.01 µf) on the input side of the buffer. The last device in the chain must drive SDO/TDO. The output drive of that device pin should be considered if a long programming cable is used. It may be necessary to add a line driver with a higher current drive to the PCB. ispdownload Cable Reference Manual 17

18 Put in an additional buffer for every eight ISP parts Because SCLK and ispen/bscan are the most sensitive to noise, special care must be taken. Insert an additional buffer when the number of parts exceeds eight, or when trace length is longer than 10 inches. SDI isplsi ispgal 22V10C isplsi SCLK MODE ispen 0.01µF This capacitor eliminates noise from PC parallel port/cable SDO 0.01µF isplsi ispgds/ ispgal 22V10B isplsi 0.01µF This capacitor eliminates noise from ISP devices 5-10K ohm This pulldown ensures ispgds never go into programming mode during normal operation Figure 7. ISP Design Board Layout Considerations

19 Lattice ISP Design Flow ISP programming signal default states must be maintained during normal device operation. The ispen pin on the isplsi 1000/E and isplsi 2000V devices has an internal pull-up to place the devices in normal functional mode when the pin is not driven externally. The ispen/bscan pin on isplsi 3000, isplsi 6000, and ispgdx devices also has an internal pull-up that puts the devices into ispjtag interface mode when the pin is not driven externally. The ispgal22v10b and ispgds device MODE or SDI signals must be tied low through a 1.2 K ohm pull-down resistor during normal functional mode. It is not acceptable to let these pins float during normal operation. However, the ispgal 22V10C devices provide an internal pull-down on SDI to maintain socket compatibility with the standard 22V10 in the PLCC package. ispdownload Cable Reference Manual 19

20 ispdownload Cable The ispdownload cable consists of two primary components: 25-Pin Parallel Port Adapter ispdownload Cable 6 System ispdownload cable with RJ-45 to 8-pin Modular AMP Connector See Figures 8 and 9 for details of ispdownload cable components. The ispdownload cable is designed for engineering purposes only and is not intended for production use. It is not intended for high volume programming environments. Users are strongly urged to insure proper cable operation (e.g. no bent pins, continuity, etc.) before initiation of device programming. To be sure of proper cable operation, check the following items: Vcc of target board within specification of isplsi devices Proper operation of PC Verification of ISP signal waveform on target board meeting specified levels and timing of isplsi devices being programmed Connecting the ispdownload Cable Perform the following steps to connect the ispdownload cable to a printed circuit board. Refer to Figures 8 and 9 for assistance. 1. Connect the parallel port adapter directly behind the security key connected to the parallel port on your PC. 2. After connecting the ispdownload cable RJ-45 modular plug to the back of the parallel port adapter, connect the AMP connector to your printed circuit board that uses Lattice Semiconductor in-system programmable devices. Your system needs to have a matching 0.100" center-to-center spacing 8-pin header, keyed to the cable s AMP connector. Refer to Figure 8 for the location of the ISP signal pinout orientation for the AMP connector and Figure 9 for the male header connector requirement. Before using the cable, refer to the appropriate datasheet for information on device pinouts and read the following descriptions about the cable signals for ISP and ispjtag Chain Interfaces: The VCC and GND pins are used to provide power from your board to a CMOS buffer in the parallel port adapter. During download, the ISP signals SDI/TDI, SCLK/TCK, and MODE/TMS are driven by the buffer in the parallel port adapter. The buffer circuitry requires 3.0V to 5.5V at a maximum of 40mA during programming from the target ISP system. Mixed voltage (3.3V and 5.0V) chains require the lowest voltage device be first in the chain and no more than 3.0V to 3.3V Vcc from the target system. The SDO/TDO signal between your system and the computer s parallel port is buffered by the parallel port adapter. ispdownload Cable Reference Manual 20

21 ispdownload Cable On completion of the download process, the SDI/TDI, SCLK/TCK, and MODE/TMS signals from the cable are placed in a high impedance state. A filtering capacitor (.01 µf) must be provided between the ispen signal and ground. This filtering capacitor must be located as close as possible to the ispen pin of the isplsi device that is closest to the ISP connector on the PC board to filter out any noise during programming. During programming, the ispen signal is driven low. Without the capacitor, noise can couple into the ispen signal during programming and could corrupt the programming sequence. NOTE ispen is not used on all Lattice in-system programmable devices. For example, ispen is not present on the ispgds devices, the ispgal devices, or the ispgal22v10. See the appropriate device data sheet for details. The plugged signal line on the AMP connector is reserved for internal testing and should not be used. The No Connect line on the RJ-45 jack should not be used. ispdownload Cable Reference Manual 21

22 RJ-45 connector eight positions AMP connector.100 center-spacing, eight positions To PC 25-pin parallel port adapter active buffer circuit housing ispen/bscan SDI/TDI SDO/TDO VCC Front view pinout of RJ-45 jack on ISP interface application. No Connect MODE/TMS GND SCLK/TCK VCC SDO/TDO SDI/TDI Front view AMP Connector pinout From Board ispen/bscan Plug Place adapter on parallel port behind security key MODE/TMS GND From Board.01 µf SCLK/TCK capacitor Note: Capacitor required between ispen and GND pins. Locate capacitor as close as possible to ISP device. Note: Capacitor requirement is not necessary for ispgds and ispgal22v10. Figure 8. ispdownload Cable Components

23 Side View Cable Housing Front View Side View 2.087'' 1.690'' RJ-45-8 PAC TEC p/n '' Top View 0.914'' 0.816'' AMP Modular Plug RJ-45 (p/n ) 6' Cable AMP Mod. IV Wire Applied Housing Single Row,.100 Centers 8 positions (p/n ) 6.0'' Pin # Function Vcc (from board) SDO/TDO SDI/TDI ispen/bscan Plug MODE/TMS GND (from board) SCLK/TCK 8-Pin Male Header 0.025'' sq. Pin #5 cut 0.235'' '' AMP Mod. IV Wire Applied Housing Single Row,.100 Centers 8 positions (p/n ) Figure 9. ispdownload Cable Components